CN104752056B - Thin film capacitor - Google Patents

Thin film capacitor Download PDF

Info

Publication number
CN104752056B
CN104752056B CN201410844332.8A CN201410844332A CN104752056B CN 104752056 B CN104752056 B CN 104752056B CN 201410844332 A CN201410844332 A CN 201410844332A CN 104752056 B CN104752056 B CN 104752056B
Authority
CN
China
Prior art keywords
terminal
layer
semiconductor layer
tft
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410844332.8A
Other languages
Chinese (zh)
Other versions
CN104752056A (en
Inventor
戈尔拉玛瑞扎·恰吉
马丽安·莫拉迪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ignis Innovation Inc
Original Assignee
Ignis Innovation Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/245,203 external-priority patent/US9070775B2/en
Application filed by Ignis Innovation Inc filed Critical Ignis Innovation Inc
Publication of CN104752056A publication Critical patent/CN104752056A/en
Application granted granted Critical
Publication of CN104752056B publication Critical patent/CN104752056B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

A kind of thin film capacitor, including：Semiconductor layer；First dielectric layer and the second dielectric layer, the two are arranged in the opposite side of the semiconductor layer；The first metal layer, it forms first terminal and Second terminal in the one side opposite with the semiconductor layer of first dielectric layer, one of the first terminal and Second terminal extend through first dielectric layer and are contacted with the semiconductor layer, and the first terminal and Second terminal form capacitor with first dielectric layer；And second metal layer, form third terminal in the one side opposite with the semiconductor layer of second dielectric layer.The first terminal and Second terminal can be source terminal and drain terminal, and the third terminal can be gate terminal.The first metal layer can be divided into form the first terminal and Second terminal.The third terminal can be shared with one of the first terminal and Second terminal.

Description

Thin film capacitor
Invention field
The present invention relates generally to thin film capacitor.
Background technology
Display can be formed by the array of organic light emitting apparatus (" OLEDs "), and each organic light emitting apparatus is by single Circuit (that is, pixel circuit) controls, these single circuits have the transistor for selectively controlling the circuit, so as to use It shows programming information and is shone according to display information.The thin film transistor (TFT) (" TFTs ") made on substrate can be merged in In these displays.
The reactivity of mobility characterization carrier in the presence of an electric field.Mobility is usually with unit cm2/ V s are represented.For For transistor, the mobility of channel region provides transistor " on " electric current (for example, the electric current can be supplied by transistor) When performance measurement.In thin film transistor (TFT), usually channel region is formed using semiconductor material layer.
The development of OLED display is because receiving and choosing for the demand of suitable driving transistor in pixel circuit War.Switch the non-crystalline silicon of the transistor channel materials of AM-LCD pixels (a-Si) with relatively low mobility as voltage is come from (~0.1cm2V-1s-1).Organic semiconductor channel material because its homogenieity, low cost and the means that can be deposited are various, and It is very suitable for being used as pixel circuit driving transistor, but the optimal mobility of the organic semiconductor channel material and a-Si are moved Shifting rate is similar.In typical TFT structure, low mobility channel layer needs larger source-drain voltages necessary to drive Electric current.Which consumes the electric power (opposite with generating light in OLED) in transistor, impair electric power saving.
P-type a-Si TFT can even have lower mobility value, and can be down to 0.01cm2V-1s-1。
The content of the invention
According to one embodiment, thin film capacitor includes：Semiconductor layer；First dielectric layer and the second dielectric layer, the two cloth It puts in the opposite side of the semiconductor layer；The first metal layer, in the opposite with the semiconductor layer of first dielectric layer One side forms first terminal and Second terminal, one of the first terminal and Second terminal extend through first dielectric Layer and contacted with the semiconductor layer, the first terminal and Second terminal form capacitor with first dielectric layer；And Second metal layer forms third terminal in the one side opposite with the semiconductor layer of second dielectric layer.In a reality It applies in scheme, the first terminal and Second terminal are source terminal and drain terminal, and the third terminal is gate terminal. The first metal layer may be partitioned into form the first terminal and Second terminal.The third terminal can be with the first terminal It is shared with one of Second terminal.
In another embodiment, thin film capacitor includes：Semiconductor layer；First dielectric layer and the second dielectric layer, the two The opposite side of the semiconductor layer is arranged in, at least described second dielectric layer has opening wherein；The first metal layer, in institute The one side opposite with the semiconductor layer for stating the first dielectric layer forms first terminal；And second metal layer, described The one side opposite with the semiconductor layer of two dielectric layers forms Second terminal, and the second metal layer extends through described second The opening in dielectric layer and contacted with the semiconductor layer.
In view of the detailed description of various embodiments and/or aspect, aspect and another aspect and implementation above of the invention Example will become obvious for those of ordinary skill in the art, and described be described in detail is refer to the attached drawing to carry out, Next the summary of the attached drawing is provided.
Description of the drawings
After described in detail below and refer to the attached drawing is read, of the invention will become aobvious and easy with further advantage above See.
Fig. 1 illustrates the block diagrams of the bottom gate thin film transistor with the channel region including nanoconductor layer.
Fig. 2 illustrates the block diagram of the top-gated electrode film transistor with the channel region for including nanoconductor layer.
Fig. 3 A are the cross-sectional views of the thin film transistor (TFT) 100 with the channel region for including nanoconductor layer.
Fig. 3 B are similar with the thin film transistor (TFT) shown in Fig. 3 A but thin film transistor (TFT) with shorter nanoconductor layer show It is intended to.
Fig. 4 A are the nanoconductor layers of the characteristic length with the interval between the drain terminal and source terminal more than TFT Schematic top plan view.
Fig. 4 B are the schematic top plan views of the nanoconductor layer similar with Fig. 4 A, but the wherein single incomplete edge of nanometer conductor Direction alignment from drain terminal to source terminal.
Fig. 4 C are the schematic top plan views of the nanoconductor layer similar with Fig. 4 A, but the characteristic length of wherein nanoconductor layer is small Interval between the drain terminal and source terminal of TFT.
Fig. 5 is the instantiation procedure illustrated for manufacturing the thin film transistor (TFT) with the channel region for including nanoconductor layer Flow chart.
Fig. 6 is the diagrammatic cross-section of the thin film transistor (TFT) with the channel region for including nanoconductor layer.
Fig. 7 is a pair of of sectional view of two kinds of typical metal-insulator-metal (MIM) capacitors.
Fig. 8 is the sectional view of the structure with high capacity.
Fig. 9 is the plan view of structure shown in Fig. 8.
Figure 10 is the sectional view of the mapped structure with high capacity.
Although the present invention easily has various changes and alternative form, this hair is shown in the accompanying drawings by way of example Bright specific embodiment is simultaneously herein described in detail it.It will be appreciated, however, that the present invention is not intended to be limited to institute Disclosed particular form.In fact, the present invention will cover belong to the present invention following claims limited spirit and In the range of all modifications, equivalent and alternative form.
Specific embodiment
Fig. 1 illustrates the block diagrams of the bottom gate thin film transistor 10 with the channel region 31 including nanoconductor layer 20.It is thin Film transistor 10 can usually be formed by the deposition on the substrate 12 of display or similar procedure.For example, substrate 12 can be backplane substrate or packaged glass substrate or provide the suitable lining of another kind on the surface that can generate TFT 10 thereon Bottom.Gate terminal 14 is formed on the substrate 12.Gate terminal 14 is to operate the conductive electrode of TFT 10 for receiving signal.It applies The signal being added on gate terminal 14 can be turned on and off binary system " height " signal of TFT 10 or binary system " low " signal, Or can be the signal in multiple level of the quantity for the electric current that control is conveyed by drain terminal and source terminal.
Dielectric layer 16 (" insulating layer ") is generated in the top of gate terminal 14, to prevent electric current from flowing to 14 He of gate terminal The channel region 31 of TFT 10 prevents the channel region 31 of electric current from gate terminal 14 and TFT 10 from flowing.Deposition process can be passed through To generate dielectric layer 16.Then the layer (that is, nanoconductor layer 20) of nanometer conductor is placed into (" positioning ") on dielectric layer 16.It receives Rice conductor layer 20 generally includes multiple nanometers of conductors and can include nano wire, nanofiber and/or such as single-walled nanotube The nanotube of (" SWNT "), double-walled nanotubes (" DWNT ") and/or many walls nanotube (" MWNT ").Nanometer conductor can be by carbon And/or silicon is formed, and dopant material can be optionally incorporated into change the electric conductivity of nanometer conductor.Nanoconductor layer 20 can To be the simple layer (that is, individual layer) of nanometer conductor.
Semiconductor layer 30 is generated above nanoconductor layer 20.Semiconductor layer 30 and nanoconductor layer 20 form TFT together 10 double-deck channel region 31.For example, semiconductor layer 30 can be made of organic semiconducting materials or inorganic semiconductor material.Example Such as, semiconductor layer 30 can be formed by non-crystalline silicon or polysilicon.Semiconductor layer 30 can also be incorporated to dopant to change TFT 10 Mobility characteristics.
Then the drain terminal 32 of TFT and source terminal 34 are formed on the semiconductor layer.Drain terminal 32 and source terminal Each conductive material for being freely suitable for conveying electric energy of son 34 is formed.For example, terminal 32,34 can be metallicity.Drain terminal The distance between 32 and source terminal 34 define raceway groove spacing distance.The raceway groove spacing distance is the operability for influencing TFT 10 One parameter of energy.
Since grid 14 is formed directly on substrate 12, so TFT 10 is known as bottom-gate TFT, so as to grid 14 The one side of TFT 10 be known as the bottom side of TFT 10, and the one side of the TFT 10 with drain terminal 32 and source terminal 34 is known as The top side of TFT 10.
Fig. 2 illustrates the block diagram of the top-gated electrode film transistor 40 with the channel region 31 for including nanoconductor layer 20.Top Grid TFT 40 is by applying the layered component relatively discussed with the bottom-gate TFT 10 shown in Fig. 1 in reverse order To manufacture.Drain terminal 32 and source terminal 34 are each formed on the substrate 12.Then semiconductor layer 30 is deposited on drain electrode end On son 32 and source terminal 34.Then nanoconductor layer 20 is applied to semiconductor layer 30 to form double-deck channel region 31.Pass through Nanoconductor layer 20 is applied to the surface of the semiconductor layer 30 opposite with drain terminal 32 and source terminal 34, nanoconductor layer 20 are oriented not contact directly there are any with drain terminal 32 and source terminal 34.Therefore, (example is operated in low field effect Such as, low grid-source voltage) during, the performance of TFT dominates by semiconductor layer, this is because the nanometer conductor not source with TFT Extreme son or drain terminal are contacted directly there are any.TFT thus provides similar with the performance of semiconductor layer 30 good let out Leakage current characteristic.Then dielectric layer 16 is generated in the nanometer conductor side of channel region 31, and gate terminal 14 is formed in dielectric On layer 16.
In addition, nanometer conductor nanoconductor layer can change the polarity of TFT device.For example, carbon nanotubes has p-type spy Property.Therefore, non-crystalline silicon (a-Si) TFT for being formed with the channel region including carbon nanotubes can have p-type characteristic.It is thusly-formed P-type a-Si TFT, and can be greatly because of the mobility of the enhancing of this p-type transistor under compared with conventional p-type TFT It is beneficial to a-Si TFT applications.The mobility of the enhancing of this p-type transistor under compared with conventional p-type TFT can have This p-type a-Si TFT is made to be used in the displayer application previously dominated by n-type TFT sharply, so as to allow p-type Image element circuit structure.
Fig. 3 A are the cross sections of the thin film transistor (TFT) 110 (" TFT ") with the channel region 131 for including nanoconductor layer 120 Schematic diagram.In schematic diagram in figure 3 a, the component of TFT 110 is composed of the corresponding assembly of TFT 10 in the block diagram than Fig. 1 The reference number of reference number big 100.TFT 110 is formed on substrate 112, the substrate 112 can be such as backplane substrate, The substrate of the displays such as transparent planar substrate or packaged glass substrate.Gate terminal 114 is formed on substrate 112.Gate terminal 114 can be the conducting terminal with the characteristic similar with the characteristic for the gate terminal 14 that Fig. 1 is relatively described.In gate terminal Dielectric layer 116 is generated on 114 so that the channel region 131 of gate terminal 114 and TFT 110 insulate.Dielectric layer 116 can be electric exhausted Edge body.
There are two layers for the tool of channel region 131 of TFT：Nanoconductor layer 120 and semiconductor layer 130.Semiconductor layer 130 makes nanometer Conductor layer 120 avoids contacting directly with drain terminal 132 or source terminal 134.Nanoconductor layer 120 generally includes a plurality of receive Rice noodles, a plurality of nanofiber and/or more nanotubes.By the single nanometer conductor (" nano particle ") in nanoconductor layer 120 It is placed in the film on dielectric layer 116.Single nanometer conductor is each desirably along from drain terminal 132 to source terminal 134 Direction general alignment, to increase the effect of the electric charge transfer between drain terminal 132 and source terminal 134.
Fig. 3 B are thin film transistor (TFT)s similar with the thin film transistor (TFT) illustrated in Fig. 3 A but with shorter nanoconductor layer 121 111 schematic diagram.Schematic diagram in Fig. 3 B shows that drain terminal 132 and source terminal 134 can be with different quantity with receiving Rice conductor layer 121 is overlapped.By along from drain terminal 132 to the size of the direction of source terminal 134 adjusting nanoconductor layer 121 Degree can change the charge transfer characteristic of double-deck channel region 131.For example, double-deck channel region 131 can be led by increasing nanometer The size degree (for example, length) of body layer 121, the density by increasing the nanometer conductor in nanoconductor layer 121 and/or pass through Increase with the overlapping quantity of drain terminal 132 and/or source terminal 134 to provide relatively large number of electric charge transfer (for example, increasing Mobility).As described herein, the overlapping quantity between nanoconductor layer 121 and drain terminal 132 and source terminal 134 refers to Be to come and 121 separated 132/ source terminal of drain terminal of nanoconductor layer only by pass through the vertical-path of semiconductor layer 130 The surface area quantity of son 134.In Fig. 3 A and Fig. 3 B, the vertical direction through semiconductor layer 130 is outwards perpendicular to substrate 112 Direction.
The many aspects of the present invention further provide for, and nanoconductor layer 121 can be along from drain terminal 132 to source terminal 134 direction is configured with size degree not Chong Die with any one of drain terminal 132 or source terminal 134.For example, it receives The length of rice conductor layer 121 can be less than the spacing distance between drain terminal 132 and source terminal 134.Pass through Fig. 4 A to figure The additional configuration of nanoconductor layer 121 of schematic top plan view general illustration in 4C.
Fig. 4 A are the nanoconductor layers of the characteristic length with the interval between the drain terminal and source terminal more than TFT Schematic top plan view.Although for illustrative purposes, with uniform length and each comfortable drain terminal 32 and source terminal 34 Between the single nanometer conductor (for example, nanometer conductor 21,22) that aligns show nanoconductor layer 20, but the present invention is not limited to This.The many aspects of the present invention, which are suitable for nanoconductor layer 20, to be had length and orients matching somebody with somebody for inhomogenous single nanometer conductor It puts.The schematic diagram of nanoconductor layer 20 in Fig. 4 A also illustrates that single nanometer conductor (for example, nanometer conductor 21,22) is with list Layer arrangement.Nanoconductor layer 20 can be point of the nanometer conductor for the complete cross section product for not covering all double-deck channel region Throwaway layer.For example, the gap between single nanometer conductor (for example, nanometer conductor 21,22) substantially can be with nanometer conductor from The size that body is of same size, so that single nanometer conductor (for example, the nanometer conductor 21,22) accumulation in nanoconductor layer 20 is covered Cover the double-deck channel region of approximate half (for example, 50%).In one example, single nanometer conductor is (for example, nanometer conductor 21st, 22) between any gap all filled by the semiconductor layer for being deposited on the top of nanoconductor layer 20.It can be big in coverage In or less than 50% coverage (such as, 30% coverage or 70% coverage) in the case of perform nanoconductor layer 20.Usually, the electric charge transfer spy of double-deck channel region can be enhanced by increasing the density (that is, coverage rate) of nanometer conductor individual layer Property.
In Fig. 4 A to Fig. 4 C, the Hash block for being denoted as " D " and " S " represents drain terminal 32 and source terminal 34 respectively Position.Drain terminal 32 has raceway groove side 33, and source terminal 34 has raceway groove side 35.For convenience, can will drain The distance between the raceway groove side 33 of terminal 32 and the raceway groove side 35 of source terminal 34 are known as raceway groove spacing distance.Such as institute in Fig. 4 A To show, the length of nanoconductor layer 20 can be more than the raceway groove spacing distance between drain terminal 32 and source terminal 34, so that Drain terminal 32 and source terminal 34 are each Chong Die at least a portion of nanoconductor layer 20.By making nanoconductor layer 20 At least a portion is be overlapped with 32/ source terminal 34 of drain terminal, and nanoconductor layer 20 advantageouslys allow for hanging down through semiconductor layer Straight connection path enhances the charge transfer characteristic of double-deck channel region.
Fig. 4 B are the schematic top plan views of the nanoconductor layer similar with Fig. 4 A, but wherein single nanometer conductor is (for example, nanometer 23) conductor 21 does not align along the direction that source terminal 34 is directed to from drain terminal 32 completely.Due to nanoconductor layer 20 simultaneously Being not directly connected to any one of 32/ source terminal 34 of drain terminal, (that is, nanoconductor layer 20 is only connected to by semiconductor layer Drain terminal/source terminal), thus the charge transfer characteristic of double-deck channel region to single nanometer conductor (for example, nanometer conductor 23) Accurate align requirement relative insensitivity.Therefore, nanometer conductor (for example, nanometer conductor 21,23) is usually partly led by passing through Body layer delivered charge is to 32/ source terminal 34 of drain terminal or from 32/ source terminal of drain terminal, 34 delivered charge through partly leading Body layer enhances the effective mobility of double-deck channel region, so that the charge transfer characteristic of thin film transistor (TFT) is not only restricted to semiconductor The mobility of layer.
Fig. 4 C are the schematic top plan views of the nanoconductor layer similar with Fig. 4 A, but the characteristic length of wherein nanoconductor layer is small Interval between the drain terminal and source terminal of TFT.In schematic diagram in figure 4 c, single nanometer conductor is (for example, nanometer 25) conductor 24 is illustrated as the length with less than raceway groove spacing distance.In the configuration illustrated in figure 4 c, nanoconductor layer 20 It is not Chong Die with any one of drain terminal 32 or source terminal 34.Therefore, led from 32/ source terminal 34 to nanometer of drain terminal Charge transfer path is not present in body layer 20, and the vertical electric charge that the charge transfer path is only included through semiconductor layer shifts road Footpath.For example, in the configuration shown in figure 4 c, the effective mobility of double-deck channel region may be subject to charge horizontal transfer to pass through Requirement limitation.
Fig. 5 is to illustrate to manufacture showing for thin film transistor (TFT) (" TFT ") with the channel region for including nanoconductor layer The flow chart 50 of example process.In first step 51, the gate terminal of TFT is formed on substrate.Then, in step 52 Dielectric layer is generated on gate terminal 54.The dielectric layer backpack cover lives the exposed surface of gate terminal, to prevent what is next deposited Double-deck channel region contacts directly gate terminal.In step 53, the nanometer conductor dispersion layer of such as nanotube or nano wire is determined Position is on the dielectric layer.It is such as relatively discussed with Fig. 3 A to Fig. 3 B, nanometer conductor dispersion layer can be do not cover channel region complete The individual layer of portion's exposed area.In step 54, semiconductor layer is deposited on to any exposed region of nanoconductor layer and dielectric layer On.Semiconductor layer can include non-crystalline silicon.Therefore, double-deck channel region is collectively formed in semiconductor layer and nanoconductor layer.Then exist In step 55, source terminal and drain terminal are formed on the semiconductor layer.Source terminal and drain terminal be formed such from Without being directly connected to nanometer conductor.
Flow chart 50 is for manufacturing the embodiment of the process of bottom-gate TFT (that is, gate terminal being deposited on substrate). However, it is possible to manufacture top-gated pole TFT using similar process, top-gated pole TFT, which has to be incorporated to, is not directly contacted with drain terminal Or the double-deck channel region of the nanometer conductor of source terminal, all top-gated pole TFT 40 as shown in Figure 2.For example, drain terminal and Source terminal can be formed on substrate.Semiconductor layer can be deposited on to the top of drain terminal and source terminal, and can Nanoconductor layer to be placed on to the top of semiconductor layer, so as to form double-deck channel region.It can be by dielectric layer deposition in bilayer The top of channel region, and gate terminal can be formed on the dielectric layer.
Fig. 6 illustrates the structure of change, and wherein source metal and drain terminal 61 and 62 are (for example, thickness is about 100 nanometers Aluminium) it is formed on the respective layer 63 and 64 of p+ silicon (for example, thickness is about 35 nanometers).What it is immediately in 63 and 64 lower section of layer is half Conductor material (for example, alternate nanocrystal silicon and non-crystalline silicon that overall thickness is about 30 nanometers) layer 65, the semiconductor material layer 65 are deposited on such as nanoconductor layer 66 of carbon nanotubes (for example, thickness is about 1 to 2 nanometer).Nanometer conductor is sunk It accumulates on dielectric layer 67 (for example, thickness is about 100 nanometers of thermal silicon dioxide), and by the dielectric layer deposition in substrate 68 On (for example, p+ silicon).The bottom surface of substrate 67 is covered with conducting back contact 69 (for example, thickness is about 100 nanometers of aluminium).
It is as follows for forming the example process of the structure shown in Fig. 6：
1. hot P+Silicon substrate cleans
(a) then the ultrasonic cleaning that substrate is made to carry out in acetone 10 minutes carries out other 10 in isopropanol (IPA) The ultrasonic cleaning of minute.This process is repeated twice.
(b) substrate is rinsed with deionized water and is dried with nitrogen.
Pay attention to：It is placed the substrate in before next step on electric furnace (~90 DEG C) and continues 10 minutes.
2. carbon nanotubes is coated with
(a) substrate is handled using aminopropyl triethoxysilane (APTES).
Before the coating, immerse the substrate in APTES solution (the IPA solution of 1%v/v) 20 minutes, then with IPA to institute Substrate is stated to be rinsed and be dried with nitrogen.
(b) by carbon nanotubes dip-coating on the substrate by APTES processing.
It immerses the substrate in carbon nano-tube solution 15 minutes.Then with sufficient deionized water substrate is rinsed and It is dried with nitrogen.
The substrate for being coated with carbon nanotubes is toasted 20 minutes on 180 DEG C of electric furnaces, load it into afterwards etc. from In son enhancing chemical vapor deposition (PECVD) system.
3. use PECVD deposition nanocrystal silicons (nc-Si) and non-crystalline silicon SiNx。
(a) nc-Si (~30nm.)
Gas：SiH4/H2=40/200sccm；Pr=900mtorr；RF=2W；T=210C (setting)；Rate= 4.07nm/min。
(b)SiNx(150nm)
Gas：SiH4/NH3/N2=5/100/50sccm；Pr=1000mtorr；RF=15W；T=250C (setting)；Speed Rate=15nm/min.
4. via the SiN of (mask #1)x
(a) photoetching process
Photoresist：NLOF 2035
Rotation：10 seconds 500rpm, then 90 seconds 4000rmp.
Soft baking：Continue 1 minute at 110 DEG C.
Contact：Low vacuum.
Exposure：5.4 the second.
Postexposure bake：110℃.
Development：The AZ300MIF of~30 seconds.
(b) buffered hydrofluoric acid (BHF) wet etching SiN is usedx。
It immerses the substrate in BHF solution (10%v/v) 27 seconds.
(c) stripping of photoresist
It immerses the substrate in AZ KWIT removers 10 minutes, then by deionized water, acetone and IPA come to the lining Bottom is rinsed.
5.P+Deposition (~35nm is thick)
Gas：SiH4/B2H6/H2=1.8/1.8/200sccm；Pr=1500mtorr；RF=65W；T=250C (is set It is fixed)；Rate=7.7nm/min.
6.S/D metal deposits (aluminium ,~100nm are thick)
7.S/D patterns (mask #1 ')
Photoresist：AZ 3312
Rotation：10 seconds 700rpm, then 60 seconds 4000rmp.
Soft baking：Continue 1 minute at 90 DEG C.
Contact：Low vacuum.
Exposure：4 seconds.
Postexposure bake：Continue 1 minute at 120 DEG C.
Development：The AZ300MIF of~15 seconds.
Etching：At room temperature in PAN etch agent~3 minutes.
It removes：It is rinsed 4 minutes in AZ KWIT removers, then with deionized water, acetone and IPA come to the substrate It is rinsed.
8. S/D metals are separated into P as hardmask+。
RIE dry etching P+ silicon：
RF=50W；Pr=20mtorr；CF4/H2=20/3sccm；Rate=~0.43nm/s
9. device separates and isolation (mask #2)
(a) photoetching process
Photoresist：AZ 3312
Rotation：10 seconds 700rpm, then 60 seconds 4000rmp.
Soft baking：Continue 1 minute at 90 DEG C.
Contact：Low vacuum.
Exposure：4 seconds.
Postexposure bake：Continue 1 minute at 120 DEG C.
Development：The AZ300MIF of~15 seconds.
(b) dry etching SiNx/ Si/ carbon nanotubes.
RF=125W；Pr=150mtorr；CF4/O2=43/5sccm；Rate=~4nm/s.
10. backside contacts metal deposit (aluminium ,~100nm are thick)
(a) back thermal oxide is removed.
The wafer front side by PR AZ3312 is protected, afterwards immerses it in BHF (10%v/v) 4 minutes.
(b) metal deposit is in the rear side of wafer.
After by BHF, the thermal oxide of wafer backside is removed, wafer is loaded into immediately in vacuum chamber so as into Row metal deposits.
Fig. 7~10 illustrate thin film capacitor, which includes：Semiconductor layer, with controllable resistor；First Dielectric layer and the second dielectric layer, the two are arranged in the opposite side of the semiconductor layer；The first metal layer, in first dielectric The one side opposite with the semiconductor layer of layer forms first terminal；Second metal layer, in second dielectric layer and institute It states the opposite one side formation Second terminal of semiconductor layer and third terminal, the third terminal extends through second dielectric layer And contacted with the semiconductor layer, the Second terminal is not contacted with the semiconductor layer；And voltage source, with described second One of terminal and third terminal couple to reduce the resistance of the semiconductor layer, and in the Second terminal and third terminal Another one and the semiconductor layer form capacitor.The Second terminal and third terminal can be source terminal and drain electrode end Son, and the first terminal can be gate terminal.The second metal layer can be divided into form the Second terminal and Three terminals, and the first terminal can be shared with one of the Second terminal and third terminal.The Second terminal and Three terminals can connect into and form capacitor between the semiconductor layer and the Second terminal and third terminal.Switch voltage Power supply may be connected to the terminal of thin film capacitor.
In the figure 7, semiconductor layer and at least one of two metal layers of opposite side positioned at the semiconductor layer it Between form capacitor.Each metal layer is separated by dielectric layer and semiconductor layer.Main challenge is that semiconductor is very resistance Property, and therefore, will be higher with carrying out charging associated RC retardation ratio to capacitor, this causes lower frame per second or hysteresis.
In order to avoid high RC retardation ratio, as shown in FIG. 8 and 9, three termination capacitors have been used.Positioned at semiconductor layer one side The first metal layer is separated by the first dielectric layer and semiconductor layer and forms to control the first end of the resistivity of semiconductor layer Sub- A.Second metal layer positioned at semiconductor layer opposite side is separated by the second dielectric layer with semiconductor layer.The second metal layer quilt Segmentation is shaped as Second terminal B and third terminal C, so as to form capacitor between terminal B and terminal C.Terminal C is extended through Second dielectric layer with semiconductor layer to contact.
In one example, terminal A is low in panel or high voltage transmission line is connected, this depends on the type (example of semiconductor Such as, it is low high for p-type to be used for n-type).In the case, significantly reduce and partly lead by charge accumulation (or consumption) Body layer resistance.In another example, terminal A is shared with another terminal (B or C).In the case, one of these terminals have The voltage of the resistance of semi-conducting material is reduced, this depends on the type of semiconductor.
In figs. 8 and 9, between terminal C and semiconductor layer tool there are two contact site, but a contact site or two with Upper contact part is also possible (this depends on usable area).
The order of layer can change, and Fig. 8 and 9 shows an example of 3 termination capacitors.
Voltage on the control terminal of capacitor can be fixed voltage or switching voltage.In the case where switching voltage, The RC retardation ratio that charge or discharge are carried out to capacitor can be controlled.For example, can be used during charging to capacitor reduces The voltage of RC retardation ratio, and then using the voltage for hold period that capacitance is made to become more stable.In the case, capacitance Characteristic because of high voltage difference bias stress without occurring significant changes.
Figure 10 is shown provides the another of high capacity in the case where not increasing additional processing step to manufacturing process Structure.Since the second dielectric substance 2 is generally thicker than semiconductor layer, so the conventional method ratio of the dielectric substance with stacking uses stacking Semiconductor and dielectric substance cause smaller capacitor.Here, the second dielectric substance is etched, during this period to the dielectric layer It is patterned, and then, is deposited as contacting with semiconductor layer through the opening in pattern for the metal of electrode B.In order to It, can connection electrode B and electrode A as follows with consistent capacitance：The voltage at two electrode As and B both ends be always above or Less than the threshold voltage of established metal-insulator semiconductor capacitor.Therefore, semiconductor layer will always be used as insulator Or conductor layer.
Although having shown that and describing specific embodiments of the present invention and application, it is to be understood that, the present invention is not limited to Accurate construction and composition disclosed herein, and the spirit and model limited in the following claims without departing from the present invention In the case of enclosing, various changes, change and variation can become apparent according to being described above.

Claims (6)

1. a kind of thin film capacitor, including：
Semiconductor layer, with controllable resistor；
First dielectric layer and the second dielectric layer, the two are arranged in the opposite side of the semiconductor layer；
The first metal layer forms first terminal in the one side opposite with the semiconductor layer of first dielectric layer；
Second metal layer forms Second terminal and the 3rd in the one side opposite with the semiconductor layer of second dielectric layer Terminal, the third terminal extend through second dielectric layer and are contacted with the semiconductor layer, the Second terminal not with The semiconductor layer contact；And
Voltage source, and one of the first terminal and the Second terminal coupling, to reduce the electricity of the semiconductor layer Resistance, and the other of the first terminal and the Second terminal form capacitor with the semiconductor layer.
2. thin film capacitor as described in claim 1, wherein, the Second terminal and the third terminal be source terminal and Drain terminal, and the first terminal is gate terminal.
3. thin film capacitor as described in claim 1, wherein, the second metal layer is divided into form the Second terminal With the third terminal.
4. thin film capacitor as described in claim 1, wherein, the first terminal and the Second terminal and the 3rd end One of son shares.
5. thin film capacitor as described in claim 1, wherein, the Second terminal is connected with the first terminal, and in institute It states and forms capacitor between semiconductor layer and the first terminal and the Second terminal.
6. thin film capacitor as described in claim 1, wherein, the power supply for switching voltage is connected to the end of the thin film capacitor Son.
CN201410844332.8A 2013-12-30 2014-12-30 Thin film capacitor Active CN104752056B (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201361921912P 2013-12-30 2013-12-30
US61/921,912 2013-12-30
US201461931778P 2014-01-27 2014-01-27
US61/931,778 2014-01-27
US14/245,203 2014-04-04
US14/245,203 US9070775B2 (en) 2011-08-03 2014-04-04 Thin film transistor

Publications (2)

Publication Number Publication Date
CN104752056A CN104752056A (en) 2015-07-01
CN104752056B true CN104752056B (en) 2018-06-05

Family

ID=53372334

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410844332.8A Active CN104752056B (en) 2013-12-30 2014-12-30 Thin film capacitor

Country Status (2)

Country Link
CN (1) CN104752056B (en)
DE (1) DE102014227034A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1041061A (en) * 1988-09-07 1990-04-04 李钊华 Piezocapacitor
CN1871675A (en) * 2003-08-20 2006-11-29 波尔伊克两合公司 Organic capacitor having a voltage-controlled capacitance

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101032027B (en) * 2004-09-02 2010-10-13 卡西欧计算机株式会社 Thin film transistor and its manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1041061A (en) * 1988-09-07 1990-04-04 李钊华 Piezocapacitor
CN1871675A (en) * 2003-08-20 2006-11-29 波尔伊克两合公司 Organic capacitor having a voltage-controlled capacitance

Also Published As

Publication number Publication date
DE102014227034A1 (en) 2015-07-02
CN104752056A (en) 2015-07-01

Similar Documents

Publication Publication Date Title
CN102983176B (en) Thin film transistor (TFT) including nanoconductor layer
US9070775B2 (en) Thin film transistor
KR101943595B1 (en) Active matrix dilute source enabled vertical organic light emitting transistor
US8586979B2 (en) Oxide semiconductor transistor and method of manufacturing the same
CN106098726A (en) Oganic light-emitting display device and the method manufacturing oganic light-emitting display device
Marrs et al. Control of threshold voltage and saturation mobility using dual-active-layer device based on amorphous mixed metal–oxide–semiconductor on flexible plastic substrates
US20110101302A1 (en) Wafer-scale fabrication of separated carbon nanotube thin-film transistors
CN106601778A (en) OLED backboard and manufacturing method thereof
KR20070014955A (en) Nano material arraying apparatus, arraying method of nano material using the same, and fabricating method of liquid crystal display device using the same
US10008605B2 (en) Connecting structure and method for manufacturing the same, and semiconductor device
CN110164914A (en) Semiconductor devices, display panel, display device and manufacturing method
Lin et al. Fabrication of high-performance ZnO thin-film transistors with submicrometer channel length
CN110233156A (en) The production method and thin film transistor base plate of thin film transistor base plate
US8658461B2 (en) Self aligned carbide source/drain FET
CN106298815A (en) Thin film transistor (TFT) and preparation method thereof, array base palte and display device
US10141407B2 (en) Graphene device and method of manufacturing the same
CN114068703B (en) Transistor and preparation method
CN104752056B (en) Thin film capacitor
CN101673753A (en) Piezoelectric transistor and method of manufacturing same
Geng et al. 29.3: High Resolution Flexible AMOLED with Integrated Gate‐Driver using Bulk‐Accumulation a‐IGZO TFTs
KR100966007B1 (en) Room Temperature operating Single Electron Device using Carbon Nano Tube and Fabrication Method thereof
CN110993600B (en) ESD protection structure, manufacturing method of ESD protection structure and display device
TWI523239B (en) Thin-film transistor and a method for fabricating the same
KR20040050588A (en) Single electron device, Method of manufacturing the same and Method of manufacturing Single electron device and MOS transistor simulataneously
Wang et al. Low temperature Ni-nanocrystals-assisted hybrid polycrystalline silicon thin film transistor for non-volatile memory applications

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant