CN104752056A - Thin film transistor - Google Patents

Thin film transistor Download PDF

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Publication number
CN104752056A
CN104752056A CN201410844332.8A CN201410844332A CN104752056A CN 104752056 A CN104752056 A CN 104752056A CN 201410844332 A CN201410844332 A CN 201410844332A CN 104752056 A CN104752056 A CN 104752056A
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China
Prior art keywords
terminal
layer
semiconductor layer
nanoconductor
dielectric layer
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Granted
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CN201410844332.8A
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CN104752056B (en
Inventor
戈尔拉玛瑞扎·恰吉
马丽安·莫拉迪
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Ignis Innovation Inc
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Ignis Innovation Inc
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Priority claimed from US14/245,203 external-priority patent/US9070775B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Abstract

A thin film transistor comprises a semiconductor layer; first and second dielectric layers disposed on opposite sides of the semiconductor layer; a first metal layer forming first and second terminals on the opposite side of the first dielectric layer from the semiconductor layer, one of said first and second terminals extending through said first dielectric layer into contact with the semiconductor layer, the first and second terminals and the first dielectric layer forming a capacitor; and a second metal layer forming a third terminal on the opposite side of the second dielectric layer from the semiconductor layer. The first and second terminals may be source and drain terminals, and the third terminal may be a gate terminal. The first metal layer may be divided to form the first and second terminals. The third terminal may be shared with one of the first and second terminals.

Description

Film capacitor
Invention field
The present invention relates generally to film capacitor.
Background technology
Display can be formed by the array of organic light emitting apparatus (" OLEDs "), each organic light emitting apparatus by single circuit (namely, image element circuit) control, these single circuit have the transistor for optionally controlling described circuit, thus with showing programming information and coming luminous according to display information.The thin-film transistor (" TFTs ") be produced on substrate can be merged in these displays.
Mobility characterizes charge carrier reactivity in the presence of an electric field.Mobility is usually with unit cm 2/ V s represents.For transistor, the tolerance of the performance when mobility of channel region provides transistor " connection " electric current (such as, this electric current can be supplied by transistor).In thin-film transistor, usually utilize semiconductor material layer to form channel region.
The development of OLED display is because receive challenge for the demand of suitable driving transistors in image element circuit.To the amorphous silicon (a-Si) switching the transistor channel materials of AM-LCD pixel, there is lower mobility (~ 0.1cm as coming from voltage 2v -1s -1).Organic semiconductor channel material because of its homogenieity, low cost and the means that can carry out depositing various, and be extremely suitable as image element circuit driving transistors, but the best mobility of described organic semiconductor channel material is similar to the mobility of a-Si.In typical TFT structure, low mobility channel layer needs larger source-drain voltages to drive necessary electric current.Which consumes electric power in transistor (with to produce light in OLED contrary), impair electric power and save.
P type a-Si TFT even can have lower mobility value, and can be low to moderate 0.01cm 2v -1s -1.
Summary of the invention
According to an embodiment, film capacitor comprises: semiconductor layer; First dielectric layer and the second dielectric layer, the two is arranged in the opposition side of described semiconductor layer; The first metal layer, it forms the first terminal and the second terminal in the side contrary with described semiconductor layer of described first dielectric layer, described the first terminal and the one in the second terminal extend through described first dielectric layer and contact with described semiconductor layer, and described the first terminal and the second terminal and described first dielectric layer form capacitor; And second metal level, it forms the 3rd terminal in the side contrary with described semiconductor layer of described second dielectric layer.In one embodiment, described the first terminal and the second terminal are source terminal and drain terminal, and described 3rd terminal is gate terminal.Described the first metal layer may be partitioned into and forms described the first terminal and the second terminal.Described 3rd terminal can share with the one in described the first terminal and the second terminal.
In another embodiment, film capacitor comprises: semiconductor layer; First dielectric layer and the second dielectric layer, the two is arranged in the opposition side of described semiconductor layer, and at least described second dielectric layer has opening wherein; The first metal layer, it forms the first terminal in the side contrary with described semiconductor layer of described first dielectric layer; And second metal level, it forms the second terminal in the side contrary with described semiconductor layer of described second dielectric layer, and described second metal level extends through the described opening in described second dielectric layer and contacts with described semiconductor layer.
In view of the detailed description of various embodiment and/or aspect, aspect above of the present invention and other aspect and embodiment will become apparent for the person of ordinary skill of the art, described detailed description is carried out with reference to accompanying drawing, next provides the summary of described accompanying drawing.
Accompanying drawing explanation
To describe in detail and after reference accompanying drawing reading is following, of the present inventionly will to become apparent with other advantage above.
Fig. 1 illustrates the block diagram of the bottom gate thin film transistor with the channel region comprising nanoconductor layer.
Fig. 2 illustrates the block diagram of the top grid thin-film transistor with the channel region comprising nanoconductor layer.
Fig. 3 A is the cross sectional representation of the thin-film transistor 100 with the channel region comprising nanoconductor layer.
Fig. 3 B is similar with the thin-film transistor shown in Fig. 3 A but has the schematic diagram of the thin-film transistor of shorter nanoconductor layer.
Fig. 4 A is the schematic top plan view of the nanoconductor layer of the characteristic length with the interval be greater than between the drain terminal of TFT and source terminal.
Fig. 4 B is the schematic top plan view with nanoconductor layer like Fig. 4 category-A, but wherein single nanometer conductor does not align along the direction from drain terminal to source terminal completely.
Fig. 4 C is the schematic top plan view with nanoconductor layer like Fig. 4 category-A, but wherein the characteristic length of nanoconductor layer is less than the interval between the drain terminal of TFT and source terminal.
Fig. 5 be a diagram that the flow chart of the instantiation procedure for the manufacture of the thin-film transistor with the channel region comprising nanoconductor layer.
Fig. 6 is the generalized section of the thin-film transistor with the channel region comprising nanoconductor layer.
Fig. 7 is a pair sectional view of two kinds of typical metal-insulator-metal (MIM) capacitors.
Fig. 8 is the sectional view of the structure with high capacity.
Fig. 9 is the plane graph of the structure shown in Fig. 8.
Figure 10 is the sectional view of the mapped structure with high capacity.
Although the present invention easily has various change and alternative form, mode shows specific embodiments of the invention in the accompanying drawings and has done detailed description to it in this article by way of example.But, should be appreciated that the present invention is not intended to be limited to particular forms disclosed.In fact, the present invention will cover all amendment belonged in spirit and scope that following claims of the present invention limits, equivalent and alternative form.
Specific embodiment
Fig. 1 illustrates the block diagram of the bottom gate thin film transistor 10 with the channel region 31 comprising nanoconductor layer 20.Thin-film transistor 10 can be formed by the deposition on the substrate 12 of display or similar procedure usually.Such as, substrate 12 can be backplane substrate or packaged glass substrate, or provides the substrate that the another kind on the surface that it can generate TFT 10 is suitable.Gate terminal 14 is formed on the substrate 12.Gate terminal 14 is to operate the conductive electrode of TFT 10 for Received signal strength.The signal be applied on gate terminal 14 can be binary system " height " signal or binary system " low " signal of opening or closing TFT 10, can be maybe the signal being in multiple level of the quantity controlling the electric current carried by drain terminal and source terminal.
Above gate terminal 14, generate dielectric layer 16 (" insulating barrier "), prevent electric current from flowing to the channel region 31 of gate terminal 14 and TFT 10 or preventing electric current from flowing from the channel region 31 of gate terminal 14 and TFT10.Dielectric layer 16 can be generated by deposition process.Then the layer (that is, nanoconductor layer 20) of nanometer conductor is placed (" location ") on dielectric layer 16.Nanoconductor layer 20 generally includes multiple nanometer conductor and can comprise the nanotube of nano wire, nanofiber and/or such as single-walled nanotube (" SWNT "), double-walled nanotubes (" DWNT ") and/or many walls nanotube (" MWNT ").Nanometer conductor can be formed by carbon and/or silicon, and optionally can be incorporated to dopant material to change the electric conductivity of nanometer conductor.Nanoconductor layer 20 can be the simple layer (that is, individual layer) of nanometer conductor.
Semiconductor layer 30 is generated above nanoconductor layer 20.Semiconductor layer 30 forms the double-deck channel region 31 of TFT 10 together with nanoconductor layer 20.Such as, semiconductor layer 30 can be made up of organic semiconducting materials or inorganic semiconductor material.Such as, semiconductor layer 30 can be formed by amorphous silicon or polysilicon.Semiconductor layer 30 also can be incorporated to alloy to change the mobility characteristics of TFT 10.
Then the drain terminal 32 of TFT and source terminal 34 are formed on the semiconductor layer.Drain terminal 32 and each electric conducting material being freely suitable for transmission of electric energy of source terminal 34 are formed.Such as, terminal 32,34 can be metallic.Distance bound between drain terminal 32 and source terminal 34 makes raceway groove spacing distance.This raceway groove spacing distance is a parameter of the operating characteristics affecting TFT 10.
Because grid 14 is formed directly on substrate 12, so TFT 10 is called bottom-gate TFT, thus the side with the TFT 10 of grid 14 is called the bottom side of TFT 10, and the side with the TFT 10 of drain terminal 32 and source terminal 34 is called the top side of TFT 10.
Fig. 2 illustrates the block diagram of the top grid thin-film transistor 40 with the channel region 31 comprising nanoconductor layer 20.Top grid TFT 40 is that the layered component by applying in reverse order to discuss relatively with the bottom-gate TFT 10 shown in Fig. 1 manufactures.Drain terminal 32 and source terminal 34 are formed on the substrate 12 separately.Then semiconductor layer 30 is deposited on drain terminal 32 and source terminal 34.Then nanoconductor layer 20 is applied to semiconductor layer 30 to form double-deck channel region 31.By nanoconductor layer 20 being applied to the surface of the semiconductor layer 30 contrary with source terminal 34 with drain terminal 32, nanoconductor layer 20 is oriented to not exist with drain terminal 32 and source terminal 34 and anyly directly contacts.Therefore, in low field effect operation (such as, low grid-source voltage) period, the performance of TFT is arranged by semiconductor layer, this is because nanometer conductor does not exist with the source terminal of TFT or drain terminal and anyly directly to contact.Thus TFT provides the good leakage current performance similar with the performance of semiconductor layer 30.Then generate dielectric layer 16 in the nanometer conductor side of channel region 31, and gate terminal 14 is formed on dielectric layer 16.
In addition, nanometer conductor nanoconductor layer can change the polarity of TFT device.Such as, carbon nano-tube has p-type characteristic.Therefore, amorphous silicon (a-Si) TFT being formed with the channel region comprising carbon nano-tube can have p-type characteristic.The p-type a-Si TFT of formation like this because of the mobility of the enhancing of this p-type transistor under compared with conventional p-type TFT, and can be of value to a-Si TFT widely and applies.The mobility of the enhancing of this p-type transistor under compared with conventional p-type TFT can advantageously make this p-type a-Si TFT be used in the previous displayer application arranged by N-shaped TFT, thus allows p-type image element circuit structure.
Fig. 3 A is the cross sectional representation of the thin-film transistor 110 (" TFT ") with the channel region 131 comprising nanoconductor layer 120.In schematic diagram in figure 3 a, the assembly of TFT 110 is by the reference number of the reference number large 100 of the corresponding assembly of TFT 10 in the block diagram that is composed of than Fig. 1.TFT 110 is formed on substrate 112, and described substrate 112 can be the substrate of the displays such as such as backplane substrate, transparent planar substrate or packaged glass substrate.Gate terminal 114 is formed on substrate 112.Gate terminal 114 can be there is the gate terminal 14 described relatively with Fig. 1 property class like the conducting terminal of characteristic.Gate terminal 114 generates dielectric layer 116 insulate with the channel region 131 of TFT 110 to make gate terminal 114.Dielectric layer 116 can be electrical insulator.
The channel region 131 of TFT has two layers: nanoconductor layer 120 and semiconductor layer 130.Semiconductor layer 130 makes nanoconductor layer 120 avoid contacting with drain terminal 132 or the direct of source terminal 134.Nanoconductor layer 120 generally includes many nano wires, many nanofibers and/or many nanotubes.Single nanometer conductor (" nano particle ") in nanoconductor layer 120 is placed in the film on dielectric layer 116.Single nanometer conductor separately desirably along from drain terminal 132 to the direction general alignment of source terminal 134, to increase the effect of the Charger transfer between drain terminal 132 and source terminal 134.
Fig. 3 B is similar with illustrated thin-film transistor in Fig. 3 A but has the schematic diagram of the thin-film transistor 111 of shorter nanoconductor layer 121.Schematic diagram in Fig. 3 B shows drain terminal 132 and source terminal 134 can be overlapping with nanoconductor layer 121 with different quantity.By along the size degree regulating nanoconductor layer 121 from drain terminal 132 to the direction of source terminal 134, the charge transfer characteristic of double-deck channel region 131 can be changed.Such as, double-deck channel region 131 can by increasing the size degree of nanoconductor layer 121 (such as, length), by increase the nanometer conductor in nanoconductor layer 121 density and/or by increasing the Charger transfer (such as, the mobility of increase) more than providing relatively with the overlapping quantity of drain terminal 132 and/or source terminal 134.As described herein, nanoconductor layer 121 and the overlapping quantity between drain terminal 132 and source terminal 134 refer to the surface area quantity of drain terminal 132/ source terminal 134 be separated with nanoconductor layer 121 by means of only the vertical-path through semiconductor layer 130.In Fig. 3 A and Fig. 3 B, the vertical direction through semiconductor layer 130 is outwards perpendicular to the direction of substrate 112.
Many aspects of the present invention provide further, nanoconductor layer 121 can along be configured with from drain terminal 132 to the direction of source terminal 134 not with any one the overlapping size degree in drain terminal 132 or source terminal 134.Such as, the length of nanoconductor layer 121 can be less than the spacing distance between drain terminal 132 and source terminal 134.The additional configuration of nanoconductor layer 121 by the schematic top plan view general illustration in Fig. 4 A to Fig. 4 C.
Fig. 4 A is the schematic top plan view of the nanoconductor layer of the characteristic length with the interval be greater than between the drain terminal of TFT and source terminal.Although for illustrative purposes, to have homogeneous length and each comfortable drain terminal 32 shows nanoconductor layer 20 with the single nanometer conductor alignd between source terminal 34 (such as, nanometer conductor 21,22), the present invention is not limited to this.Many aspects of the present invention are applicable to the configuration that nanoconductor layer 20 has length and the inhomogenous single nanometer conductor of orientation.The schematic diagram of the nanoconductor layer 20 in Fig. 4 A also illustrates single nanometer conductor (such as, nanometer conductor 21,22) and arranges with individual layer.Nanoconductor layer 20 can be the dispersion individual layer of the nanometer conductor that the complete cross section not covering double-deck channel region is completely amassed.Such as, single nanometer conductor (such as, nanometer conductor 21,22) between gap can be roughly the size identical with nanometer conductor local width, to make single nanometer conductor in nanoconductor layer 20 (such as, nanometer conductor 21,22) accumulate the double-deck channel region covering approximate half (such as, 50%).In one example, any gap between single nanometer conductor (such as, nanometer conductor 21,22) is all filled by the semiconductor layer be deposited on above nanoconductor layer 20.Nanoconductor layer 20 can be performed when coverage is greater than or less than coverage (such as, 30% coverage or 70% coverage) of 50%.As a rule, the density (that is, coverage rate) increasing nanometer conductor individual layer can strengthen the charge transfer characteristic of double-deck channel region.
In Fig. 4 A to Fig. 4 C, the Hash block being denoted as " D " and " S " represents the position of drain terminal 32 and source terminal 34 respectively.Drain terminal 32 has raceway groove side 33, and source terminal 34 has raceway groove side 35.Consider for convenience, the distance between the raceway groove side 33 of drain terminal 32 and the raceway groove side 35 of source terminal 34 can be called raceway groove spacing distance.As shown in Figure 4 A, the length of nanoconductor layer 20 can be greater than the raceway groove spacing distance between drain terminal 32 and source terminal 34, to make overlapping at least partially separately with nanoconductor layer 20 of drain terminal 32 and source terminal 34.By making the overlapping with drain terminal 32/ source terminal 34 at least partially of nanoconductor layer 20, nanoconductor layer 20 advantageously allows vertical connection paths through semiconductor layer to strengthen the charge transfer characteristic of double-deck channel region.
Fig. 4 B is the schematic top plan view with nanoconductor layer like Fig. 4 category-A, but wherein single nanometer conductor (such as, nanometer conductor 21,23) does not align along the direction being directed to source terminal 34 from drain terminal 32 completely.Be not directly connected to drain terminal 32/ source terminal 34 due to nanoconductor layer 20 any one (namely, nanoconductor layer 20 is connected to drain terminal/source terminal by means of only semiconductor layer), so the charge transfer characteristic of double-deck channel region requires relative insensitivity to the Accurate align of single nanometer conductor (such as, nanometer conductor 23).Therefore, nanometer conductor (such as, nanometer conductor 21,23) usually by passing the effective mobility that semiconductor layer strengthens double-deck channel region, with the mobility making the charge transfer characteristic of thin-film transistor not be limited to semiconductor layer through semiconductor layer delivered charge to drain terminal 32/ source terminal 34 or from drain terminal 32/ source terminal 34 delivered charge.
Fig. 4 C is the schematic top plan view with nanoconductor layer like Fig. 4 category-A, but wherein the characteristic length of nanoconductor layer is less than the interval between the drain terminal of TFT and source terminal.In schematic diagram in figure 4 c, single nanometer conductor (such as, nanometer conductor 24,25) is illustrated as the length having and be less than raceway groove spacing distance.In figure 4 c in illustrated configuration, nanoconductor layer 20 is not overlapping with any one of drain terminal 32 or source terminal 34.Therefore, there is not charge transfer path from drain terminal 32/ source terminal 34 to nanoconductor layer 20, described charge transfer path only includes the vertical electric charge transfer path through semiconductor layer.Such as, in the configuration illustrated in figure 4 c, the effective mobility of double-deck channel region may be subject to the restriction of the requirement that electric charge horizontal transfer is passed.
Fig. 5 be a diagram that flow process Figure 50 of the instantiation procedure for the manufacture of the thin-film transistor with the channel region comprising nanoconductor layer (" TFT ").In first step 51, the gate terminal of TFT is formed on substrate.Then, in step 52, on gate terminal 54, dielectric layer is generated.This dielectric layer clad lives the exposed surface of gate terminal, to prevent the double-deck channel region of next deposition from directly contacting gate terminal.In step 53, by the nanometer conductor dispersion layer of such as nanotube or nano wire location on the dielectric layer.As discussed relatively with Fig. 3 A to Fig. 3 B, nanometer conductor dispersion layer can be the individual layer of the whole exposed areas not covering channel region.In step 54, semiconductor layer is deposited on any exposed region of nanoconductor layer and dielectric layer.Semiconductor layer can comprise amorphous silicon.Therefore, semiconductor layer and nanoconductor layer form double-deck channel region jointly.Then in step 55, source terminal and drain terminal are formed on the semiconductor layer.Source terminal is so formed with drain terminal thus is not directly connected with nanometer conductor.
Flow process Figure 50 is the embodiment of the process for the manufacture of bottom-gate TFT (that is, being deposited on substrate by gate terminal).But can adopt similar process to manufacture top grid TFT, this top grid TFT has the double-deck channel region being incorporated to the nanometer conductor directly not contacting drain terminal or source terminal, all top grid TFT 40 as shown in Figure 2.Such as, drain terminal and source terminal can be formed on substrate.Semiconductor layer can be deposited on the top of drain terminal and source terminal, and nanoconductor layer can be placed on the top of semiconductor layer, thus form double-deck channel region.By dielectric layer deposition above double-deck channel region, and gate terminal can be formed on the dielectric layer.
Fig. 6 illustrates the structure of change, and wherein source metal and drain terminal 61 and 62 (such as, thickness is the aluminium of about 100 nanometers) are formed on the respective layer 63 and 64 of p+ silicon (such as, thickness is about 35 nanometers).Immediately preceding below layer 63 and 64 be semi-conducting material (such as, gross thickness is the nanocrystal silicon replaced and the amorphous silicon of about 30 nanometers) layer 65, described semiconductor material layer 65 is deposited on the nanoconductor layer 66 of such as carbon nano-tube (such as, thickness is about 1 to 2 nanometer).Nanometer conductor is deposited on dielectric layer 67 (such as, thickness is the thermal silicon dioxide of about 100 nanometers), again by described dielectric layer deposition on substrate 68 (such as, p+ silicon).The bottom surface of substrate 67 is coated with conducting back contact 69 (such as, thickness is the aluminium of about 100 nanometers).
Example process for the formation of the structure shown in Fig. 6 is as follows:
1. hot P +silicon substrate cleans
A Ultrasonic Cleaning that () makes substrate carry out in acetone 10 minutes, then carries out the Ultrasonic Cleaning of other 10 minutes in isopropyl alcohol (IPA).This process is repeated twice.
B () is carried out rinsing with deionized water to substrate and is carried out drying with nitrogen.
Attention: substrate is placed on electric furnace (~ 90 DEG C) before next step upper lasting 10 minutes.
2. carbon nano-tube coating
A () uses aminopropyl triethoxysilane (APTES) to process substrate.
Before the coating, substrate to be immersed in APTES solution (the IPA solution of 1%v/v) 20 minutes, then with IPA rinsing carried out to described substrate and carry out drying with nitrogen.
(b) by carbon nano-tube dip-coating on the substrate through APTES process.
Substrate to be immersed in carbon nano-tube solution 15 minutes.Then with sufficient deionized water rinsing carried out to substrate and carry out drying with nitrogen.
The described substrate being coated with carbon nano-tube is toasted 20 minutes on 180 DEG C of electric furnaces, afterwards it is loaded in plasma reinforced chemical vapour deposition (PECVD) system.
3. use PECVD depositing nano crystal silicon (nc-Si) and amorphous silicon SiN x.
(a)nc-Si(～30nm.)
Gas: SiH 4/ H 2=40/200sccm; Pr=900mtorr; R f=2W; T=210C (setting); Speed=4.07nm/min.
(b)SiN x(150nm)
Gas: SiH 4/ NH 3/ N 2=5/100/50sccm; Pr=1000mtorr; R f=15W; T=250C (setting); Speed=15nm/min.
4. via the SiN of (mask #1) x
(a) photoetching process
Photoresist: NLOF 2035
Rotate: 10 seconds 500rpm, then 90 seconds 4000rmp.
Soft baking: continue 1 minute at 110 DEG C.
Contact: low vacuum.
Exposure: 5.4 seconds.
Postexposure bake: 110 DEG C.
Development: the AZ300MIF of ~ 30 seconds.
B () uses buffered hydrofluoric acid (BHF) wet etching SiN x.
Substrate to be immersed in BHF solution (10%v/v) 27 seconds.
The stripping of (c) photoresist
Substrate to be immersed in AZ KWIT remover 10 minutes, then by deionized water, acetone and IPA, rinsing is carried out to described substrate.
5.P +deposition (~ 35nm is thick)
Gas: SiH 4/ B 2h 6/ H 2=1.8/1.8/200sccm; Pr=1500mtorr; R f=65W; T=250C, (setting); Speed=7.7nm/min.
6.S/D metal deposition (aluminium, ~ 100nm is thick)
7.S/D patterning (mask #1 ')
Photoresist: AZ 3312
Rotate: 10 seconds 700rpm, then 60 seconds 4000rmp.
Soft baking: continue 1 minute at 90 DEG C.
Contact: low vacuum.
Exposure: 4 seconds.
Postexposure bake: continue 1 minute at 120 DEG C.
Development: the AZ300MIF of ~ 15 seconds.
Etching: at room temperature in PAN etchant ~ 3 minutes.
Peel off: rinsing 4 minutes in AZ KWIT remover, then with deionized water, acetone and IPA, rinsing is carried out to described substrate.
8. S/D metal is used as hardmask and is separated P +.
RIE dry etching P+ silicon:
RF=50W; Pr=20mtorr; CF4/H2=20/3sccm; Speed=~ 0.43nm/s
9. device is separated and isolation (mask #2)
(a) photoetching process
Photoresist: AZ 3312
Rotate: 10 seconds 700rpm, then 60 seconds 4000rmp.
Soft baking: continue 1 minute at 90 DEG C.
Contact: low vacuum.
Exposure: 4 seconds.
Postexposure bake: continue 1 minute at 120 DEG C.
Development: the AZ300MIF of ~ 15 seconds.
(b) dry etching SiN x/ Si/ carbon nano-tube.
R f=125W; Pr=150mtorr; CF 4/ O 2=43/5sccm; Speed=~ 4nm/s.
10. backside contacts metal deposition (aluminium, ~ 100nm is thick)
(a) removing back thermal oxide.
Described wafer front side is protected by PR AZ3312, afterwards its to be immersed in BHF (10%v/v) 4 minutes.
B () metal is deposited on the rear side of wafer.
By BHF by the thermal oxide of wafer backside remove after, wafer is loaded into immediately in vacuum chamber to carry out metal deposition.
Fig. 7 ~ 10 illustrate film capacitor, and this film capacitor comprises: semiconductor layer, and it has controllable resistor; First dielectric layer and the second dielectric layer, the two is arranged in the opposition side of described semiconductor layer; The first metal layer, it forms the first terminal in the side contrary with described semiconductor layer of described first dielectric layer; Second metal level, it forms the second terminal and the 3rd terminal in the side contrary with described semiconductor layer of described second dielectric layer, described 3rd terminal extends through described second dielectric layer and contacts with described semiconductor layer, and described second terminal does not contact with described semiconductor layer; And voltage source, the one in itself and described second terminal and the 3rd terminal couples the resistance reducing described semiconductor layer, and another one in described second terminal and the 3rd terminal and described semiconductor layer form capacitor.Described second terminal and the 3rd terminal can be source terminal and drain terminal, and described the first terminal can be gate terminal.Described second metal level can be divided into described second terminal of formation and the 3rd terminal, and described the first terminal can share with the one in described second terminal and the 3rd terminal.Described second terminal and the 3rd terminal can connect into and form capacitor at described semiconductor layer and between described second terminal and the 3rd terminal.The power supply of switched voltage can be connected to the terminal of film capacitor.
In the figure 7, capacitor is formed between at least one in semiconductor layer and two metal levels in the opposition side of this semiconductor layer.Each metal level is separated by dielectric layer and semiconductor layer.Main challenge is that semiconductor is very ohmic, and therefore, and postpone will be higher with the RC that is associated of charging to capacitor, and this causes lower frame per second or delayed.
In order to avoid high RC postpones, as shown in FIG. 8 and 9, employ three termination capacitor.The first metal layer being positioned at semiconductor layer side is separated by the first dielectric layer and semiconductor layer and forms the first terminal A of the resistivity for controlling semiconductor layer.The second metal level being positioned at semiconductor layer opposite side is separated by the second dielectric layer and semiconductor layer.This second metal level is divided into formation second terminal B and the 3rd terminal C, thus forms capacitor between terminal B and terminal C.Terminal C extends through the second dielectric layer to contact with semiconductor layer.
In one example, terminal A is connected with the low or high voltage transmission line in panel, and this depends on the type (such as, low high for N-shaped for p-type) of semiconductor.In the case, semiconductor layer resistance is significantly reduced by charge accumulation (or consumption).In another example, terminal A and another terminal (B or C) share.In the case, one of these terminals have the voltage of the resistance reducing semi-conducting material, and this depends on the type of semiconductor.
In figs. 8 and 9, there are between terminal C and semiconductor layer two contact sites, but a contact site or two or more contact site are also fine (this depends on usable area).
The order of layer can change, and Fig. 8 and 9 shows an example of 3 termination capacitor.
Voltage on the control terminal of capacitor can be fixed voltage or switched voltage.When switched voltage, the RC that can control to carry out capacitor charge or discharge postpones.Such as, carrying out capacitor between charge period, using the voltage reducing RC and postpone, and then making the voltage for hold period that electric capacity becomes more stable.In the case, the characteristic of electric capacity does not have, because of high voltage difference bias stress, marked change occurs.
Figure 10 shows another structure providing high capacity when not increasing extra treatment step to manufacture process.Because the second dielectric 2 is thicker than semiconductor layer usually, so the conventional method with stacking dielectric causes less capacitor than using stacking semiconductor and dielectric.Here, the second dielectric is etched, during this period patterning is carried out to this dielectric layer, and then, the metal for electrode B is deposited as and contacts with semiconductor layer through the opening in pattern.In order to have consistent electric capacity, can connecting electrode B and electrode A as follows: the voltage at two electrode A and B two ends is always higher or lower than the threshold voltage of established metal-insulator semiconductor capacitor.Therefore, semiconductor layer always will be used as insulator or conductor layer.
Although illustrate and described specific embodiments of the invention and application, but be to be understood that, the present invention is not limited to precise arrangements disclosed herein and composition, and when not departing from the spirit and scope limited in following claims of the present invention, various change, change and change can become apparent according to describing above.

Claims (6)

1. a film capacitor, it comprises:
Semiconductor layer, it has controllable resistor;
First dielectric layer and the second dielectric layer, the two is arranged in the opposition side of described semiconductor layer;
The first metal layer, it forms the first terminal in the side contrary with described semiconductor layer of described first dielectric layer;
Second metal level, it forms the second terminal and the 3rd terminal in the side contrary with described semiconductor layer of described second dielectric layer, described 3rd terminal extends through described second dielectric layer and contacts with described semiconductor layer, and described second terminal does not contact with described semiconductor layer; And
Voltage source, the one in itself and described second terminal and described 3rd terminal couples, and to reduce the resistance of described semiconductor layer, and another one in described second terminal and described 3rd terminal and described semiconductor layer form capacitor.
2. film capacitor as claimed in claim 1, wherein, described second terminal and described 3rd terminal are source terminal and drain terminal, and described the first terminal is gate terminal.
3. film capacitor as claimed in claim 1, wherein, described second metal level is divided into described second terminal of formation and described 3rd terminal.
4. film capacitor as claimed in claim 1, wherein, described the first terminal is shared with the one in described second terminal and described 3rd terminal.
5. film capacitor as claimed in claim 1, wherein, described second terminal is connected with described 3rd terminal, and forms capacitor at described semiconductor layer and between described second terminal and described 3rd terminal.
6. film capacitor as claimed in claim 1, wherein, the power supply of switched voltage is connected with the terminal of described film capacitor.
CN201410844332.8A 2013-12-30 2014-12-30 Thin film capacitor Active CN104752056B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1041061A (en) * 1988-09-07 1990-04-04 李钊华 Piezocapacitor
CN1871675A (en) * 2003-08-20 2006-11-29 波尔伊克两合公司 Organic capacitor having a voltage-controlled capacitance
CN101032027A (en) * 2004-09-02 2007-09-05 卡西欧计算机株式会社 Thin film transistor and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1041061A (en) * 1988-09-07 1990-04-04 李钊华 Piezocapacitor
CN1871675A (en) * 2003-08-20 2006-11-29 波尔伊克两合公司 Organic capacitor having a voltage-controlled capacitance
CN101032027A (en) * 2004-09-02 2007-09-05 卡西欧计算机株式会社 Thin film transistor and its manufacturing method

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