CN104751886B - A kind of power-off protection method and device of nonvolatile memory - Google Patents
A kind of power-off protection method and device of nonvolatile memory Download PDFInfo
- Publication number
- CN104751886B CN104751886B CN201310741882.2A CN201310741882A CN104751886B CN 104751886 B CN104751886 B CN 104751886B CN 201310741882 A CN201310741882 A CN 201310741882A CN 104751886 B CN104751886 B CN 104751886B
- Authority
- CN
- China
- Prior art keywords
- erasing
- power down
- recorded
- bit line
- erasure information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention provides a kind of power-off protection method and device of nonvolatile memory, when solving to be abnormal power down during executing erasing operation, leads to the problem of the data inaccuracy read to storage unit due to crossing erasing phenomenon after re-powering.Wherein, method includes：In power down, erasure information is recorded；When re-powering after a power failure, judge whether to be abnormal power down during executing erasing operation according to the erasure information；If being abnormal power down, erasing verification was executed according to the erasure information.Present invention can ensure that nonvolatile memory is abnormal power down during executing erasing operation, the reliability for the data that storage unit is read after re-powering.
Description
Technical field
The present invention relates to semiconductor memory technologies fields, more particularly to a kind of power down protection of nonvolatile memory
Method and apparatus.
Background technology
Nonvolatile memory refers to remaining to keep data after powering off, that is, what the data stored after powering off will not lose
A kind of memory.Flash memory（Flash Memory）And EEPROM（Electrically Erasable Programmable
Read-Only Memory, Electrically Erasable Programmable Read-Only Memory）Belong to nonvolatile memory.
As shown in Figure 1, being a kind of structural schematic diagram of nonvolatile memory.The nonvolatile memory includes physics
Block（Physics BLOCK）, a physical block includes multiple storage units（cell）, multiple bit lines（Bit line, BL）And it is a plurality of
Wordline（Word line, WL）, MN1, MN2, MN3, MN4...... are storage unit in Fig. 1, BL1, BL2, BL3,
BL4...... it is bit line, WL1, WL2, WL3, WL4...... are wordline.Can it connect in every bit line and every wordline
Connect multiple storage units.The erasing of nonvolatile memory（erase）Operation is carried out by block, i.e., every time in an erasing region
Each storage unit carry out erasing operation.
Usually after executing erasing operation, the threshold voltage of region memory storage unit is wiped into normal distribution, Fig. 2 is to execute
The schematic diagram that the threshold voltage of region memory storage unit is wiped after erasing operation, in Fig. 2, Vt is the threshold voltage of storage unit,
EV is erasing target voltage.As can be drawn from Figure 2, the threshold voltage of erasing rear portion storage unit can be less than or equal to 0, this
It was exactly erasing（Over erase）Phenomenon.Since multiple storages can be connected on same bit line in the nonvolatile memory
Unit, so storage unit of these threshold voltages less than or equal to 0 can make there is larger leakage current on the bit line where it,
To influence the reading result of other storage units on the bit line.
To solve the above-mentioned problems, increased erasing checking procedure usually after erasing operation executes completion at present, led to
The threshold voltage for crossing storage unit of the erasing verification by these threshold voltages less than or equal to 0 is reprogrammed to more than 0, to
The leakage current for having larger on bit line is avoided, as shown in figure 3, to execute the threshold value for wiping region memory storage unit after erasing verifies
The schematic diagram of voltage, in Fig. 3, Vt is the threshold voltage of storage unit, and EV is erasing target voltage, is executed as can be drawn from Figure 3
After crossing erasing verification, the threshold voltage of each storage unit is all higher than 0.
But if nonvolatile memory is abnormal power down during executing erasing operation, at this time due to wiping
Division operation does not complete also, therefore executes erasing verification not yet.Therefore, after re-powering, still there can be threshold voltage
Storage unit less than or equal to 0 is in when reading the storage unit in non-erasing region with the threshold voltage less than or equal to 0
When data in the storage unit on same bit line, the data read may be caused due to the leakage current on the bit line not
Accurately.
Invention content
The present invention provides a kind of power-off protection method and device of nonvolatile memory, to solve executing erasing operation
During when being abnormal power down, lead to the data inaccuracy read to storage unit due to crossing erasing phenomenon after re-powering
The problem of.
To solve the above-mentioned problems, the invention discloses a kind of power-off protection method of nonvolatile memory, features
It is, including：
In power down, erasure information is recorded；
When re-powering after a power failure, judge whether to occur during executing erasing operation according to the erasure information
Powered-off fault；
If being abnormal power down, erasing verification was executed according to the erasure information.
Preferably, the erasure information is recorded in pre-set power down protection region, and the erasure information includes falling
Electrosemaphore and erasing regional address.
Preferably, the step of record erasure information includes：
It detects whether to execute erasing operation according to erasing instruction, the erasing instruction includes erasing regional address；
If executing erasing operation according to erasing instruction, the power loss indicator is recorded as to be abnormal power down, it will
The erasing regional address is recorded as the erasing regional address in the erasing instruction；
If not executing erasing operation according to erasing instruction, the power loss indicator is recorded as no exceptions and is fallen
The erasing regional address is recorded as sky by electricity.
Preferably, described to judge whether to be abnormal power down during executing erasing operation according to the erasure information
The step of include：
Judge whether the power loss indicator is to be abnormal power down；
If being abnormal power down, it is determined that be abnormal power down during executing erasing operation.
Preferably, the nonvolatile memory includes physical block, and the physical block includes at least one storage unit, extremely
A few bit line and at least one wordline, the bit line are connect with the drain electrode of at least one storage unit, the wordline and extremely
The grid connection of a few storage unit, an erasing region includes at least one storage unit,
It is described according to the erasure information executed erasing verification the step of include：
Search the corresponding erasing region of the erasing regional address；
Applying the voltage equal to 0 where the erasing region in each wordline of physical block；
Detect the bit line for being more than preset leakage current threshold in each bit line in the erasing region with the presence or absence of electric current；
If in the presence of programming drain voltage is applied on the bit line, and return to each of the detection erasing region
The step of being more than the bit line of preset leakage current threshold with the presence or absence of electric current in bit line；
If being not present, it is determined that the verification of erasing excessively executes completion.
Preferably, the method further includes：
It is described cross erasing verification and execute after the completion of, the power loss indicator is recorded as no exceptions power down, will be described
Erasing regional address is recorded as sky.
According to another aspect of the present invention, a kind of power-down protection apparatus of nonvolatile memory, feature are also disclosed
It is, including：
First logging modle, in power down, recording erasure information；
Judgment module when for re-powering after a power failure, judges whether executing erasing behaviour according to the erasure information
Power down is abnormal during work；
Correction verification module is when being abnormal power down, to believe according to the erasing for the judging result in the judgment module
Breath executed erasing verification.
Preferably, the erasure information is recorded in pre-set power down protection region, and the erasure information includes falling
Electrosemaphore and erasing regional address.
Preferably, first logging modle includes：
Erasure detection submodule, for detecting whether executing erasing operation, the erasing instruction according to erasing instruction
Including wiping regional address；
First record sub module is when being, by the power down mark for the testing result in the erasure detection submodule
Will is recorded as being abnormal power down, and the erasing regional address is recorded as the erasing regional address in the erasing instruction；
Second record sub module is used for when the testing result of the erasure detection submodule is no, by the power down mark
Will is recorded as no exceptions power down, and the erasing regional address is recorded as sky.
Preferably, the judgment module includes：
Indicate judging submodule, for judging whether the power loss indicator is to be abnormal power down；
Power down determination sub-module, for it is described mark judging submodule judging result be abnormal power down when, really
It is scheduled on during executing erasing operation and is abnormal power down.
Preferably, the nonvolatile memory includes physical block, and the physical block includes at least one storage unit, extremely
A few bit line and at least one wordline, the bit line are connect with the drain electrode of at least one storage unit, the wordline and extremely
The grid connection of a few storage unit, an erasing region includes at least one storage unit,
The correction verification module includes：
Address search submodule, for searching the corresponding erasing region of the erasing regional address；
First applies submodule, for applying the electricity equal to 0 where the erasing region in each wordline of physical block
Pressure；
Current detecting submodule, for detecting in each bit line for wiping region with the presence or absence of electric current more than preset
The bit line of leakage current threshold；
Second applies submodule, in the presence of the testing result of the current detecting submodule is, in the bit line
Upper application programs drain voltage, and calls the current detecting submodule；
Determination sub-module is verified, described in the absence of the testing result of the current detecting submodule is, determining
It crosses erasing verification and executes completion.
Preferably, described device further includes：
Second logging modle, for it is described cross erasing verification execute after the completion of, the power loss indicator is recorded as not sending out
Raw powered-off fault, sky is recorded as by the erasing regional address.
Compared with prior art, the present invention includes following advantages：
Nonvolatile memory will record erasure information in power down in the present invention；When re-powering after a power failure, foundation
The erasure information judges whether to be abnormal power down during executing erasing operation；If being abnormal power down, foundation
The erasure information executed erasing verification.The present invention can be with needle during being re-powered after nonvolatile memory power down
The phenomenon that being abnormal power down during executing erasing operation, executed erasing verification, thereby may be ensured that non-volatile
Property memory power down is abnormal during executing erasing operation, after re-powering to storage unit read data can
By property.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of nonvolatile memory in the prior art；
Fig. 2 is the schematic diagram of the threshold voltage of erasing region memory storage unit after executing erasing operation in the prior art；
Fig. 3 is the schematic diagram of the threshold voltage of erasing region memory storage unit after executing erasing verification in the prior art；
Fig. 4 is a kind of flow chart of the power-off protection method of nonvolatile memory of the embodiment of the present invention one；
Fig. 5 is a kind of flow chart of the power-off protection method of nonvolatile memory of the embodiment of the present invention two；
Fig. 6 is a kind of structural schematic diagram of nonvolatile memory of the embodiment of the present invention two；
Fig. 7 is a kind of structural schematic diagram of storage unit of the embodiment of the present invention two；
Fig. 8 is a kind of structure diagram of the power-down protection apparatus of nonvolatile memory of the embodiment of the present invention three.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
Embodiment one：
With reference to Fig. 4, a kind of flow of the power-off protection method of nonvolatile memory of the embodiment of the present invention one is shown
Figure, this method can specifically include following steps：
Step 401, in power down, erasure information is recorded.
It is described to refer to while power down in power down in the embodiment of the present invention（I.e. during power down）.If
Power down occurs for nonvolatile memory, then can record erasure information during power down.Wherein, the erasure information of record can
Using as the foundation for subsequently judging whether to be abnormal power down during executing erasing operation.It is non-in the embodiment of the present invention
Volatile memory can be flash memory, EEPROM etc..
Step 402, when re-powering after a power failure, judge whether in the mistake for executing erasing operation according to the erasure information
Power down is abnormal in journey.
If power down occurs for nonvolatile memory, when re-powering after a power failure, you can to believe according to the erasing
Breath judges whether to be abnormal power down during executing erasing operation.Power down herein can be powered-off fault（Such as it is prominent
So cut-out power supply）, or normal powering down（Such as user actively closes power supply）, it is described after a power failure again on
When electric, it can refer to while powering on（During powering on）, can also refer to after powering on.
Step 403, if being abnormal power down, erasing verification was executed according to the erasure information.
If it is judged that being abnormal power down during executing erasing operation, then can be held according to the erasure information
Erasing of going verifies；If no exceptions power down during executing erasing operation, erasing verification can not be executed.
Nonvolatile memory will record erasure information in power down in the embodiment of the present invention；It re-powers after a power failure
When, judge whether to be abnormal power down during executing erasing operation according to the erasure information；If being abnormal power down,
Then erasing verification was executed according to the erasure information.During the present invention re-powers after nonvolatile memory power down
It can be directed to the phenomenon that being abnormal power down during executing erasing operation, erasing verification was executed, and thereby may be ensured that
Nonvolatile memory is abnormal power down during executing erasing operation, the number read to storage unit after re-powering
According to reliability.
Embodiment two：
With reference to Fig. 5, a kind of flow of the power-off protection method of nonvolatile memory of the embodiment of the present invention two is shown
Figure, this method can specifically include following steps：
Step 501, in power down, erasure information is recorded.
The purpose of the embodiment of the present invention mainly nonvolatile memory after the power is turned on, according to record erasure information judge
Whether during executing erasing operation it is abnormal power down, in case of powered-off fault, is then held according to the erasure information
Erasing of going verifies.Therefore, nonvolatile memory can record erasure information, need in power down in the embodiment of the present invention
Illustrate, it can be while power down in the embodiment of the present invention（I.e. during power down）Record erasure information.
In one preferred embodiment of the invention, a power down protection can be separately provided in the nonvolatile memory
Region is for recording above-mentioned erasure information.
With reference to Fig. 6, a kind of structural schematic diagram of nonvolatile memory of inventive embodiments two is shown, this is non-volatile
Memory may include physical block and power down protection region, and the physical block includes multiple storage units（MN1,MN2,MN3,
MN4......）, multiple bit lines（BL1,BL2,BL3,BL4.....）And a plurality of wordline（WL1,WL2,WL3,
WL4......）.Multiple storage units, the bit line and storage unit can be connected on wherein every bit line and every wordline
Drain electrode connection, the grid of the wordline and storage unit connects, for example, physics shown in fig. 6 storage unit in the block according to
Array format is arranged, and the grid of each line storage unit is connected in same wordline, the drain electrode connection of each array storage unit
On same bit line.The erasing operation of nonvolatile memory is carried out by block, i.e., every time to each in an erasing region
Storage unit carries out erasing operation.Certainly, nonvolatile memory shown in fig. 6 is used merely as example, the present invention is implemented
Example in, the nonvolatile memory includes physical block, the physical block include at least one storage unit, at least one
Line and at least one wordline, the bit line are connect with the drain electrode of at least one storage unit, and the wordline is deposited at least one
The grid of storage unit connects, and an erasing region includes at least one storage unit.
The erasure information may include power loss indicator and erasing regional address, and therefore, the power down protection region can be with
As follows：
| EN | ADDRESS |
Wherein, EN is power loss indicator, which may include two values：It is abnormal power down and no exceptions
Power down indicates to be abnormal power down when EN is 1, indicates not occur when EN is 0 for example, the value of the EN can be 0 or 1
Powered-off fault.Certainly, the EN can also be other values or be other representations, as long as can be according to the value of EN
Or representation determines whether to be abnormal power down, the embodiment of the present invention does not limit this.ADDRESS is
Regional address is wiped, the embodiment of the present invention may include erasing regional address, therefore nonvolatile memory in erasing instruction
Corresponding erasing region can be searched according to the erasing regional address in erasing instruction, and the storage unit in the region is held
Row erasing operation.
In the embodiment of the present invention, the process that erasure information is recorded in the step 501 may include following sub-step：
Sub-step a1 detects whether that the erasing instruction includes scratching area according to erasing instruction execution erasing operation
Domain addresses；
If executing erasing operation according to erasing instruction, sub-step a2 is executed；If not according to erasing instruction
Erasing operation is executed, then executes sub-step a3.
Sub-step a2 is recorded as the power loss indicator to be abnormal power down, and the erasing regional address is recorded as institute
State the erasing regional address in erasing instruction；
The power loss indicator is recorded as no exceptions power down by sub-step a3, and the erasing regional address is recorded as
It is empty.
In the embodiment of the present invention, if power down occurs for nonvolatile memory, it can detect and work as during power down
It is preceding whether to execute erasing operation according to erasing instruction, then above-mentioned sub-step a2 or sub-step are executed according to testing result
A3 records corresponding erasure information.Therefore when re-powering after a power failure, you can the erasure information judgement according to above-mentioned record is
It is no to be abnormal power down during executing erasing operation, and when judging to be abnormal power down, believe according to the erasing
Breath executed erasing verification.
The process of erasing operation is wiped respectively each storage unit in this erasing region.With reference to figure
7, show that a kind of structural schematic diagram of storage unit of the embodiment of the present invention two, the storage unit include control gate 71, blocking
Layer 72, floating boom 73, oxide layer 74 and substrate 75, wherein substrate 75 include drain electrode and source electrode（Two " N of both sides in substrate 75
+ " drain electrode and source electrode are indicated respectively, when " N+ " in left side is drain electrode, " N+ " on right side is source electrode；When " N+ " in left side is source electrode
When, " N+ " on right side is drain electrode）, control gate 71, barrier layer 72, floating boom 73 and oxide layer 74 are combined into grid.
Nonvolatile memory stores information by changing the quantity of electronics in floating boom.Inject electrons into storage unit
Floating boom when, the threshold voltage of storage unit increases, and at this moment storage unit is in programming state；The electronics that will be captured in floating boom
After removal, the threshold voltage of storage unit reduces, and at this moment storage unit is in erased state.The erasing of nonvolatile memory
The tunneling effect based on electronics is operated, by grid（Control gate）Add negative voltage（VG）, while adding positive voltage in substrate
（VB）, at this time the electronics on floating boom substrate is entered by tunneling effect under the action of electric field, floating boom after losing electronics, storage
The threshold voltage of unit reduces, as erase process.
Step 502, when re-powering after a power failure, judge whether in the mistake for executing erasing operation according to the erasure information
Power down is abnormal in journey.
If it is judged that being abnormal power down during executing erasing operation, 503 are thened follow the steps；If it is judged that
It is not abnormal power down during executing erasing operation, then can not execute step 503, and bristle with anger under waiting system
It enables, executes corresponding operating according to described instruction, and in power down, return and execute above-mentioned steps 501.
In the embodiment of the present invention, the power down can be powered-off fault（Such as sudden shut off power supply）, or
Normal powering down（Such as user actively closes power supply）, the powered-off fault may be to be sent out during executing erasing operation
Raw powered-off fault, it is also possible to be abnormal power down, etc. during executing reading, write operation.I.e. the present invention is implemented
In example, when nonvolatile memory powers on（While powering on or after powering on）, i.e., to execute the step 502.
According to the description of above-mentioned steps 501 it is known that if detecting to execute according to erasing instruction in power down
Erasing operation, it can be said that bright be abnormal power down during executing erasing operation, therefore the power loss indicator recorded is hair
Raw powered-off fault；If detecting do not executing erasing operation according to erasing instruction in power down, it can be said that bright holding
No exceptions power down during row erasing operation, therefore the power loss indicator recorded is no exceptions power down.Therefore, this hair
It can judge whether to occur during executing erasing operation according to the power loss indicator in the erasure information in bright embodiment
Powered-off fault.
The process of the step 502 can be：Judge whether the power loss indicator is to be abnormal power down；If being abnormal
Power down, it is determined that be abnormal power down during executing erasing operation；If no exceptions power down, it is determined that executing
Power down is not abnormal during erasing operation.For example, if being indicated with " 0,1 " according to the description in above-mentioned steps 501
The value of EN, then when it is 1 to judge EN, you can power down is abnormal with determination, when it is 0 to judge EN, you can to determine not
It is abnormal power down.
Step 503, if being abnormal power down, erasing verification was executed according to the erasure information.
It, can be according to institute if judging to be abnormal power down during executing erasing operation in step 502
It states erasure information and executed erasing verification.
In one preferred embodiment of the invention, which may include following sub-step：
Sub-step b1 searches the corresponding erasing region of the erasing regional address；
It is possible, firstly, to find the corresponding of the erasing operation of execution according to the erasing regional address in the erasure information
Region is wiped, i.e., is abnormal power down when carrying out erasing operation to the storage unit in the erasing region, it is therefore desirable to this
Erasing region carried out erasing verification.
Sub-step b2 is applying the voltage equal to 0 in each wordline of physical block where the erasing region；
Sub-step b3 is detected in each bit line in the erasing region and is more than preset leakage current threshold with the presence or absence of electric current
Bit line；If in the presence of sub-step b4 is executed；If being not present, sub-step b5 is executed；
Apply the voltage equal to 0 in each wordline of physical block where the erasing region, if certain in certain wordline
The threshold voltage of a storage unit is less than or equal to 0, then will will produce on the bit line connected with the drain electrode of the storage unit larger
Leakage current so that electric current in the bit line is more than preset leakage current threshold, namely if electric current in certain bit line
More than preset leakage current threshold, it can be said that there are threshold voltages to be less than or equal in the bright storage unit being connect with the bit line
0 storage unit.
Sub-step b4 applies programming drain voltage on the bit line, and returns to sub-step b3；
If detected there are the bit line that electric current is more than preset leakage current threshold, can be more than in the electric current preset
Apply programming drain voltage on the bit line of leakage current threshold（Such as programming drain voltage is 4V）, apply the programming drain voltage
Afterwards, prodigious electric current will be will produce on this bit line so that wherein storage unit of the threshold voltage less than or equal to 0 is in programming
State injects electrons into the floating boom of the storage unit, so that the threshold voltage of the storage unit increases.In institute's rheme
Apply programming drain voltage on line so that after the threshold voltage increase of storage unit of the threshold voltage less than or equal to 0, you can return
Sub-step b3 is returned to be detected again.
Sub-step b5 determines that the verification of erasing excessively executes completion.
If detect that the electric current of all bit lines is respectively less than or is equal to preset leakage current threshold, you can determine scratching area
The threshold voltage of storage unit in domain has been more than 0, determines that erasing verification executed completion at this time.
For example, the erasing region found is to wipe region shown in Fig. 6, which includes that 8 storages are single
Member, including bit line be BL1, BL2, BL3 and BL4, the wordline that physical block where the erasing region includes be WL1, WL2,
WL3,WL4.......Apply on physics where the erasing region wordline WL1, WL2, WL3, WL4...... in the block and is equal to 0
Voltage, and detect erasing region each bit line BL1, BL2, BL3 and BL4 in the presence or absence of electric current be more than preset leakage current
The bit line of threshold value, such as detect that the electric current of bit line BL1 is more than preset leakage current threshold, it at this time can be on bit line BL1
Apply programming drain voltage, then detects in BL1, BL2, BL3 and BL4 again and be more than preset leakage current threshold with the presence or absence of electric current
The bit line of value, repeats the above process, until the electric current of BL1, BL2, BL3 and BL4 are respectively less than or are equal to preset leakage current
Until threshold value.
Step 504, after the completion of the verification of erasing excessively executes, the power loss indicator is recorded as no exceptions and is fallen
The erasing regional address is recorded as sky by electricity.
It is described cross erasing verification execute after the completion of, you can the power loss indicator is recorded as no exceptions power down, will
The erasing regional address is recorded as sky.Then can send instructions under waiting system, it, can be according to if receiving erasing instruction
Erasing operation is executed according to the erasing instruction, and in nonvolatile memory power down, execution above-mentioned steps can be returned
501。
In the embodiment of the present invention, in order to avoid powered-off fault made erasing phenomenon pair during executing erasing operation
The reliability for reading data has an impact, and nonvolatile memory will record erasure information in power down, and when re-powering
Corresponding erasing region executed erasing verification operation when to being abnormal power down during executing erasing operation, to protect
Demonstrate,prove the reliability that follow-up data is read.
For each method embodiment above-mentioned, for simple description, therefore it is all expressed as a series of combination of actions, but
Be those skilled in the art should understand that, the present invention is not limited by the described action sequence because according to the present invention, certain
A little steps can be performed in other orders or simultaneously.Secondly, it those skilled in the art should also know that, is retouched in specification
The embodiment stated belongs to preferred embodiment, and involved action and module are not necessarily essential to the invention.
Embodiment three：
With reference to Fig. 8, a kind of structure of the power-down protection apparatus of nonvolatile memory of the embodiment of the present invention three is shown
Block diagram, the device can specifically include with lower module：
First logging modle 801, in power down, recording erasure information；
Judgment module 802 when for re-powering after a power failure, judges whether executing erasing according to the erasure information
Power down is abnormal during operation；
Correction verification module 803 is when being abnormal power down, according to the erasing for the judging result in the judgment module
Information executed erasing verification.
In one preferred embodiment of the invention, the erasure information can be recorded in pre-set power down protection area
In domain, the erasure information may include power loss indicator and erasing regional address.The nonvolatile memory may include object
Block is managed, the physical block may include at least one storage unit, at least one bit line and at least one wordline, institute's rheme
Line is connect with the drain electrode of at least one storage unit, and the wordline is connect with the grid of at least one storage unit, an erasing
Region includes at least one storage unit.
First logging modle can specifically include following submodule：
Erasure detection submodule, for detecting whether executing erasing operation, the erasing instruction according to erasing instruction
Including wiping regional address；
First record sub module is when being, by the power down mark for the testing result in the erasure detection submodule
Will is recorded as being abnormal power down, and the erasing regional address is recorded as the erasing regional address in the erasing instruction；
Second record sub module is used for when the testing result of the erasure detection submodule is no, by the power down mark
Will is recorded as no exceptions power down, and the erasing regional address is recorded as sky.
The judgment module can specifically include following submodule：
Indicate judging submodule, for judging whether the power loss indicator is to be abnormal power down；
Power down determination sub-module, for it is described mark judging submodule judging result be abnormal power down when, really
It is scheduled on during executing erasing operation and is abnormal power down.
The correction verification module can specifically include following submodule：
Address search submodule, for searching the corresponding erasing region of the erasing regional address；
First applies submodule, for applying the electricity equal to 0 where the erasing region in each wordline of physical block
Pressure；
Current detecting submodule, for detecting in each bit line for wiping region with the presence or absence of electric current more than preset
The bit line of leakage current threshold；
Second applies submodule, in the presence of the testing result of the current detecting submodule is, in the bit line
Upper application programs drain voltage, and calls the current detecting submodule；
Determination sub-module is verified, described in the absence of the testing result of the current detecting submodule is, determining
It crosses erasing verification and executes completion.
In one preferred embodiment of the invention, described device can also comprise the following modules：
Second logging modle, for it is described cross erasing verification execute after the completion of, the power loss indicator is recorded as not sending out
Raw powered-off fault, sky is recorded as by the erasing regional address.
Nonvolatile memory will record erasure information in power down in the embodiment of the present invention；It re-powers after a power failure
When, judge whether to be abnormal power down during executing erasing operation according to the erasure information；If being abnormal power down,
Then erasing verification was executed according to the erasure information.What the embodiment of the present invention re-powered after nonvolatile memory power down
It can be directed to the phenomenon that being abnormal power down during executing erasing operation in the process, executed erasing verification, so as to
To ensure that nonvolatile memory is abnormal power down during executing erasing operation, storage unit is read after re-powering
The reliability of the data taken.
For device example, since it is basically similar to the method embodiment, so description is fairly simple, related place
Illustrate referring to the part of embodiment of the method.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiment, the same or similar parts between the embodiments can be referred to each other.
The present invention can describe in the general context of computer-executable instructions executed by a computer, such as program
Module.Usually, program module includes routines performing specific tasks or implementing specific abstract data types, program, object, group
Part, data structure etc..The present invention can also be put into practice in a distributed computing environment, in these distributed computing environments, by
Task is executed by the connected remote processing devices of communication network.In a distributed computing environment, program module can be with
In the local and remote computer storage media including storage device.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, commodity or equipment including a series of elements include not only that
A little elements, but also include other elements that are not explicitly listed, or further include for this process, method, commodity or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in process, method, commodity or the equipment including the element.
Above to a kind of power-off protection method and device of nonvolatile memory provided by the present invention, carry out in detail
It introduces, principle and implementation of the present invention are described for specific case used herein, the explanation of above example
It is merely used to help understand the method and its core concept of the present invention；Meanwhile for those of ordinary skill in the art, according to this
The thought of invention, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification is not answered
It is interpreted as limitation of the present invention.
Claims (10)
1. a kind of power-off protection method of nonvolatile memory, which is characterized in that including：
In power down, erasure information is recorded；
When re-powering after a power failure, judge whether to be abnormal during executing erasing operation according to the erasure information
Power down；
If being abnormal power down, erasing verification was executed according to the erasure information；
Wherein, the erasure information is recorded in pre-set power down protection region, and the erasure information includes power loss indicator
With erasing regional address.
2. according to the method described in claim 1, it is characterized in that, the step of record erasure information include：
It detects whether to execute erasing operation according to erasing instruction, the erasing instruction includes erasing regional address；
If executing erasing operation according to erasing instruction, the power loss indicator is recorded as to be abnormal power down, it will be described
Erasing regional address is recorded as the erasing regional address in the erasing instruction；
If not executing erasing operation according to erasing instruction, the power loss indicator is recorded as no exceptions power down,
The erasing regional address is recorded as sky.
3. according to the method described in claim 1, it is characterized in that, described judge whether executing wiping according to the erasure information
The step of power down is abnormal during division operation include：
Judge whether the power loss indicator is to be abnormal power down；
If being abnormal power down, it is determined that be abnormal power down during executing erasing operation.
4. according to the method described in claim 1, it is characterized in that, the nonvolatile memory includes physical block, the object
Reason block includes at least one storage unit, at least one bit line and at least one wordline, the bit line and at least one storage
The drain electrode of unit connects, and the wordline is connect with the grid of at least one storage unit, and an erasing region includes at least one
Storage unit,
It is described according to the erasure information executed erasing verification the step of include：
Search the corresponding erasing region of the erasing regional address；
Applying the voltage equal to 0 where the erasing region in each wordline of physical block；
Detect the bit line for being more than preset leakage current threshold in each bit line in the erasing region with the presence or absence of electric current；
If in the presence of programming drain voltage is applied on the bit line, and return to each item position in the detection erasing region
The step of being more than the bit line of preset leakage current threshold with the presence or absence of electric current in line；
If being not present, it is determined that the verification of erasing excessively executes completion.
5. method according to claim 1 or 4, which is characterized in that further include：
After the completion of the verification of erasing excessively executes, the power loss indicator is recorded as no exceptions power down, by the erasing
Regional address is recorded as sky.
6. a kind of power-down protection apparatus of nonvolatile memory, which is characterized in that including：
First logging modle, in power down, recording erasure information；
Judgment module when for re-powering after a power failure, judges whether executing erasing operation according to the erasure information
It is abnormal power down in the process；
Correction verification module is when being abnormal power down, to be held according to the erasure information for the judging result in the judgment module
Erasing of going verifies；
Wherein, the erasure information is recorded in pre-set power down protection region, and the erasure information includes power loss indicator
With erasing regional address.
7. device according to claim 6, which is characterized in that first logging modle includes：
Erasure detection submodule, for detecting whether executing erasing operation according to erasing instruction, the erasing instruction includes
Wipe regional address；
First record sub module is that when being, the power loss indicator is remembered for the testing result in the erasure detection submodule
The erasing regional address is recorded as the erasing regional address in the erasing instruction by record to be abnormal power down；
Second record sub module, for when the testing result of the erasure detection submodule is no, the power loss indicator to be remembered
Record is no exceptions power down, and the erasing regional address is recorded as sky.
8. device according to claim 6, which is characterized in that the judgment module includes：
Indicate judging submodule, for judging whether the power loss indicator is to be abnormal power down；
Power down determination sub-module, for when the judging result of the mark judging submodule is to be abnormal power down, determining
It is abnormal power down during executing erasing operation.
9. device according to claim 6, which is characterized in that the nonvolatile memory includes physical block, the object
Reason block includes at least one storage unit, at least one bit line and at least one wordline, the bit line and at least one storage
The drain electrode of unit connects, and the wordline is connect with the grid of at least one storage unit, and an erasing region includes at least one
Storage unit,
The correction verification module includes：
Address search submodule, for searching the corresponding erasing region of the erasing regional address；
First applies submodule, for applying the voltage equal to 0 where the erasing region in each wordline of physical block；
Current detecting submodule is more than preset electric leakage for detecting in each bit line for wiping region with the presence or absence of electric current
Flow the bit line of threshold value；
Second applies submodule, in the presence of the testing result of the current detecting submodule is, being applied on the bit line
Add programming drain voltage, and calls the current detecting submodule；
Determination sub-module is verified, in the absence of the testing result of the current detecting submodule is, determining that described cross is wiped
Except verification executes completion.
10. the device according to claim 6 or 9, which is characterized in that further include：
Second logging modle, for it is described cross erasing verification execute after the completion of, the power loss indicator is recorded as not occurring different
The erasing regional address is recorded as sky by normal power down.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310741882.2A CN104751886B (en) | 2013-12-27 | 2013-12-27 | A kind of power-off protection method and device of nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310741882.2A CN104751886B (en) | 2013-12-27 | 2013-12-27 | A kind of power-off protection method and device of nonvolatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104751886A CN104751886A (en) | 2015-07-01 |
| CN104751886B true CN104751886B (en) | 2018-11-06 |
Family
ID=53591439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310741882.2A Active CN104751886B (en) | 2013-12-27 | 2013-12-27 | A kind of power-off protection method and device of nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104751886B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109872756A (en) * | 2017-12-01 | 2019-06-11 | 北京兆易创新科技股份有限公司 | A kind of memory method for deleting and device |
| CN109935266B (en) * | 2017-12-18 | 2021-03-09 | 北京兆易创新科技股份有限公司 | Memory cell leakage processing method and device and memory |
| CN109813982B (en) * | 2019-01-24 | 2021-05-14 | 深圳智链物联科技有限公司 | Charging pile power failure monitoring method and device, charging pile management platform and storage medium |
| CN111090542A (en) * | 2019-12-17 | 2020-05-01 | 深圳忆联信息系统有限公司 | Abnormal block identification method and device based on abnormal power failure and computer equipment |
| CN111667872A (en) * | 2020-05-26 | 2020-09-15 | 深圳市芯天下技术有限公司 | Method, system, storage medium and terminal device for power-on repair of over-erasure interference |
| CN112397128A (en) * | 2020-11-19 | 2021-02-23 | 潍柴动力股份有限公司 | Control method and device for Flash memory |
| CN113409853B (en) * | 2021-05-21 | 2023-08-25 | 芯天下技术股份有限公司 | Method, device, storage medium and terminal for reducing probability of reading error after power failure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101010668A (en) * | 2004-09-02 | 2007-08-01 | 英特尔公司 | Volatile storage based power loss recovery mechanism |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8208337B2 (en) * | 2009-12-21 | 2012-06-26 | Macronix International Co., Ltd. | Operation method and leakage controller for a memory and a memory applying the same |
-
2013
- 2013-12-27 CN CN201310741882.2A patent/CN104751886B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101010668A (en) * | 2004-09-02 | 2007-08-01 | 英特尔公司 | Volatile storage based power loss recovery mechanism |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104751886A (en) | 2015-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104751887B (en) | A kind of power-off protection method and device of nonvolatile memory | |
| CN104751886B (en) | A kind of power-off protection method and device of nonvolatile memory | |
| CN104751888B (en) | A kind of power-off protection method and device of nonvolatile memory | |
| CN108364667B (en) | Non-volatile memory device and programming method thereof | |
| US9529663B1 (en) | Detection and localization of failures in 3D NAND flash memory | |
| CN100530435C (en) | System and method for erase of non-volatile memory | |
| KR102170975B1 (en) | Nonvolatile memory device and defected wordline detection method thereof | |
| CN106158033B (en) | Memory circuit and its operating method | |
| US9330783B1 (en) | Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block | |
| CN103854700B (en) | The method for deleting and device of a kind of nonvolatile memory | |
| CN101430935B (en) | Detection method for over-erasing memory unit in flash memory | |
| CN102906712A (en) | MLC self-raid flash data protection scheme | |
| CN103680627A (en) | Semiconductor memory device | |
| CN103680614B (en) | Semiconductor memory devices and its operating method | |
| US9390809B1 (en) | Data storage in a memory block following WL-WL short | |
| CN101174459A (en) | Non-volatile semiconductor memory device using weak cells as reading identifier | |
| KR20190046330A (en) | Memory device including a circuit for detecting word line defect and operating method of the memory device | |
| CN101308703A (en) | Method for nrom array word line retry erasing and threshold voltage recovering | |
| KR20120005848A (en) | Non volatile memory device and erasing method therefor | |
| CN104637536A (en) | Flash memory device having efficient refresh operation | |
| KR20100011751A (en) | Test system and method | |
| CN102568578A (en) | Semiconductor storing apparatus, testing method thereof, and controlling method thereof | |
| CN109872756A (en) | A kind of memory method for deleting and device | |
| CN104376872B (en) | A kind of processing method interrupted to flash memory erasing | |
| WO2024032560A1 (en) | Method for over-erase repair, and storage apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
|
| CP03 | Change of name, title or address |