CN104750430B - A kind of access method of NAND Flash interface and device - Google Patents

Abstract

Do you the invention discloses a kind of NAND? the access method of Flash interface and device, define the interface of a series of command operating NAND particle; In application layer, according to the NAND particle manipulation that will realize, get out instruction set according to the agreement of NAND particle interface; Resolve instruction set in Physical layer, the interface of driving N AND particle, and control interface sequential, perform the instruction set in described step, realizes the access of NAND particle interface.Method of the present invention, without the need to design logic circuit, by the instruction of definition, carrys out the change of control interface, realizes access NAND particle interface; The instruction of the present invention's definition can be supported to access existing NAND particle, by the combination of these instructions, can also following NAND be tackled? the new situation occurred in flash development, and need not again add hardware to realize, greatly save time and cost.

Description

A kind of access method of NAND Flash interface and device

Technical field

The present invention relates to a kind of access method and device of NANDFlash interface.

Background technology

The advantages such as it is comparatively large that NANDflash storer (i.e. NAND) has capacity, and speed of rewriting is fast, are applicable to the storage of mass data, thus in the industry cycle obtain and apply more and more widely.To read and write NAND in a system, need a hardware control, the read-write of system be converted to the read-write under the interface of NAND particle definition.Fig. 1 is the interface diagram of NAND particle, and wherein RE and DQS is differential signal.Fig. 2 is the structural representation that system is read and write NAND particle.

Along with the development of Ge great NANDflash manufacturer, such that NANDflash's is of a great variety.Asynchronous interface is had, these five kinds of interface definition of toggle1, toggle2, ONFI2, ONFI3 from interface.Toggle2 with ONFI3 is substantially the same.

Fig. 3 is under the definition of toggle2 interface, writes the NAND interface signal diagram that data enter particle.Fig. 4 is under asynchronous interface definition, writes the NAND interface signal diagram that data enter particle.Contrast can be found out, the change of timing requirements and signal is different.In order to support the NAND particle of accessing these two kinds of interface definition, current way is when hardware logic designs, and adds corresponding logic control part.Between different NAND particle manufacturers (MICRON, HYNIX, TOSHIBA...), different operating processes is had for identical operation, so the control circui logic of corresponding particle manufacturer also will be added.As shown in Figure 5, also want to support more particle type, just need to add steering logic to hardware circuit.

According to existing way, when needing adaptive new NANDFlash interface features at every turn, logical circuit will be added toward controller chip, circuit design is become increasingly complex, be unfavorable for maintenance.Also may exist in former design, the risk that logical circuit supports New function can not be added again.These shortcomings can bring the great expense incurred on time and cost to the research and development of product.

Summary of the invention

Technical matters to be solved by this invention is, not enough for prior art, a kind of access method and device of NANDFlash interface are provided, make chip can adapt to existing all kinds NANDflash particle fast, also the new situation occurred can be tackled during following NANDflash develops, and need not again add hardware to realize, save time and cost.

For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of access method of NANDFlash interface, comprises the following steps:

1) interface of a series of command operating NAND particle is defined;

2) in application layer, according to the NAND particle manipulation that will realize and instruction defined above, instruction set is got out according to the agreement of NAND particle interface;

3) Physical layer resolve instruction set, the interface of driving N AND particle, and control interface sequential, perform described step 2) in instruction set, realize the access of NAND particle interface.

The instruction of described definition is as follows:

Title	Instruction width	Instruction description
			ALE	[1:0]	ALE order: 00-resets; 01-puts one; 10-reverses; 11-does not operate
CLE	[3:2]	CLE order, same to ALE
			REN	[5:4]	REN order, same to ALE
WEN	[7:6]	WEN order, same to ALE
			DQS	[9:8]	DQS order, same to ALE
CEN	[13:10]	Deliver to the data on CE
			REV	[15:14]	Reserved place, does not use
DQ	[23:16]	Deliver to the data on DQ
			WAIT	[31:24]	After executing instruction, the time of maintenance, i.e. cycle number

Above-mentioned instruction is the instruction of 32 bit widths, and the data width of General System is 32 bits, handled easily.

Present invention also offers a kind of access means of NANDFlash interface, comprising:

Application layer CPU: for the instruction of the interface of a series of operation NAND particle according to the NAND particle manipulation that will realize and definition, get out instruction set according to the agreement of NAND particle interface, and send described instruction set the operational code code translator of Physical layer to;

Operational code code translator: for resolving above-mentioned instruction set in Physical layer, the interface of driving N AND particle, control interface sequential, and the instruction set performing application layer CPU transmission, realize the access of NAND particle interface.

Described operational code code translator is connected with write data buffer, read data buffer.

Compared with prior art, the beneficial effect that the present invention has is: method of the present invention, without the need to design logic circuit, by the instruction of definition, carrys out the change of control interface, realizes access NAND particle interface; The instruction of the present invention's definition can be supported to access existing NAND particle, by the combination of these instructions, also can tackle during following NANDflash develops the new situation occurred, and need not again add hardware to realize, greatly save time and cost.

Accompanying drawing explanation

Fig. 1 is the interface diagram of NAND particle;

Fig. 2 is the structural representation that system is read and write NAND particle;

Fig. 3 is under the definition of toggle2 interface, writes the NAND interface singnal chart that data enter particle;

Fig. 4 is under asynchronous interface definition, writes the NAND interface singnal chart that data enter particle;

Fig. 5 adds the schematic diagram of steering logic to hardware circuit in prior art;

Fig. 6 is the hardware circuit diagram that the present invention adopts;

Fig. 7 is the signal waveforms of the NAND particle asynchronous interface of the embodiment of the present invention;

Fig. 8 is the signal waveforms under the definition of embodiment of the present invention toggle2 interface.

Embodiment

First need to define a series of instruction to operate the interface of NAND particle.

Here is the instruction example of 32 bit widths, and representated by each bit of the inside, implication is listed in the table.

Item	Width	Description
			ALE	[1:0]	ALE order: 00-resets; 01-puts one; 10-reverses; 11-does not operate
CLE	[3:2]	CLE order, same to ALE
			REN	[5:4]	REN order, same to ALE
WEN	[7:6]	WEN order, same to ALE
			DQS	[9:8]	DQS order, same to ALE
CEN	[13:10]	Deliver to the data on CE
			REV	[15:14]	Reserved place, does not use
DQ	[23:16]	Deliver to the data on DQ
			WAIT	[31:24]	After executing this instruction, the time (cycle number) of maintenance

In application layer, according to the NAND particle manipulation that will realize, get out instruction set.Such as want the operation of the data write performing NAND particle asynchronous interface, then instruction set can be:

0x00003850 (drive CE [3:0] to be 4 ' hE, chip enable (ChipEnable) is low effectively)

0x005538b0 (driving data signal DQ is 8 ' h55, and WE is reversed)

0x005538b0 (driving data signal DQ is 8 ' h55, and WE is reversed)

0x00aa38b0 (driving data signal DQ is 8 ' haa, and WE is reversed)

0x00aa38b0 (driving data signal DQ is 8 ' haa, and WE is reversed)

0x000038ff0 (driving data signal DQ is 8 ' h00, drives CE [3:0] to be 4 ' hF)

In Physical layer, instruction set resolved by the operational code code translator of Fig. 6, and the interface of driving N AND particle, and control interface sequential, meet timing requirements.Perform the instruction set prepared in above-mentioned application layer, realization signal waveform out as shown in Figure 7, meets the definition requirement of particle datasheet interface, data can be write into particle.

If data are write under first will realizing the definition of toggle2 interface the function of particle, then can by following instruction set.

0x00003850 (drive CE [3:0] to be 4 ' hE, chip enable (ChipEnable) is low effectively)

0x02123af0 (driving data signal DQ is 8 ' h12, and DQS is reversed)

0x01343af0 (driving data signal DQ is 8 ' h34, and DQS is reversed)

0x01563af0 (driving data signal DQ is 8 ' h56, and DQS is reversed)

0x01783af0 (driving data signal DQ is 8 ' h78, and DQS is reversed)

0x00003ef0 (driving data signal DQ is 8 ' h00, drives CE [3:0] to be 4 ' hF, and DQS is reversed)

Perform the signal waveform of above instruction set generation as Fig. 8.

Claims (3)

1. an access method for NANDFlash interface, is characterized in that, comprises the following steps:

1) interface of a series of command operating NAND particle is defined;

The instruction of described definition is as follows:

Title Instruction width Instruction description ALE [1:0] ALE order: 00-resets; 01-puts one; 10-reverses; 11-does not operate CLE [3:2] CLE order, same to ALE REN [5:4] REN order, same to ALE WEN [7:6] WEN order, same to ALE DQS [9:8] DQS order, same to ALE CEN [13:10] Deliver to the data on CE REV [15:14] Reserved place, does not use DQ [23:16] Deliver to the data on DQ WAIT [31:24] After executing instruction, the time of maintenance, i.e. cycle number

2) in application layer, according to the NAND particle manipulation that will realize and instruction defined above, instruction set is got out according to the agreement of NAND particle interface;

3) Physical layer resolve instruction set, the interface of driving N AND particle, and control interface sequential, perform described step 2) in instruction set, realize the access of NAND particle interface.

2. an access means for NANDFlash interface, is characterized in that, comprising:

Application layer CPU: for the instruction of the interface of a series of operation NAND particle according to the NAND particle manipulation that will realize and definition, get out instruction set according to the agreement of NAND particle interface, and send described instruction set the operational code code translator of Physical layer to; The instruction of described definition is as follows:

Title Instruction width Instruction description ALE [1:0] ALE order: 00-resets; 01-puts one; 10-reverses; 11-does not operate

CLE [3:2] CLE order, same to ALE REN [5:4] REN order, same to ALE WEN [7:6] WEN order, same to ALE DQS [9:8] DQS order, same to ALE CEN [13:10] Deliver to the data on CE REV [15:14] Reserved place, does not use DQ [23:16] Deliver to the data on DQ WAIT [31:24] After executing instruction, the time of maintenance, i.e. cycle number

Operational code code translator: for resolving above-mentioned instruction set in Physical layer, the interface of driving N AND particle, control interface sequential, and the instruction set performing application layer CPU transmission, realize the access of NAND particle interface.

3. the access means of NANDFlash interface according to claim 2, is characterized in that, described operational code code translator is connected with write data buffer, read data buffer.