CN117076351B - Memory access method and device based on ONFI PHY interface specification - Google Patents
Memory access method and device based on ONFI PHY interface specification Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 69
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- 229940044442 onfi Drugs 0.000 title claims abstract 10
- 230000003993 interaction Effects 0.000 claims abstract description 98
- 239000002245 particle Substances 0.000 claims abstract description 70
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- 239000008188 pellet Substances 0.000 claims description 19
- 238000004590 computer program Methods 0.000 claims description 12
- 239000008187 granular material Substances 0.000 claims description 8
- 230000002452 interceptive effect Effects 0.000 claims description 5
- 238000013461 design Methods 0.000 abstract description 8
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a memory access method and device based on ONFI PHY interface specification, which belongs to the technical field of memories, wherein the ONFI PHY interface specification defines a general interface between a memory controller and a physical layer and a corresponding interaction signal set, and the method comprises the following steps: determining target NAND particles to be accessed and corresponding access types in response to memory access triggering operation of a user; determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particles and the corresponding access types; the state of the target interaction signal is controlled based on the control time sequence to realize the access to the target NAND particles, so that the efficient access to the memory can be realized based on ONFI PHY interface specifications, the research and development efficiency of the chip is improved, and the design cost is reduced.
Description
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a memory access method and device based on ONFI PHY interface specifications.
Background
The Nand flash memory has been widely used in industry due to the advantages of large capacity and fast writing speed, and ONFI (Open NAND Flash Interface, open Nand flash memory interface) specifications are also becoming the currently mainstream Nand flash interface standard.
During the design of existing electronic systems, the ONFI memory interface is typically divided into two parts, namely a memory control logic (ONFI Controller) and a physical layer interface (ONFI PHY). However, because the designers of the ONFI Controller and the ONFI PHY are often different, in order to realize interconnection between the ONFI Controller and the ONFI PHY for memory access, corresponding hardware circuits and memory access methods are required to be designed in each time, so that the research and development efficiency of the chip is reduced, the design cost is increased, and the efficiency of memory access is greatly reduced.
Disclosure of Invention
The application provides a memory access method and device based on ONFI PHY interface specifications, which are used for solving the problems of low chip research and development efficiency, high design cost and low memory access efficiency in the prior art.
The application provides a memory access method based on ONFI PHY interface specification, wherein the ONFI PHY interface specification defines a general interface between a memory controller and a physical layer and a corresponding interaction signal set, and the method comprises the following steps:
responding to a memory access triggering operation of a user, and determining target NAND particles to be accessed and a corresponding access type;
determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type;
and controlling the state of the target interaction signal based on the control time sequence to realize the access to the target NAND particle.
According to the memory access method based on ONFI PHY interface specification, the interactive signal set comprises a command and address signal subset, a data bus signal subset and a custom signal subset;
the interaction signals in the command and address signal subsets are used for interfacing with a chip enabling interface, a read enabling interface, an address latch enabling interface, a command latch enabling interface, a write protection interface and a status interface of the NAND particle;
the interaction signals in the data bus signal subset are used for interfacing with the data interface of the NAND pellet;
the interaction signals in the custom signal subset are used for internal control of the physical layer and interaction with the non-memory access purpose of the memory controller.
According to the memory access method based on ONFI PHY interface specification, the interaction signals in the command and address signal subset include:
chip select control signal onfi_ce_n, chip enable interface for associating NAND particles;
the read enable control signals onfi_re_p0, onfi_re_p1, onfi_re_toggle_p0 and onfi_re_toggle_p1 are used for associating the read enable interface of the NAND particle;
address latch control signals onfi_ ale _p0 and onfi_ ale _p1 for address latch enable interfaces associated with NAND die;
command latch control signals onfi_cle_p0 and onfi_cle_p1 for a command latch enable interface associated with the NAND grain;
write enable control signals onfi_we_n_p0 and onfi_we_n_p1 for write enable interfaces associated with the NAND die;
write protection control signals onfi_wp_n_p0 and onfi_wp_n_p1 for write protection interfaces associated with the NAND particles;
the status indication signal onfi_rb_n is used to associate the status interface of the NAND pellet.
According to the memory access method based on ONFI PHY interface specification, the interactive signals in the data bus signal subset include:
write data indication signals onfi_wrdata_p0 and onfi_wrdata_p1 for indicating data written into the NAND pellet;
write data enable signals onfi_wrdata_en_p0 and onfi_wrdata_en_p0 for implementing writing data to the NAND grain in combination with a write data indication signal;
read data indication signals onfi_rddata_p0 and onfi_rddata_p1 for indicating data read from the NAND pellet;
read data valid identification signals onfi_rddata_valid_p0 and onfi_rddata_valid_p1 for indicating valid data read from the NAND granule;
the read data enable signals onfi_rddata_en_p0 and onfi_rddata_en_p1 are used for realizing reading data from the NAND particles in combination with a read data indication signal and a read data valid identification signal;
DQS status indication signals onfi_wrdqs_toggle_p0 and onfi_wrdqs_toggle_p1 for indicating DQS signal status;
DQS transmit enable signals onfi_wrdqs_en_p0 and onfi_wrdqs_en_p1 are used in combination with the DQS status indication signal to generate the transmit timing of the DQS signal.
According to the memory access method based on ONFI PHY interface specification, the interaction signals in the custom signal subset include:
a request signal onfi_ctrloupd_req is used for sending a request to the physical layer by the memory controller to complete the calibration work;
a response signal onfi_ctrlupd_ack for indicating the current state of the physical layer;
the initialization status signal onfi_init_complete is used for indicating whether the physical layer is initialized to be completed.
According to the memory access method based on the ONFI PHY interface specification, the data bit widths of onfi_re_toggle_p0, onfi_re_toggle_p1, onfi_wrdqs_toggle_p0 and onfi_wrdqs_toggle_p1 are all 2, when the value is 2' b00, the data bit width is low, when the value is 2' b01, the data bit width is high, when the value is 2' b10, the data bit width is overturned, and the overturned frequency is 2 times of the clock frequency of the memory controller.
According to the memory access method based on ONFI PHY interface specifications, the access types comprise read data and write data.
The present application also provides a memory access device based on ONFI PHY interface specification, where the ONFI PHY interface specification defines a generic interface between a memory controller and a physical layer and a corresponding set of interaction signals, and the device includes:
the first determining module is used for responding to the memory access triggering operation of the user and determining target NAND particles to be accessed and corresponding access types;
the second determining module is used for determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type;
and the access control module is used for controlling the state of the target interaction signal based on the control time sequence so as to realize the access to the target NAND particles.
The present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a memory access method based on the ONFI PHY interface specification as described in any one of the above.
The present application also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of a memory access method according to any one of the above-mentioned ONFI PHY interface specifications.
The memory access method and device based on ONFI PHY interface specification, wherein the ONFI PHY interface specification defines a general interface between a memory controller and a physical layer and a corresponding interaction signal set, and the method comprises the following steps: responding to a memory access triggering operation of a user, and determining target NAND particles to be accessed and a corresponding access type; determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type; the state of the target interaction signal is controlled based on the control time sequence to realize the access to the target NAND particles, so that the efficient access to the memory can be realized based on the ONFI PHY interface specification, meanwhile, the situation that corresponding hardware circuits and memory access methods are required to be specifically designed each time due to different designers of the ONFI Controller and the ONFI PHY can be avoided, the research and development efficiency of the chip is improved, and the design cost is reduced.
Drawings
For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a memory access method based on ONFI PHY interface specification provided in the present application;
fig. 2 is a schematic diagram of all interaction signals corresponding to ONFI PHY interface specifications provided in the present application;
FIG. 3 is a schematic diagram of a subset of command and address signals corresponding to the ONFI PHY interface specification provided herein;
FIG. 4 is a schematic diagram of a subset of data bus signals corresponding to the ONFI PHY interface specification provided herein;
fig. 5 is a schematic diagram of a custom signal subset corresponding to the ONFI PHY interface specification provided in the present application;
fig. 6 is a schematic structural diagram of a memory access device based on ONFI PHY interface specifications provided in the present application;
fig. 7 is a schematic structural diagram of an electronic device provided in the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Fig. 1 is a flow chart of a memory access method based on ONFI PHY interface specification provided in the present application, as shown in fig. 1, where the method includes:
step 101, determining a target NAND particle to be accessed and a corresponding access type in response to a memory access triggering operation of a user.
Specifically, the ONFI PHY interface specification defines a generic interface between a memory controller and a physical layer and a corresponding set of interaction signals. Based on the above, even if the designers of the ONFI Controller and the ONFI PHY are different, the interconnection between the ONFI Controller and the ONFI PHY can be realized based on the ONFI PHY interface specification to access the memory, and the corresponding hardware circuit and the memory access method are not required to be designed in a targeted manner, so that the research and development efficiency of the chip can be improved, the design cost can be reduced, and the memory access efficiency can be improved. More specifically, fig. 2 is a schematic diagram of all interaction signals corresponding to the ONFI PHY interface specification provided in the present application, as shown in fig. 2, where the interaction signal set includes a subset of command and address signals (i.e. ONFI addr/cmd signals in fig. 2), a subset of data bus signals (i.e. ONFI data signals in fig. 2), and a subset of custom signals (i.e. other ctrl signals in fig. 2);
the interaction signals in the command and address signal subsets are used for interfacing with a chip enabling interface, a read enabling interface, an address latch enabling interface, a command latch enabling interface, a write protection interface and a status interface of the NAND particle;
the interaction signals in the data bus signal subset are used for interfacing with the data interface of the NAND pellet;
the interaction signals in the custom signal subset are used for internal control of the physical layer and interaction with the non-memory access purpose of the memory controller.
Fig. 3 is a schematic diagram of a subset of command and address signals corresponding to the ONFI PHY interface specification provided in the present application, as shown in fig. 3, where interaction signals in the subset of command and address signals include:
chip select control signal onfi_ce_n, chip enable interface (i.e., ce_n pad) for associated NAND die;
read enable control signals onfi_re_p0, onfi_re_p1, onfi_re_toggle_p0, and onfi_re_toggle_p1 for associating a read enable interface (i.e., RE pad) of the NAND particle;
address latch control signals onfi_ ALE _p0 and onfi_ ALE _p1 for an address latch enable interface (i.e., ALE pad) associated with the NAND granule;
command latch control signals onfi_cycle_p0 and onfi_cycle_p1, command latch enable interface (i.e., CLE pad) for associated NAND grain;
write enable control signals onfi_we_n_p0 and onfi_we_n_p1 for write enable interfaces (i.e., we_n pad) associated with the NAND die;
write protection control signals onfi_wp_n_p0 and onfi_wp_n_p1 for write protection interfaces (i.e., wp_n pad) associated with the NAND grain;
the status indication signal onfi_rb_n is used to associate the status interface (i.e., rb_n pad) of the NAND die.
Wherein, the data bit width of onfi_ce_n is 1; the onfi_re_p0 and the onfi_re_p1 comprise two phases p0 and p1, and the data bit width is 1; the onfi_re_toggle_p0 and the onfi_re_toggle_p1 comprise two phases p0 and p1, and the data bit width is 2; onfi_ ale _p0 and onfi_ ale _p1 comprise two phases p0 and p1, and the data bit width is 1; the onfi_cle_p0 and the onfi_cle_p1 comprise two phases p0 and p1, and the data bit width is 1; the onfi_we_n_p0 and onfi_we_n_p1 comprise two phases p0 and p1, and the data bit width is 1; the onfi_wp_n_p0 and the onfi_wp_n_p1 comprise two phases p0 and p1, and the data bit width is 1; the onfi_rb_n data bit width is 1. The interaction signals in the command and address signal subsets are combined to realize control and state acquisition of the corresponding interfaces of the NAND particles, so that smooth sending of the addresses and the commands in the memory access process is ensured.
Fig. 4 is a schematic diagram of a subset of data bus signals corresponding to the ONFI PHY interface specification provided in the present application, as shown in fig. 4, where interaction signals in the subset of data bus signals include:
write data indication signals onfi_wrdata_p0 and onfi_wrdata_p1 for indicating data written into the NAND pellet;
write data enable signals onfi_wrdata_en_p0 and onfi_wrdata_en_p0 for implementing writing data to the NAND grain in combination with a write data indication signal;
read data indication signals onfi_rddata_p0 and onfi_rddata_p1 for indicating data read from the NAND pellet;
read data valid identification signals onfi_rddata_valid_p0 and onfi_rddata_valid_p1 for indicating valid data read from the NAND granule;
the read data enable signals onfi_rddata_en_p0 and onfi_rddata_en_p1 are used for realizing reading data from the NAND particles in combination with a read data indication signal and a read data valid identification signal;
DQS status indication signals onfi_wrdqs_toggle_p0 and onfi_wrdqs_toggle_p1 for indicating DQS signal status;
DQS transmit enable signals onfi_wrdqs_en_p0 and onfi_wrdqs_en_p1 are used in combination with the DQS status indication signal to generate the transmit timing of the DQS signal.
Wherein, the onfi_wrdata_p0 and the onfi_wrdata_p1 comprise two phases p0 and p1, and the data bit width is 16; the onfi_rddata_p0 and the onfi_rddata_p1 comprise two phases p0 and p1, and the data bit width is 16; the onfi_rddata_en_p0 and the onfi_rddata_en_p1 comprise two phases p0 and p1, and the data bit width is 1; the onfi_rddata_valid_p0 and the onfi_rddata_valid_p1 comprise two phases p0 and p1, and the data bit width is 1; the onfi_wrdqs_en_p0 and the onfi_wrdqs_en_p1 comprise two phases p0 and p1, and the data bit width is 1; the onfi_wrdqs_toggle_p0 and onfi_wrdqs_toggle_p1 comprise two phases p0 and p1, and the data bit width is 2. The data can be smoothly sent and received in the memory access process by combining the interactive signals in the data bus signal subsets.
It can be understood that the phase number corresponding to the above-mentioned interaction signal is only an example, and may be adjusted according to needs in the actual application process, which is not specifically limited in the embodiment of the present application.
Fig. 5 is a schematic diagram of a custom signal subset corresponding to an ONFI PHY interface specification provided in the present application, as shown in fig. 5, where an interaction signal in the custom signal subset includes:
a request signal onfi_ctrloupd_req is used for sending a request to the physical layer by the memory controller to complete the calibration work;
a response signal onfi_ctrlupd_ack for indicating the current state of the physical layer;
the initialization status signal onfi_init_complete is used for indicating whether the physical layer is initialized to be completed.
Based on the interaction signals in the custom signal subset, the processes of calibration, initialization and the like can be realized. Meanwhile, it can be understood that the custom signal subset may further include other user custom signals, and more control signals may be added according to the needs of the memory controller to achieve more application effects, which is not exhaustive in this embodiment of the present application.
In summary, through the ONFI PHY interface specification provided by the embodiment of the present application, the interface standard between the ONFI Controller and the ONFI PHY can be unified, and based on the unified interface standard, the development difficulty of the chip can be reduced, the development cost can be reduced, and the access efficiency of the memory can also be improved.
It can be understood that the memory access method based on the ONFI PHY interface specification in the embodiment of the present application is specifically applied to a memory controller, and after the memory controller detects a memory access trigger operation of a user, the memory controller can quickly determine a target NAND particle to be accessed and a corresponding access type, and perform efficient memory access based on the ONFI PHY interface specification.
Step 102, determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and a corresponding access type.
Specifically, the access type includes read data and write data, and it is understood that, whether the read operation or the write operation is performed, the access flow of the NAND grain is obtained by combining a command sending sub-flow, an address sending sub-flow, a data sending sub-flow and a data reading sub-flow, and the target interaction signals corresponding to different sub-flows are determined. Therefore, after the target NAND grain and the corresponding access type are determined, the target interaction signal and the corresponding control time sequence in the interaction signal set can be rapidly determined based on the normal access flow of the NAND grain.
And step 103, controlling the state of the target interaction signal based on the control time sequence to realize the access to the target NAND particle.
Specifically, after determining the target interaction signal and the corresponding control timing sequence, the memory controller can control the state of the target interaction signal based on the control timing sequence to realize access to the target NAND particle. In combination with the foregoing, it can be seen that, whether the access procedure of the NAND grain is a read operation or a write operation, the access procedure of the NAND grain is obtained by combining a command sending sub-procedure, an address sending sub-procedure, a data sending sub-procedure and a data reading sub-procedure, so that after determining the target interaction signals and the corresponding control time sequences of different sub-procedures based on the ONFI PHY interface specifications of the embodiment of the present application, the overall control time sequences corresponding to the specific access types can be determined quickly, thereby realizing efficient access of the NAND grain. More specifically, for the send command sub-flow, the method comprises the following steps: pull low onfi_ce_n at time T0 (select target NAND grain); at time T1, onfi_cle_p1 and onfi_cle_p0 are pulled high, onfi_we_n_p1 and onfi_we_n_p0 are pulled low, onfi_wrdata_en_p0, onfi_wrdata_en_p1 are pulled high, onfi_wrdata_p1[15:0] and onfi_wrdata_p0[15:0] assign 16 bits 8585 (preparation before sending command); at time T2, onfi_we_n_p1 and onfi_we_n_p0 are pulled high (commands have been started to be sent); at time T3, onfi_wrdata_en_p1 and onfi_wrdata_en_p0 are pulled low (release wrdata and wrdata_en buses); at time T4, onfi_cle_p1 and onfi_cle_p0 are pulled low (release onfi_cle bus). Based on the above flow, the requirement of sending commands to the NAND particles can be met, and correspondingly, the control of the CE_n pad, ALE pad, CLE pad and WE_n pad of the target NAND particles can be realized through the state control of the target interaction signals, so that the commands are sent to the data interface (namely DQ [7:0 ]) of the target NAND particles. For the address sending sub-process, the timing control process is similar to the command sending sub-process, and the embodiment of the present application will not be repeated herein, specifically referring to the conventional address sending process of NAND particles. It will be appreciated that the intervals between the times T0, T1, T2, T3, T4 are one clock cycle of the memory controller (the subsequent flow is the same as the above).
For the data sending sub-process and the data reading sub-process, corresponding DQS signals are controlled through the onfi_wrdqs_toggle_p0/onfi_wrqs_toggle_p1 and the onfi_re_toggle_p0/onfi_re_toggle_p1 respectively to realize data sending and data reading respectively. The data bit widths of the onfi_re_toggle_p0, the onfi_re_toggle_p1, the onfi_wrqs_toggle_p0 and the onfi_wrqs_toggle_p1 are all 2, when the value is 2' b00, the data bit width is represented by low level, when the value is 2' b01, the data bit width is represented by high level, when the value is 2' b10, the data bit width is represented by turnover, and the turnover frequency is 2 times of the clock frequency of the memory controller, based on the data bit widths, smooth sending and reading of the data can be realized.
Specifically, for the data transmission sub-process, the method includes the following steps: the onfi_wrdqs_toggle_p1 and onfi_wrdqs_toggle_p0 at time T0 are 2' b01, indicating that wrdqs (i.e., the DQS signal corresponding to the write data) is high level; the onfi_wrdqs_toggle_p1 and onfi_wrdqs_toggle_p0 at the time T1 are 2' b00, which represents a wrdqs low level; the onfi_wrqs_toggle_p1 and onfi_wrqs_toggle_p0 are 2'b10, indicating wrqs flip, and at this point onfi_wrdata_p1[15:0] and onfi_wrdata_p0[15:0] are assigned 16' bins 16'h3322 and 16' h1100; at the time of T3, onfi_wrdqs_toggle_p1 and onfi_wrdqs_toggle_p0 are 2' b00, which represents a wrdqs low level; at time T4, onfi_wrqs_toggle_p1 and onfi_wrqs_toggle_p0 are 2' b01, indicating a wrqs high level. Based on the above flow, the need for sending data to the NAND particle can be completed, and correspondingly, DQS signals and data signals can be sent to the target NAND particle through controlling the onfi_wrdqs_toggle_p1, onfi_wrdqs_toggle_p0, onfi_wrdata_p1[15:0] and onfi_wrdata_p0[15:0], thereby realizing the data sending sub-flow.
For the read data sub-flow, the method comprises the following steps: the onfi_wrdqs_toggle_p1 and onfi_wrdqs_toggle_p0 are 2' b01, the onfi_wrdqs_en_p1 and onfi_wrdqs_en_p0 are pulled high (control the initial state of the NAND granule DQS signal to be high); at time T1, onfi_re_toggle_p1 and onfi_re_toggle_p0 are 2' b00, which indicates that RE is pulled low; the onfi_wrdqs_en_p1 and onfi_wrdqs_en_p0 are pulled low (giving DQS control to the NAND granule) at time T2; the onfi_rddata_en_p1 and onfi_rddata_en_p0 are pulled high at time T3; onfi_re_toggle_p1 and onfi_re_toggle_p0 are 2' b10, which represents RE flip, controlling DQS signal sent by NAND particle; at time T4, onfi_re_toggle_p1 and onfi_re_toggle_p0 are 2' b00, indicating that RE is pulled down while onfi_rddata_en_p1 and onfi_rddata_en_p0 are pulled down, at this time the physical layer receives the data returned by the NAND particle while onfi_rddata_valid_p1 and onfi_rddata_valid_p0 are pulled up, and data is sent to the memory controller. Based on the above process, the need of reading data from the NAND grain can be completed, and correspondingly, the data signal can be obtained from the target NAND grain by controlling the signals, thereby realizing the data reading sub-process.
In summary, after determining the target interaction signals and the corresponding control timings of different sub-flows based on the ONFI PHY interface specification in the embodiment of the present application, the overall control timing corresponding to the specific access type may be determined quickly, so as to achieve efficient access of NAND particles.
The method provided by the embodiment of the application, the ONFI PHY interface specification defines a general interface between a memory controller and a physical layer and a corresponding interaction signal set, and the method includes: responding to a memory access triggering operation of a user, and determining target NAND particles to be accessed and a corresponding access type; determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type; the state of the target interaction signal is controlled based on the control time sequence to realize the access to the target NAND particles, so that the efficient access to the memory can be realized based on the ONFI PHY interface specification, meanwhile, the situation that corresponding hardware circuits and memory access methods are required to be specifically designed each time due to different designers of the ONFI Controller and the ONFI PHY can be avoided, the research and development efficiency of the chip is improved, and the design cost is reduced.
Based on any of the above embodiments, fig. 6 is a schematic structural diagram of a memory access device provided in the present application and based on ONFI PHY interface specifications, as shown in fig. 6, where the ONFI PHY interface specifications define a generic interface between a memory controller and a physical layer and a corresponding set of interaction signals, and the device includes:
a first determining module 201, configured to determine a target NAND grain to be accessed and a corresponding access type in response to a memory access triggering operation of a user;
a second determining module 202, configured to determine a target interaction signal and a corresponding control timing sequence in the interaction signal set based on the target NAND grain to be accessed and a corresponding access type;
and the access control module 203 is used for controlling the state of the target interaction signal based on the control time sequence so as to realize the access to the target NAND particle.
The apparatus provided in this embodiment of the present application, the ONFI PHY interface specification defines a general interface between a memory controller and a physical layer and a corresponding set of interaction signals, where the apparatus includes: a first determining module 201, configured to determine a target NAND grain to be accessed and a corresponding access type in response to a memory access triggering operation of a user; a second determining module 202, configured to determine a target interaction signal and a corresponding control timing sequence in the interaction signal set based on the target NAND grain to be accessed and a corresponding access type; the access control module 203 is configured to control the state of the target interaction signal based on the control timing sequence to achieve access to the target NAND particle, so that efficient access to the memory can be achieved based on the ONFI PHY interface specification, and meanwhile, the situation that corresponding hardware circuits and memory access methods are required to be specifically designed each time due to different designers of the two parts of the ONFI Controller and the ONFI PHY can be avoided, and therefore research and development efficiency of the chip is improved, and design cost is reduced.
Based on the above embodiment, the interaction signal set includes a subset of command and address signals, a subset of data bus signals, and a subset of custom signals;
the interaction signals in the command and address signal subsets are used for interfacing with a chip enabling interface, a read enabling interface, an address latch enabling interface, a command latch enabling interface, a write protection interface and a status interface of the NAND particle;
the interaction signals in the data bus signal subset are used for interfacing with the data interface of the NAND pellet;
the interaction signals in the custom signal subset are used for internal control of the physical layer and interaction with the non-memory access purpose of the memory controller.
Based on any of the above embodiments, the interaction signals in the subset of command and address signals include:
chip select control signal onfi_ce_n, chip enable interface for associating NAND particles;
the read enable control signals onfi_re_p0, onfi_re_p1, onfi_re_toggle_p0 and onfi_re_toggle_p1 are used for associating the read enable interface of the NAND particle;
address latch control signals onfi_ ale _p0 and onfi_ ale _p1 for address latch enable interfaces associated with NAND die;
command latch control signals onfi_cle_p0 and onfi_cle_p1 for a command latch enable interface associated with the NAND grain;
write enable control signals onfi_we_n_p0 and onfi_we_n_p1 for write enable interfaces associated with the NAND die;
write protection control signals onfi_wp_n_p0 and onfi_wp_n_p1 for write protection interfaces associated with the NAND particles;
the status indication signal onfi_rb_n is used to associate the status interface of the NAND pellet.
Based on any of the above embodiments, the interaction signals in the subset of data bus signals include:
write data indication signals onfi_wrdata_p0 and onfi_wrdata_p1 for indicating data written into the NAND pellet;
write data enable signals onfi_wrdata_en_p0 and onfi_wrdata_en_p0 for implementing writing data to the NAND grain in combination with a write data indication signal;
read data indication signals onfi_rddata_p0 and onfi_rddata_p1 for indicating data read from the NAND pellet;
read data valid identification signals onfi_rddata_valid_p0 and onfi_rddata_valid_p1 for indicating valid data read from the NAND granule;
the read data enable signals onfi_rddata_en_p0 and onfi_rddata_en_p1 are used for realizing reading data from the NAND particles in combination with a read data indication signal and a read data valid identification signal;
DQS status indication signals onfi_wrdqs_toggle_p0 and onfi_wrdqs_toggle_p1 for indicating DQS signal status;
DQS transmit enable signals onfi_wrdqs_en_p0 and onfi_wrdqs_en_p1 are used in combination with the DQS status indication signal to generate the transmit timing of the DQS signal.
Based on any of the above embodiments, the interaction signals in the custom signal subset include:
a request signal onfi_ctrloupd_req is used for sending a request to the physical layer by the memory controller to complete the calibration work;
a response signal onfi_ctrlupd_ack for indicating the current state of the physical layer;
the initialization status signal onfi_init_complete is used for indicating whether the physical layer is initialized to be completed.
Based on any of the above embodiments, the data bit widths of the onfi_re_toggle_p0, onfi_re_toggle_p1, onfi_wrdqs_toggle_p0, and onfi_wrdqs_toggle_p1 are all 2, and represent low level when the value is 2' b00, high level when the value is 2' b01, flip when the value is 2' b10, and the flip frequency is 2 times the clock frequency of the memory controller.
Based on any of the above embodiments, the access type includes read data and write data.
Fig. 7 illustrates a physical schematic diagram of an electronic device, as shown in fig. 7, which may include: processor 301, communication interface 302, memory 303 and communication bus 304, wherein processor 301, communication interface 302, memory 303 accomplish the intercommunication through communication bus 304. The processor 301 may invoke logic instructions in the memory 303 to perform the memory access method based on the ONFI PHY interface specification provided by the methods described above, the method comprising: responding to a memory access triggering operation of a user, and determining target NAND particles to be accessed and a corresponding access type; determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type; and controlling the state of the target interaction signal based on the control time sequence to realize the access to the target NAND particle.
Further, the logic instructions in the memory 303 may be implemented in the form of software functional units and stored in a computer readable storage medium when sold or used as a stand alone product. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
In another aspect, the present application further provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, where the computer program when executed by a processor can perform a memory access method based on ONFI PHY interface specifications provided by the above methods, where the method includes: responding to a memory access triggering operation of a user, and determining target NAND particles to be accessed and a corresponding access type; determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type; and controlling the state of the target interaction signal based on the control time sequence to realize the access to the target NAND particle.
In yet another aspect, the present application further provides a non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor, is implemented to perform a memory access method based on ONFI PHY interface specifications provided by the methods above, the method comprising: responding to a memory access triggering operation of a user, and determining target NAND particles to be accessed and a corresponding access type; determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type; and controlling the state of the target interaction signal based on the control time sequence to realize the access to the target NAND particle.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a ROM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (6)
1. A memory access method based on ONFI PHY interface specifications, wherein the ONFI PHY interface specifications define a generic interface between a memory controller and a physical layer and a corresponding set of interaction signals, the method comprising:
responding to a memory access triggering operation of a user, and determining target NAND particles to be accessed and a corresponding access type;
determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type;
controlling the state of the target interaction signal based on the control timing sequence to realize access to target NAND particles;
the interactive signal set comprises a command signal subset, an address signal subset, a data bus signal subset and a custom signal subset;
the interaction signals in the command and address signal subsets are used for interfacing with a chip enabling interface, a read enabling interface, an address latch enabling interface, a command latch enabling interface, a write protection interface and a status interface of the NAND particle;
the interaction signals in the data bus signal subset are used for interfacing with the data interface of the NAND pellet;
the interaction signals in the custom signal subset are used for the internal control of the physical layer and the interaction with the non-memory access purpose of the memory controller;
the interaction signals in the subset of command and address signals include:
chip select control signal onfi_ce_n, chip enable interface for associating NAND particles;
the read enable control signals onfi_re_p0, onfi_re_p1, onfi_re_toggle_p0 and onfi_re_toggle_p1 are used for associating the read enable interface of the NAND particle;
address latch control signals onfi_ ale _p0 and onfi_ ale _p1 for address latch enable interfaces associated with NAND die;
command latch control signals onfi_cle_p0 and onfi_cle_p1 for a command latch enable interface associated with the NAND grain;
write enable control signals onfi_we_n_p0 and onfi_we_n_p1 for write enable interfaces associated with the NAND die;
write protection control signals onfi_wp_n_p0 and onfi_wp_n_p1 for write protection interfaces associated with the NAND particles;
a status indication signal onfi_rb_n for associating a status interface of the NAND pellet;
the interaction signals in the subset of data bus signals include:
write data indication signals onfi_wrdata_p0 and onfi_wrdata_p1 for indicating data written into the NAND pellet;
write data enable signals onfi_wrdata_en_p0 and onfi_wrdata_en_p0 for implementing writing data to the NAND grain in combination with a write data indication signal;
read data indication signals onfi_rddata_p0 and onfi_rddata_p1 for indicating data read from the NAND pellet;
read data valid identification signals onfi_rddata_valid_p0 and onfi_rddata_valid_p1 for indicating valid data read from the NAND granule;
the read data enable signals onfi_rddata_en_p0 and onfi_rddata_en_p1 are used for realizing reading data from the NAND particles in combination with a read data indication signal and a read data valid identification signal;
DQS status indication signals onfi_wrdqs_toggle_p0 and onfi_wrdqs_toggle_p1 for indicating DQS signal status;
DQS transmit enable signals onfi_wrdqs_en_p0 and onfi_wrdqs_en_p1 for generating transmit timing of the DQS signal in combination with the DQS status indication signal;
the interaction signals in the custom signal subset include:
a request signal onfi_ctrloupd_req is used for sending a request to the physical layer by the memory controller to complete the calibration work;
a response signal onfi_ctrlupd_ack for indicating the current state of the physical layer;
the initialization status signal onfi_init_complete is used for indicating whether the physical layer is initialized to be completed.
2. The memory access method based on ONFI PHY interface specification of claim 1, wherein data bit widths of onfi_re_toggle_p0, onfi_re_toggle_p1, onfi_wrdqs_toggle_p0, and onfi_wrdqs_toggle_p1 are all 2, and represent low level when the value is 2' b00, high level when the value is 2' b01, flip when the value is 2' b10, and the flip frequency is 2 times of the clock frequency of the memory controller.
3. The method of claim 2, wherein the access type includes read data and write data.
4. A memory access device based on ONFI PHY interface specifications defining a generic interface between a memory controller and a physical layer and a corresponding set of interaction signals, the device comprising:
the first determining module is used for responding to the memory access triggering operation of the user and determining target NAND particles to be accessed and corresponding access types;
the second determining module is used for determining a target interaction signal and a corresponding control time sequence in the interaction signal set based on the target NAND particle to be accessed and the corresponding access type;
the access control module is used for controlling the state of the target interaction signal based on the control time sequence so as to realize the access to the target NAND particles;
the interactive signal set comprises a command signal subset, an address signal subset, a data bus signal subset and a custom signal subset;
the interaction signals in the command and address signal subsets are used for interfacing with a chip enabling interface, a read enabling interface, an address latch enabling interface, a command latch enabling interface, a write protection interface and a status interface of the NAND particle;
the interaction signals in the data bus signal subset are used for interfacing with the data interface of the NAND pellet;
the interaction signals in the custom signal subset are used for the internal control of the physical layer and the interaction with the non-memory access purpose of the memory controller;
the interaction signals in the subset of command and address signals include:
chip select control signal onfi_ce_n, chip enable interface for associating NAND particles;
the read enable control signals onfi_re_p0, onfi_re_p1, onfi_re_toggle_p0 and onfi_re_toggle_p1 are used for associating the read enable interface of the NAND particle;
address latch control signals onfi_ ale _p0 and onfi_ ale _p1 for address latch enable interfaces associated with NAND die;
command latch control signals onfi_cle_p0 and onfi_cle_p1 for a command latch enable interface associated with the NAND grain;
write enable control signals onfi_we_n_p0 and onfi_we_n_p1 for write enable interfaces associated with the NAND die;
write protection control signals onfi_wp_n_p0 and onfi_wp_n_p1 for write protection interfaces associated with the NAND particles;
a status indication signal onfi_rb_n for associating a status interface of the NAND pellet;
the interaction signals in the subset of data bus signals include:
write data indication signals onfi_wrdata_p0 and onfi_wrdata_p1 for indicating data written into the NAND pellet;
write data enable signals onfi_wrdata_en_p0 and onfi_wrdata_en_p0 for implementing writing data to the NAND grain in combination with a write data indication signal;
read data indication signals onfi_rddata_p0 and onfi_rddata_p1 for indicating data read from the NAND pellet;
read data valid identification signals onfi_rddata_valid_p0 and onfi_rddata_valid_p1 for indicating valid data read from the NAND granule;
the read data enable signals onfi_rddata_en_p0 and onfi_rddata_en_p1 are used for realizing reading data from the NAND particles in combination with a read data indication signal and a read data valid identification signal;
DQS status indication signals onfi_wrdqs_toggle_p0 and onfi_wrdqs_toggle_p1 for indicating DQS signal status;
DQS transmit enable signals onfi_wrdqs_en_p0 and onfi_wrdqs_en_p1 for generating transmit timing of the DQS signal in combination with the DQS status indication signal;
the interaction signals in the custom signal subset include:
a request signal onfi_ctrloupd_req is used for sending a request to the physical layer by the memory controller to complete the calibration work;
a response signal onfi_ctrlupd_ack for indicating the current state of the physical layer;
the initialization status signal onfi_init_complete is used for indicating whether the physical layer is initialized to be completed.
5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor performs the steps of the memory access method based on ONFI PHY interface specification of any one of claims 1 to 3 when the program is executed.
6. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the steps of the memory access method based on ONFI PHY interface specification of any one of claims 1 to 3.
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