CN1047483C

CN1047483C - Power converter and method of manufacturing the same

Info

Publication number: CN1047483C
Application number: CN95104866A
Authority: CN
Inventors: 冈山秀夫; 福盛久
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1994-10-26
Filing date: 1995-05-15
Publication date: 1999-12-15
Anticipated expiration: 2015-05-15
Also published as: DE19541111B4; JP3213671B2; DE19541111A1; JPH08126302A; CN1122068A

Abstract

A power converter is provided with a self-extinction semiconductor element, a snubber circuit composed of a snubber diode and a snubber capacitor connected in series, broad belt-like conductors which connect the semiconductor element, a diode, and a capacitor to each other and the semiconductor element, diode, and capacitor are arranged so that the surfaces of their electrodes can become parallel to each other. The conductors which connect the electrodes to each other are arranged in parallel with the surfaces of the electrodes. The electrodes are arranged in line in the top view of the power converter and, of the conductors, those through which electric currents flow in the opposite direction are brought nearer to the electrodes.

Description

Power converter and manufacture method thereof

The present invention relates to a kind of power converter,, relate in particular to a kind of layout and method that parts is connected the buffer circuit (snubber circuit) that is used for protecting thyristor as adopting the inverter of thyristor.

Figure 29 has briefly shown the common power converter of an example; this example is openly put down in 4 (1992)-No. 229078 open in Japan's special permission application; more precisely, Figure 29 shows layout and the method that parts is connected the buffer circuit that is used for protecting thyristor.Among this figure, comprising a turn-off thyristor as thyristor (below be abbreviated as GTO) 1, a buffering diode 2 and a buffer condenser 3, is that thyristor 1 constitutes shunt circuit by buffering diode 2 and buffering capacitor 3 buffer circuit of forming that is connected in series wherein.Also comprise capacitor cover 4, connector 6, connector 7 and fin 9 in addition, wherein capacitor cover 4 is positioned at buffer condenser 3 one ends becomes the one electrode, and another electrode 5 of buffer condenser 3 forms at its other end; Connector 6 is used to be electrically connected the anode of buffering diode 2 and the electrode 4 of buffering capacitor 3; Connector 7 is used to be electrically connected another electrode 5 of GTO 1 and buffering capacitor 3; And fin 9 is GTO 1 and 2 heat radiations of buffering diode.The description of being given in the above-mentioned patent application document is based on such thought, promptly reduce the stray inductance that is present in the buffer circuit by a kind of the configuration, in this configuration, an end 4 of forming the buffer condenser 3 of the buffer circuit that is connected to GTO 1 surrounds the capacitor cover of the high conductivity of capacitor 3 as part, and this configuration also is enough to make the length of buffer circuit wire loop the shortest.Advise that wherein used GTO 1 has the cut-off current of about 2 kiloamperes and the rated voltage of 4.5 kilovolts.Silicon chip diameter with typical known GTO of electrical ratings like this is approximately 4 inches.And the direct capacitance of the buffer condenser of wherein describing 3 is 2.5 microfarads.The buffering diode 2 that is adopted in the simultaneously above-mentioned known example is a kind of special bolt shape diodes with low rated current and relatively large stray inductance.This buffering diode 2 links to each other with fin 9 regularly.

Because common power converter is constructed as mentioned above in the prior art, therefore when applying thyristor when (as having developed and have a GTO that the novel silicon chip of 6 inches or larger diameter is made at present by using), its electrical ratings is greater than 6 kilovolts and 6 kiloamperes.Therefore, desirable insulation level is different from the insulation level that any common silicon chip diameter is approximately 4 inches GTO fully, and required insulated lengths is longer than known numeric value inevitably.In addition, the electric current that increase is cut off by the shutoff of self-extinction of arc semiconductor element, the result can make the electric current that branches in the buffer circuit increase, therefore need provide big rated current and big direct capacitance (as, when cut-off current is 6 kiloamperes, electric capacity is approximately 6 microfarads) buffer condenser, also have buffering diode, thereby the distance between the link can be elongated inevitably.The extended wire loop of buffer circuit of result is even and directly use common buffer circuit method of attachment and also be difficult to keep in the prior art about making the shortest basic thought of wire loop length.Although in above-mentioned known example, do not mention the GTO switching frequency, if but improve the GTO switching frequency for the control performance that improves self-extinction of arc semiconductor element (as power converter), the effective current that then flows into buffer circuit can increase, the size of buffer condenser and buffering diode is increased, thereby make the maintenance of aforementioned basic thought more difficult.

Owing to be present in the growth of the stray inductance in the buffer circuit, the turn-off power loss that the thyristor electric current causes when disconnecting also increases.Below will make an explanation to this phenomenon referring to Figure 30.Negative and positive voltage across poles V when the figure shows the thyristor failure of current _AKHarmonizing yinyang electrode current I _AKTypical waveform.When the numerical value of the electric current in the thyristor during from failure of current began to surrender, any remaining electric current was branched in the buffer circuit.Fen Liu electric current I like this _SNProduce a charging voltage V to buffer condenser _CSIn addition, by-pass current I _SNTo be equal to the surrender electric current I shown in Figure 30 _AKThe current changing rate of current changing rate di/dt absolute value change, thereby in buffer circuit, produce by the determined voltage V of the product of this current changing rate and stray inductance _LSThe transient voltage V that is produced in the while buffering diode _DSGrowth with current changing rate di/dt absolute value increases.Therefore, the voltage that is applied on the thyristor is the charging voltage V of buffer condenser _CS, stray inductance induced voltage V _LSAnd the transient voltage V in the buffering diode _DSSum, thus produce as moment T among Figure 30 ₁Shown in peak voltage.T when thyristor turn-offs fully ₁Constantly, no longer produce by the electric current I that branches to buffer circuit _SNThe voltage that causes of rate of change di/dt, thereby be added in voltage V on the thyristor _AKBe decreased to the charging voltage V that has only buffer condenser _CSThe energy that is accumulated in simultaneously in the stray inductance produces superfluous charging voltage at the buffer condenser two ends, and this voltage becomes at T ₂Increase the maximum V that adds to the voltage on the thyristor constantly _DMOne of factor.Since can be roughly by the electric current I of thyristor _AKWith voltage V _AKProduct calculate the loss of thyristor at its blocking interval, the stray inductance that therefore is present in the buffer circuit increases this loss.It should be noted that this loss is not only a factor that reduces power converter efficient, and, may destroy the poised state relevant with the heat-sinking capability of thyristor according to the degree of loss, last because the rising of total moisture content causes damage of elements.

If the stray inductance that is present in the buffer circuit so is increased; then buffer circuit can't be realized the semi-conductive basic function of its protection self-extinction of arc; on the contrary; the reliability that may reduce power converter when using thyristor maybe needs to reduce cut-off current, thereby reduces the serviceability of element.

Finished the present invention in the process attempting to address the above problem.The object of the present invention is to provide a kind of modified model power converter that adopts the big thyristor of electrical ratings; even wherein the parts of buffer circuit are large-sized, also can reduce to be present in the stray inductance in the buffer circuit that is used for protecting semiconductor element.

According to a first aspect of the invention, a kind of power converter is provided, the placement that wherein two electrode surfaces of the anode surface of the anode surface of thyristor and cathode plane, buffering diode and cathode plane and buffer condenser is parallel to each other, and these thyristors, buffering diode and buffering capacitor are interconnected with the wide conductor of placing that is parallel to each other.

According to a second aspect of the invention, a kind of power converter is provided, wherein thyristor, buffering diode and buffering capacitor are installed by this way and be connected, be about to the center of thyristor anode surface and cathode plane, the anode surface of buffering diode and the center of cathode plane and the mutual centering in center of two electrode surfaces of buffer condenser and place.

According to a third aspect of the present invention, a kind of power converter is provided, wherein for anode surface and cathode plane, the anode surface of buffering diode and two electrode surfaces of cathode plane and buffer condenser of thyristor, in order to the width of the wide conductor that connects two above-mentioned electrode surfaces at least greater than less one width in these two electrode surfaces.

According to a fourth aspect of the present invention, provide a kind of power converter, wherein about a plurality of wide conductors, two conductors that are superimposed with each other in the disposition-plan like this, make conductor narrower in the plane graph be included in broad within.

According to a fifth aspect of the present invention, provide a kind of power converter,,, and they are intercoupled adjacent and closely place mutually with the pair of conductors that the phase negative side passes to electric current wherein about a plurality of wide conductors.

According to a sixth aspect of the invention, provide a kind of power converter,, place part to such an extent that be parallel to and approach a pair of adjacently and be connected with the electric conductor of reverse current, and these parts are intercoupled wherein about a plurality of wide conductors.

According to a seventh aspect of the present invention, provide a kind of power converter, wherein form the circuit of forming by thyristor, buffering diode, buffer condenser and wide conductor like this, make its area in end view less than its whole sectional area.

Because said structure, power converter of the present invention can reduce the inductance in the buffer circuit, thus the loss when reducing thyristor and turn-offing.

According to an eighth aspect of the present invention, provide a kind of power converter, wherein make the wide conductor of two electrodes that are connected to buffer condenser parallel close to each other, and dielectric is inserted between this paired wide conductor with the formation antithetical phrase.

Because said structure, power converter of the present invention can improve the electric capacity of buffer condenser equivalently, thus the loss when reducing thyristor and turn-offing.

According to a ninth aspect of the present invention, provide a kind of combination of power converter, this combination comprises a plurality of power converters with said structure, and wherein each thyristor is connected in series or the connection in series-parallel connection mutually.In this case, can be reduced in the inductance of each buffer circuit in high voltage or the big electric capacity power converter, thus the loss when reducing each self-extinction of arc semiconductor element and turn-offing.

According to a tenth aspect of the present invention, adopt the combination of power converter, a three-level inverter is provided with said structure.In this case, can reduce the inductance in each buffer circuit, thus the loss when reducing each thyristor and turn-offing.

And, according to an eleventh aspect of the present invention, provide a kind of method of making power converter.This method comprises following steps: with the placement that is parallel to each other of all thyristors, buffering diode and buffering capacitor; And thyristor, buffering diode and buffering capacitor are interconnected with parallel wide conductor.Because do not need known U type bending process or similar process, thus assembly work can be simplified, thus save production cost.

Fig. 1 is the end view of buffer circuit structure in the first embodiment of the invention;

Fig. 2 is the plane graph of buffer circuit structure in the first embodiment of the invention;

Fig. 3 is the key diagram of explanation buffer condenser electrode centers;

Fig. 4 has shown the structural model of buffer circuit;

Fig. 5 shows the inductance characteristic of buffer circuit in Fig. 4 model with curve;

Fig. 6 is the end view of buffer circuit structure in the second embodiment of the invention;

Fig. 7 is the plane graph of buffer circuit structure in the second embodiment of the invention;

Fig. 8 is the end view of buffer circuit structure in the third embodiment of the invention;

Fig. 9 is the end view of buffer circuit structure in the fourth embodiment of the invention;

Figure 10 is the end view of buffer circuit structure in the fifth embodiment of the invention;

Figure 11 is the end view of buffer circuit structure in the sixth embodiment of the invention;

Figure 12 is the plane graph of buffer circuit structure in the seventh embodiment of the invention;

Figure 13 is the plane graph of buffer circuit structure in the eighth embodiment of the invention;

Figure 14 is the end view of buffer circuit structure in the ninth embodiment of the invention;

Figure 15 A-15D shows the connection of buffer circuit under the thyristor series connection situation and gives an example;

Figure 16 is the plane graph of buffer circuit structure in the tenth embodiment of the invention;

Figure 17 is the end view of buffer circuit structure in the tenth embodiment of the invention;

Figure 18 is the circuit diagram of three-level inverter in the eleventh embodiment of the invention;

Figure 19 A and 19B are the key diagrams that explanation is applicable to the buffer circuit working condition of the three-level inverter in the eleventh embodiment of the invention;

Figure 20 is the end view of buffer circuit structure in the eleventh embodiment of the invention;

Figure 21 is the opposite side view of buffer circuit structure in the eleventh embodiment of the invention;

Figure 22 is the circuit diagram of the three-level inverter in the twelveth embodiment of the invention;

Figure 23 A and 23B are the key diagrams that explanation is applicable to the buffer circuit working condition of the three-level inverter in the twelveth embodiment of the invention;

Figure 24 is the end view of buffer circuit structure in the twelveth embodiment of the invention;

Figure 25 is the opposite side view of buffer circuit structure in the twelveth embodiment of the invention;

Figure 26 is the end view of buffer circuit structure in the thriteenth embodiment of the invention;

Figure 27 is the opposite side view of buffer circuit structure in the thriteenth embodiment of the invention;

Figure 28 is the end view of buffer circuit structure in the fourteenth embodiment of the invention;

Figure 29 is common buffer circuit structure; And

Figure 30 is the key diagram that explanation is applicable to the buffer circuit working condition of thyristor.

Below, narrate embodiments of the invention in conjunction with the accompanying drawings.Embodiment 1:

Below will first embodiment of the present invention be described referring to accompanying drawing.Fig. 1 is the end view that shows the buffer circuit structure that is used for thyristor.Although use the example of turn-off thyristor (being designated hereinafter simply as GTO) here as thyristor 1, if but the electrode surface of other any kind elements is flat, then also can use, they comprise turn-off thyristor, IGBT, silicon wafer brake tube (SI thyristor), semiconductor integrated circuit (SIC) of reverse-conducting or the like.Among Fig. 1, omitted used current regulator diode, buffer resistance device and optional feature in the buffering energy regenerative circuit.But described parts are useful naturally in the basic structure shown in this figure.Should see in addition, also omit any insulator and pressure Welding Structure here.Fig. 1 comprises GTO 1, the flat buffering diode 2 of non-screw bolt-type, buffer condenser 3, be connected on the fin (or conductor) 10 of GTO 1 anode with Pressure Welding, be connected on the fin (or conductor) 11 of GTO 1 negative electrode with Pressure Welding, the

electrode

12 and 13 of buffer condenser 3 is connected electrically to fin 10 (extension of GTO 1 anode) the banded wide conductor 14 of the anode of buffering diode 2, the negative electrode of buffering diode 2 is connected electrically to the wide conductor 15 of an electrode 12 of buffer condenser 3 and the wide conductor 16 that another electrode 13 of buffer condenser 3 is connected electrically to fin 11 (extension of GTO 1 negative electrode).Can be by being fin 10 wide conductors 14 of assembling or the additional function that obtains to cool off buffering diode 2 such as suitable heat abstractors such as independent fin that is equipped with.

At first describe " parallel position relationship between electrode surface ".Shown in the end view of buffer circuit structure among Fig. 1, the placement of whole 6 electrodes relation is an angulation not mutually, promptly, two electrodes 12 of the anode surface of buffering diode 2 and cathode plane and

buffer condenser

3 and 13 face, their expansion planes separately are spatially not crossing with anode surface or the cathode plane of GTO 1.Here we call " parallel position relationship of electrode surface " to this position relation.Because this configuration makes mounting technology compare and can obviously simplify with the normal conditions of prior art, thereby reduce the complexity of assembly work.

When making power converter of the present invention, process comprises following steps: arrange GTO 1, buffering diode 2 and buffering capacitor 3 at first by this way, electrode surface separately is parallel to each other; Is connected GTO1, buffering diode 2 with 16 with the wide conductor that is parallel to each other 14,15 then and cushions the electrode surface of capacitor 3.

Because need not specially is that

wide conductor

14,15 and 16 carries out the crooked or similarly routine work of U type, therefore can save the production cost about these conductors.And this structure realized the parallel position relationship of following wide conductor easily, thereby reduced the inductance of circuit.

" the linear position relation between electrode surface " will be described below.Fig. 2 has shown the plane graph of buffer circuit structure.For convenience of explanation, Fig. 2 shows being connected of being connected of being connected of GTO 1 and buffering diode 2, buffering diode 2 and buffer condenser 3 and buffer condenser 3 and GTO 1 individually.But, in fact be superimposed with each other during these part devices.As shown in Figure 2, prerequisite is such position relation, so that in top view, pass GTO 1 center A and buffering diode 2 center B central line AB, pass buffering diode 2 center B and buffering capacitor 3 one electrodes 12 center C central line BC and pass the center D of buffer condenser 3 another electrodes 13 and the central line DA of GTO 1 center A arranges in a line mutually.Here this position relation is called " the linear position relation between electrode surface ".The

electrode

12 and 13 of each buffer condenser 3 generally by one group of terminal form (as, among the present invention be three), see the plane graph of Fig. 3.As shown in Figure 3, the center that the electrode 12 of

buffer condenser

3 or 13 central representation should the group terminals.This structure guarantees that wide conductor is superimposed with each other in plane graph, thereby reduces following line inductance.

" parallel position relationship between wide conductor " next will be described.In Fig. 1 of display buffer circuit structure end view, arrange

wide conductor

14,15 and 16 like this, make them not form angle mutually, promptly in the relation of this position, does not spatially intersect with anode surface or the cathode plane of GTO 1 on

wide conductor

14,15 and 16 expansion plane.Here this position relation is called " parallel position relationship between wide conductor ".This structure can reduce following line inductance effectively.

Stipulate the width of wide conductor below.Especially, explanation to be wider than by the condition of narrow end in two electrode terminals that connect about the conductor that connects two electrode terminals at least.Electrode 12 situation just in time identical with 13 width of the anode (negative electrode) of the anode of all GTO 1 (negative electrode), buffering diode 2 and buffer condenser 3 is few.So, shown in Figure 2 as the top view of display buffer circuit structure, when describing above-mentioned condition, we suppose that the width of GTO 1, buffer condenser 3 and buffering diode 2 each self-electrode increases successively by this order.The width of wide conductor 14 that is used to connect GTO 1 fin 10 and buffering diode 2 anodes is at least greater than the electrode of buffering diode 2; And the width of wide conductor 15 of electrode 12 that is used to connect buffering diode 2 negative electrodes and buffering capacitor 3 is at least greater than the electrode of buffering diode 2; And the width of electrode 16 of wide conductor that is used to connect the electrode 13 of buffer condenser 3 and GTO1 fin 11 is at least greater than the electrode 13 of buffer condenser 3.

Wide conductor

14,15 and 16 shown in Figure 2 is to satisfy above-mentioned special case about wide conductor width regulation, and the lowest term about conductor width is called " regulation of wide conductor width " here.This structure has realized the even distribution of high-frequency current, thereby reduces following line inductance.

To further specify the regulation that intercouples about wide conductor now.More precisely, description is subjected to the coupling of mutual inductance influence between wide conductor 15 and the wide conductor 16, wherein wide conductor 15 is used to connect the negative electrode of buffering diode 2 and the electrode 12 of buffering capacitor 3, and wide conductor 16 is used to connect the electrode 13 of buffer condenser 3 and the negative electrode of GTO 1.Earlier with reference to " electrical engineering handbook (The Institution of Electrical Engineers) can be according to the mutual inductance M between two close circuit of equation (1) acquisition, and equation (1) is a neumann's formula.

Therefore, if two current values equate that mutually then mutual inductance M is inversely proportional to the interval r between circuit and the circuit, and is proportional to the cosine of the formed angle theta of current phasor.Can obtain line inductance L according to equation (2), the self-induction L of it and each circuit _SRelevant.

L=Ls+M……(2)

Because should be worth nonnegative value, so, mutual inductance M must be arranged to make mutual inductance M approach the value of self-induction Ls with the big as far as possible numerical value of negative sign, absolute value in order to make its minimum.In other words, need make the electric current in two circuits reverse mutually, that is, angle is 180 ° (cos θ=-1), and the interval between circuit and the circuit is as far as possible little.Here the position of the conductor that satisfies above-mentioned condition relation is called " regulation that mutual coupling is closed between wide conductor ".This structure can reduce line inductance.

To describe the embodiment shown in Fig. 1 and 2 emphatically below.Among Fig. 1,

wide conductor

14 and 16 is the relation between above-mentioned two circuits, and wide conductor 15 also is identical relation with 16.At first see the electric current in

wide conductor

14,15 and 16, when cutting off electric current when GTO 1 shutoff, cut electric current branches in the series circuit of being made up of buffering diode 2 and buffering capacitor 3.So according to Kirchhoff's law, obviously in whole wide conductor, the absolute value of electric current is the same.The formed angle theta of current phasor of the current phasor of

wide conductor

14,15 and wide conductor 16 is 180 °, sees Fig. 2.Because the electric current that flows through in the

wide conductor

14,15 and 16 during GTO 1 failure of current is a high-frequency current, thus can not exempt to be attended by skin effect with keeping away, thus electric current is flowed in wide conductor unevenly.As a result, the magnetic flux that magnetic flux that wide conductor 14 produces and wide conductor 16 produce is cancelled out each other, thereby causes the increase of absolute value and further the reducing of line inductance L of mutual inductance M.In order to prove this effect that reduces line inductance L, Fig. 5 with curve display the three dimensional analysis result of line inductance and the effective resistance that obtains by the intermediate groove width X that adopts in the naive model shown in Fig. 4 as parameter.By curve as seen, along with the increase of width X, inductance reduces.This expression is when comparing with 130 millimeters of length when placing wide conductor more close with about 5 millimeters) can cause and intercouple, and in dimension limit (210 millimeters), make width X maximum can reduce line inductance as far as possible.

Summary is got up, and the condition that " parallel position relationship between electrode surface " of GTO 1, buffering diode 2 and buffering capacitor 3 needs to satisfy is: can use the bending of needs Min. with the wide conductor as the electrode surface jockey; With the self-induction that can reduce jockey, thus the total inductance in the reduction buffer circuit.Simultaneously, " the linear position relation between electrode surface " of GTO 1, buffering diode 2 and buffering capacitor 3 condition of needing to satisfy be: make that the sense of current is almost 0 ° and 180 ° in the wide conductor; And can increase mutual inductance between the wide conductor, thereby reduce the total inductance in the buffer circuit.As for " parallel position relationship between wide conductor " be particularly related to " the wide conductor width regulation " that the width that uses wide conductor is greater than a narrower width in connected two electrodes, the condition that must satisfy is: high-frequency current is evenly flow through in wide conductive surface; With the total inductance that can reduce in the buffer circuit.Moreover about " regulation that intercouples between wide conductor " (the increasing the absolute value of mutual inductance so that increase the density that intercouples thereby be connected with reverse current in two conductors) that is used for two wide conductors are mounted closest, its condition is to reduce the total inductance of buffer circuit.In will satisfying buffer circuit that these primary conditions realize and structure that circuit for the thyristor shunting links to each other, can reduce the peak voltage V of generation as shown in figure 30 _DSPThereby, reduce turn-off power loss.

Said structure has further advantage, and the side-looking area of the circuit of being made up of thyristor, buffering diode, buffer condenser and wide conductor is compared with total sectional area, can be reduced.If other conditions are identical, then the inductance in the circuit is approximately proportional with the area around circuit, thereby reduces inductance with said structure.Embodiment 2:

To second embodiment of the present invention be described referring to accompanying drawing below.Fig. 6 has shown the structure that is combined as the formed buffer circuit of thyristor by the another kind according to first embodiment design philosophy.This figure comprises GTO 1, buffering diode 2, buffer condenser 3, be connected to the fin (or conductor) 10 of GTO 1 anode with Pressure Welding, be connected to the fin (or conductor) 11 of GTO 1 negative electrode with Pressure Welding, the

electrode

12 and 13 of buffer condenser 3, be used for being electrically connected the wide conductor 14 of the negative electrode of fin 11 (extension of GTO 1 negative electrode) and buffering diode 2, be used for being electrically connected the anode of buffering diode 2 and the wide conductor 15 of an electrode 12 of buffering capacitor 3, and be used for being electrically connected another electrode 13 of buffer condenser 3 and the wide conductor 16 of fin 10 (extension of GTO 1 anode).Can pass through, or obtain to cool off the function of buffering diode 2 by additional configurations such as suitable heat abstractors such as independent fin fin 11 and wide conductor 14 coadunations.

Among Fig. 6, the place different with Fig. 1 is the buffering diode 2 that is connected in parallel with GTO 1 and cushions the order that is connected of capacitor 3.More precisely, be to begin to be connected from its anode one side with being connected in parallel of GTO 1 among Fig. 1, and in Fig. 6, be to begin to be connected from its anode one side with buffer condenser 3 and the order that cushions diode with being connected in parallel of GTO 1 with the order of buffering diode 2 with buffering capacitor 3.Fig. 6 is the end view of buffer circuit structure, wherein with parallel position relationship all electrode surfaces is installed, and all wide conductors become parallel position relationship.Further shown in the plane graph of Fig. 7, all electrode surfaces are installed with the linear position relation.Also have two identical about among the regulation of the relation of intercoupling between wide conductor width and wide conductor and Fig. 1.So, obviously about reducing the effect of inductance, the buffer circuit structure of Fig. 6 and the structural equivalents among above-mentioned Fig. 1 in Fig. 1 buffer circuit.Embodiment 3:

To the 3rd embodiment of the present invention be described referring to accompanying drawing below.Fig. 8 has shown by the structure that according to first embodiment design philosophy is the buffer circuit of the formed another kind of combination of thyristor.This figure comprise GTO 1, buffering diode 2, buffer condenser 3, with Pressure Welding be connected to GTO 1 anode fin (or conductor) 10, be connected to the wide conductor 15 of an electrode 12 of the

electrode

12 and 13 of fin (or conductor) 11, the buffer condenser 3 of GTO 1 negative electrode, the wide conductor 14 that is used for being electrically connected the anode of fin 10 and buffering diode 2, the negative electrode that is used for being electrically connected buffering diode 2 and buffering capacitor 3 with Pressure Welding, and be used for being electrically connected another electrode 13 of buffer condenser 3 and the wide conductor 16 of fin 11.

Among Fig. 8, the places different with Fig. 1 are, the distance relation of buffering diode 2 and buffering capacitor 3 and GTO 1.More precisely, among Fig. 1 buffering diode 2 than buffer condenser 3 install more close GTO 1, and in Fig. 8 buffer condenser 3 than buffering diode 2 install more close GTO 1.Although omitted the top view of buffer circuit structure shown in Figure 8 here, obviously, the buffer circuit structure of Fig. 8 has adopted the technology of Fig. 1 about inductance in the reduction buffer circuit, thereby can suitably reduce the inductance in the buffer circuit.Embodiment 4:

Next referring to accompanying drawing four embodiment of the invention is described.Fig. 9 has shown by being combined as the formed buffer circuit structure of thyristor according to another of first embodiment design philosophy.This figure comprise GTO 1, buffering diode 2, buffer condenser 3, with Pressure Welding be connected to GTO 1 anode fin (or conductor) 10, be connected to the wide conductor 15 of an electrode 12 of the

electrode

12 and 13 of fin (or conductor) 11, the buffer condenser 3 of GTO 1 negative electrode, the wide conductor 14 that is used for being electrically connected the negative electrode of fin 11 and buffering diode 2, the anode that is used for being electrically connected buffering diode 2 and buffering capacitor 3 with Pressure Welding, and be used for being electrically connected another electrode 13 of buffer condenser 3 and the wide conductor 16 of fin 10.

Among Fig. 9, the place different with Fig. 6 is the distance relation of buffering diode 2 and buffering capacitor 3 to GTO 1.More precisely, among Fig. 6 buffering diode 2 than buffer condenser 3 install more close GTO 1, and in Fig. 9 buffer condenser 3 than buffering diode 2 install more close GTO 1.Although omitted the top view of the buffer circuit structure shown in Fig. 9 here, obviously the buffer circuit structure of Fig. 9 has adopted the technology of Fig. 6 about the inductance in the reduction buffer circuit, thereby suitably reduces the inductance in the buffer circuit.Embodiment 5:

Next referring to accompanying drawing the 5th embodiment of the present invention described.Figure 10 has shown that the design philosophy by partly improving first embodiment is the structure of the formed buffer circuit of thyristor.This figure comprise GTO 1, buffering diode 2, buffer condenser 3, with Pressure Welding be connected to GTO 1 anode fin (or conductor) 10, be connected to the wide conductor 15 of an electrode 12 of the

electrode

12 and 13 of fin (or conductor) 11, the buffer condenser 3 of GTO1 negative electrode, the wide conductor 14 that is used for being electrically connected the anode of fin 10 and buffering diode 2, the negative electrode that is used for being electrically connected buffering diode 2 and buffering capacitor 3 with Pressure Welding, and be used for being electrically connected another electrode 13 of buffer condenser 3 and the wide conductor 16 of fin 11.

Among Figure 10, the places different with Fig. 1 are that the electrode 12 of buffer condenser 3 does not become parallel position relationship to install with each electrode surface of GTO 1 and buffering diode 2 with 13 pole-face.More precisely, among Fig. 1 the

electrode

12 and 13 of buffer condenser 3 is arranged to have different mutually height and all electrodes is installed by parallel position relationship, and in Figure 10, the

electrode

12 and 13 of buffer condenser 3 has equal height and adopts L molded breadth conductor 15 and 16.Because this structure, the 5th embodiment of Figure 10 is more beneficial than the embodiment of earlier figures 1, and benefit has been to reduce the self-induction of wide conductor 15, thereby has reduced the total inductance in the buffer circuit.This advantage can derive from such design, i.e. many than in the wide conductor 16 of Figure 10 of wide conductor 15 that exists in the wide conductor 16 of Fig. 1 and 16 not parallel part.Although omitted the top view of the buffer circuit structure shown in Figure 10 here, obviously in the buffer circuit structure of Figure 10, obtained, in order to the effect that reduces total inductance in the buffer circuit obtained in than structure at Fig. 1 effective.Embodiment 6:

Referring to accompanying drawing the 6th embodiment of the present invention described below.Figure 11 has shown that the design philosophy by partly improving first embodiment is the structure of the formed buffer circuit of thyristor.This figure comprises GTO 1, buffering diode 2, buffer condenser 3, is connected to the fin (or conductor) 10 of GTO 1 anode with Pressure Welding, be connected to the wide conductor 15 of an electrode 12 of the

electrode

12 and 13 of fin (or conductor) 11, the buffer condenser 3 of GTO1 negative electrode, the wide conductor 14 that is used for being electrically connected the negative electrode of fin 11 and buffering diode 2, the anode that is used for being electrically connected buffering diode 2 and buffering capacitor 3 with Pressure Welding, and be used for being electrically connected another electrode 13 of buffer condenser 3 and the wide conductor 16 of fin 10.

Among Figure 11, the places different with Fig. 6 are that the electrode 12 of

buffer condenser

3 and 13 pole-face are not installed by parallel position relationship with each electrode surface of GTO 1 and buffering diode 2.More precisely, among Fig. 6 the

electrode

12 and 13 of buffer condenser 3 is arranged to have different mutually height and all electrodes is installed by parallel position relationship, and in Figure 11, the

electrode

12 and 13 of buffer condenser 3 has identical height and adopts L molded breadth conductor 15 and 16.Because this structure, the 6th embodiment of Figure 11 is more beneficial than the embodiment of earlier figures 6, and benefit has been to reduce the self-induction of wide conductor 16, thereby has reduced the total inductance in the buffer circuit.This advantage can derive from such design, i.e. many than in the wide conductor 16 of Figure 11 of wide conductor 15 that exists in the wide conductor 16 of Fig. 6 and 16 not parallel part.Although it is omitted the top view of the buffer circuit structure shown in Figure 11 here, that obviously obtained in the buffer circuit structure of Figure 11, more effective than what in the structure of Fig. 6, obtained in order to the effect that reduces total inductance in the buffer circuit.Embodiment 7:

Next will the 7th embodiment of the present invention be described referring to accompanying drawing.Figure 12 has shown that the design philosophy by partly improving first embodiment is the structure of the formed buffer circuit of thyristor.This figure comprises GTO 1, buffering diode 2, buffer condenser 3, is connected to the fin (or conductor) 10 of GTO 1 anode with Pressure Welding, be connected to the wide conductor 15 of an electrode 12 of the

electrode

Among Figure 12, the places different with Fig. 2 are that the electrode surface of GTO 1 does not concern by linear position with each electrode surface that cushions capacitor 3 with buffering diode 2 to be installed.More precisely, Fig. 2 cathetus AB, BC and DA are placed in a straight line, and Figure 12 cathetus AB and AD not with straight line BC in a straight line.Yet if the end view of the buffer circuit structure shown in Figure 12 and Fig. 1's is identical, all electrode surfaces become parallel position relationship, and all wide conductors also become parallel position relationship.And as shown in figure 12, satisfy regulation about wide conductor width.Obviously, except all electrode surfaces are misaligned each other, that obtained in the buffer circuit structure of Figure 12, identical with the effect that obtained in the structure of Fig. 2 substantially in order to the effect that reduces total inductance in the buffer circuit.Embodiment 8:

Next referring to accompanying drawing the eighth embodiment of the present invention is described.Figure 13 has shown that improving first embodiment design philosophy by part is the formed buffer circuit structure of thyristor.This figure comprises GTO 1, buffering diode 2, with Pressure Welding be connected to GTO 1 anode fin (or conductor) 10, be connected to the wide conductor 15 of an electrode 12 of the

electrode

12 and 13 of fin (or conductor) 11, buffer condenser 3 (not shown) of GTO 1 negative electrode, the wide conductor 14 that is used for being electrically connected the anode of fin 10 and buffering diode 2, the negative electrode that is used for being electrically connected buffering diode 2 and buffering capacitor 3 with Pressure Welding, and be used for being electrically connected another electrode 13 of buffer condenser 3 and the wide conductor 16 of fin 11.

Among Figure 13, with Fig. 2 different place be that the electrode surface of GTO 1 does not concern by linear position with buffering diode 2 and buffering capacitor 3 to be installed.More precisely, Fig. 2 cathetus AB, BC and DA are placed in a straight line, and Figure 13 cathetus AB and AD not with straight line BC in a straight line.Yet if the end view of the buffer circuit structure shown in Figure 13 and Fig. 1's is identical, all electrode surfaces become parallel position relationship, and all wide conductors also become parallel position relationship.And as shown in figure 13, satisfy regulation about wide conductor width.About the width of wide conductor, to compare present embodiment with Figure 12 and have more strong point, reason is, is positioned at wide conductor 14 by the electrode of GTO 1 to the tangent line P1 and the P2 of the electrode of buffering diode 2; By the electrode of buffering diode 2 tangent line Q to an electrode 12 of buffer condenser 3 ₁And Q ₂Be positioned at wide conductor 16, and by the tangent line R1 of the electrode of another electrode 13 to GTO 1 of buffer condenser 3 and R2 also in wide conductor 16, thereby can prevent that electric field from concentrating, if not, GTO 1 branches to high-frequency electrical in the buffer circuit and fails to be convened for lack of a quorum and cause that electric field concentrates when turn-offing.Among Figure 12, electric field is concentrated the junction that especially can occur in fin 10 and wide conductor 14.When this electric field of generation is concentrated, can produce the problems such as temperature rising that some comprise knot among localized heat loss and the GTO 1, thereby make component wear.Therefore, except all electrodes are out-of-line, obviously in the buffer circuit structure of Figure 13, can fully obtain substantially effect structural similarity, that can reduce total inductance in the buffer circuit with Fig. 2, and can suitably make the rising homogenizing of the temperature that produces in the wide conductor.In fact, be used for avoiding that electric field is concentrated, also be applicable to any other embodiment about the design philosophy of wide conductor width.Although wide conductor 14,15 and 16 used among Figure 13 is a rectangle in its top view, with regard to wide conductor 14, it can have different shapes, the shape that is cut into along tangent line P1 for example, thus can save the production cost of wide conductor.

In addition, about reducing inductance, each center of electrode does not need mutually just in time on same straight line, and the narrower condition that is included among of broad in the top view in two wide conductors that are superimposed with each other in its top view must satisfy.Embodiment 9:

To the 9th embodiment of the present invention be described referring to accompanying drawing below.Figure 14 has shown by the design philosophy of using first embodiment to be the structure of a plurality of formed buffer circuits of thyristor that are connected in series.This figure comprises

GTO

1A and 1B,

buffering diode

2A and 2B and buffer condenser 3A and 3B.Note GTO 1A, shown among the figure with Pressure Welding be connected to GTO 1A anode fin (or conductor) 10A, be connected to the wide conductor 15A of the electrode 12A of electrode 12A and the 13A of fin (or conductor) 11A, the buffer condenser 3A of GTO 1 negative electrode, the wide conductor 14A that is used for being electrically connected the anode of fin 10A and buffering diode 2A, the negative electrode that is used for being electrically connected buffering diode 2A and buffering capacitor 3A with Pressure Welding, and be used for being electrically connected another electrode 13A of buffer condenser 3A and the wide conductor 16A of fin 11A.Can be by assemble wide conductor 14A or the additional function that obtains to cool off buffering diode 2A such as suitable heat abstractors such as independent fin that is equipped with for fin 10A.Because the structure of GTO 1B is identical with GTO 1A's, so no longer be repeated in this description here.

Figure 14 is the exemplary that adopts Fig. 1 structure, and GTO 1A that a plurality of series connection rise and the anode of 1B and negative electrode do not add any modification.Therefore, obviously, the effect that reduces total inductance in the buffer circuit is equivalent to the effect that obtains among Fig. 1.Can connect with four kinds of methods shown in Figure 15 A to 15D and be connected in parallel in the buffer circuit on the series connection GTO more than two.Except the Figure 14 that specifically illustrates Figure 15 A structure, obviously can design the end view of some other structure, for example, the end view of the combination of available Fig. 1 and Fig. 6 or the relevant Figure 15 B of Combination Design of Figure 10 and Figure 11.In addition, also can realize Figure 15 C and 15D by the appropriate combination previous embodiment.

Although present embodiment has the typical structure that a plurality of thyristors are connected in series mutually, the present invention is equally applicable to the structure that another kind of element connection in series-parallel connects.More precisely, can form series parallel structure like this, the axial symmetry that is about to Figure 14 adds to the right-hand member of

GTO

1A and 1B among Figure 14, then the terminal of

GTO

1A and 1B is coupled together with the GTO terminal of interpolation like this respectively.Embodiment 10:

Next referring to accompanying drawing the of the present invention ten embodiment described.Figure 16 and 17 has shown that the design philosophy by partly improving first embodiment is the structure of the formed buffer circuit of thyristor.Figure 16 is a plane graph, and Figure 17 is an end view, has wherein omitted buffer condenser and connected mode thereof for convenience of explanation.The places different with Figure 14 are, from plane graph, the center B1 of buffering diode 2A and 2B and B2 be not in identical position.Yet, as shown in figure 16, all electrode surfaces become parallel position relationship, and wide conductor also becomes parallel position relationship, buffering diode 2A is positioned on the center line SS of relevant GTO 1A with buffering capacitor 3A (not shown) in addition, simultaneously buffering diode 2B and buffering capacitor 3B (not shown) be positioned at relevant GTO 1B, and the angled center line TT of center line SS on.In this case, the end view of the buffer circuit structure of seeing from direction 1 and 2 is same as in figure 1 at last.Therefore obviously, be similar to Fig. 1, can obtain to reduce the function of total inductance in each buffer circuit.Though Figure 16 has shown that by two center line SS and the formed interior angle of TT be the typical case at right angle, interior angle needn't one be decided to be the right angle, and does not have special restriction.Embodiment 11:

Next referring to accompanying drawing the 11 embodiment of the present invention described.Figure 18 has shown a power converter, it comprises the positive and negative bus P and

thyristor

1A, 1B, 1C and the 1D between the N (for example GTO) that are connected in series in the DC power supply 17 with intermediate potential point C, reverse parallel connection is connected in the clamping diode 19B between the clamping diode 19A between

current regulator diode

18A, 18B, 18C and the 18D on the semiconductor element, the contact that is connected

GTO

1A and 1B and the intermediate potential point C, the contact that is connected GTO 1C and 1D and the intermediate potential point C respectively, and is contained in the output on the contact of GTO 1B and 1C.This power converter exports three kinds of voltage levels the three level adverse current devices of output O to as on-off action that can be by GTO 1A to 1D, that is, and and the positive and negative bus P of DC power supply 17 and voltage on the N and the voltage on the intermediate potential point C.Because other are any directly not relevant with the present invention such as add ons such as anode reactor, buffer resistance device and buffering energy regeneration circuit, thus among the figure with its omission.

Below will describe the connection of buffer circuit, they are used for suppressing any precipitous voltage build-up rate that is produced when each GTO that forms this three-level inverter cuts off electric current.The buffer condenser 3C that the buffer circuit structure that this three-level inverter adopted comprises buffer circuit that the buffering diode 2B that links to each other by the buffer circuit of forming with the buffer condenser 3A of GTO 1A parallel connection and buffering diode 2A, by the anode with the anode of clamping diode 19A and current regulator diode 18C and buffering capacitor 3B form, linked to each other by the negative electrode with the negative electrode of current regulator diode 18B and clamping diode 19B and cushion the buffer circuit that diode 2C forms, and by the buffer condenser 3D in parallel with GTO 1D with cushion the buffer circuit that diode 2D forms.For example, about GTO 1A, shown in Figure 19 A, when GTO 1A cut off electric current (a), then electric current was split into electric current (b), thereby the charging effect of buffer condenser 3A can suppress the voltage build-up rate of relevant GTO 1A in the buffer circuit.For GTO1D, also can obtain identical effect.Simultaneously, about GTO 1B, shown in Figure 19 B, when GTO 1B cut off electric current (a), electric current was split into electric current (b), thereby the charging effect of buffer condenser 3B can suppress the voltage build-up rate of relevant GTO 1B in the buffer circuit.Also can obtain identical effect for GTO 1C.

Need not to revise,, just can form the buffer circuit about GTO 1A and 1D shown in Figure 180 by using the buffer circuit structure among above-mentioned any embodiment.But, about the buffer circuit of GTO1B and 1C, because Figure 19 A is different with the effect of the failure of current shown in the 19B, so obviously the foregoing description directly is not suitable for.

Now, specify the structure of the buffer circuit that can reduce inductance of relevant GTO 1B and 1C referring to accompanying drawing.At first, Figure 20 is the end view that shows about the buffer circuit structure of GTO 1B.This figure comprises GTO 1B, buffering diode 2B, buffer condenser 3B, be connected to fin (or conductor) 10B of GTO 1B anode with Pressure Welding, fin (or conductor) 11B that is connected to GTO 1B negative electrode and links to each other with Pressure Welding with output O, be clamping diode 19A fin (or conductor) 20B that be equipped with and that link to each other with intermediate potential point C, fin (or conductor) 21B for current regulator diode 18C outfit, electrode 12B and the 13B of buffer condenser 3B, be used for being electrically connected the wide conductor 14B of fin 20B and the anode of buffering diode 2B, be used for being electrically connected the negative electrode of buffering diode 2B and the wide conductor 15B of the electrode 12B of buffering capacitor 3B, and be used for being electrically connected another electrode 13B of buffer condenser 3B and the wide conductor 16B of fin 21B.Can be by assemble wide conductor 14B or the additional function that obtains to cool off buffering diode 2B such as suitable heat abstractors such as independent fin that is equipped with for fin 20B.

Among Figure 20, all electrode surfaces become parallel position relationship and linear position relation.But also the regulation of satisfied relevant wide conductor width.As for the clamping diode 19A and the current regulator diode 18C that add in Fig. 1 structure, electric current in flowing into clamping diode 19A and buffering diode 2B, perhaps flow under the opposite polarity each other situation of electric current of dash area of current regulator diode 18C and wide conductor 15B, think that these diodes intercouple.In addition, though

wide conductor

15B and 16B have part not satisfy parallel position relationship, major part is keeping parallelism position relation still.Therefore, still the design philosophy of first embodiment can be applied to present embodiment, thereby be similar to first embodiment, can obtain to reduce the effect of total inductance in the buffer circuit.

Figure 21 is the end view that shows about the buffer circuit structure of GTO 1C.This figure comprises GTO 1C, buffering diode 2C, buffer condenser 3C, be connected to fin (or conductor) 10C of GTO1C anode with Pressure Welding, the fin 11C that is connected to GTO 1C negative electrode and links to each other with Pressure Welding with output O, be equipped with and fin (or conductor) 20C that link to each other with intermediate potential point C for clamping diode 19B, fin (or conductor) 21C for current regulator diode 18B outfit, electrode 12C and the 13C of buffer condenser 3C, be used for being electrically connected the wide conductor 14C of fin 20C and the negative electrode of buffering diode 2C, be used for being electrically connected the anode of buffering diode 2C and the wide conductor 15C of the electrode 12C of buffering capacitor 3C, and be used for being electrically connected another electrode 13C of buffer condenser 3C and the wide conductor 16C of fin 21C.Can be by assemble wide conductor 14C for fin 20C, the perhaps additional function that obtains to cool off buffering diode 2C such as suitable heat abstractors such as independent fin that is equipped with.

Be similar to Figure 20, all electrode surfaces become parallel position relationship and linear position relation among Figure 21.But also the regulation of satisfied relevant wide conductor width.As for the clamping diode 19B and the current regulator diode 18B that add in Fig. 1 structure, at the electric current that flows into clamping diode 19B and buffering diode 2C, perhaps flow under the opposite polarity each other situation of electric current of dash area of current regulator diode 18B and wide conductor 15C, think that these diodes intercouple.In addition, though

wide conductor

15C and 16C have part not satisfy parallel position relationship, major part is keeping parallelism position relation still.Therefore, the design philosophy of first embodiment still can be applied to present embodiment, thereby is similar to first embodiment, can obtain to reduce the effect of total inductance in the buffer circuit.

Naturally, by above-mentioned other embodiment is applied in the buffer circuit of relevant GTO 1B and 1C, can reduce the inductance in the buffer circuit.For example, buffer condenser shown in Figure 10 is applicable to the buffer condenser 3B among Figure 20 naturally.Embodiment 12:

Next referring to accompanying drawing the 12 embodiment of the present invention described.Figure 22 has shown a power converter, it (for example comprises the positive and negative bus P that is connected in series in the DC power supply 17 with intermediate potential point C and

thyristor

1A, 1B, 1C and 1D between the N, GTO), reverse parallel connection is connected in the clamping diode 19B between the clamping diode 19A between

current regulator diode

GTO

1A and 1B and the intermediate potential point C, the contact that is connected GTO 1C and 1D and the intermediate potential point C respectively, and be provided at output O on the contact of GTO 1B and 1C.This power converter exports three kinds of voltage levels to the three-level inverter of output O, the i.e. positive and negative bus P of DC power supply 17 and voltage on the N and the voltage on the intermediate potential point C as on-off action that can be by GTO 1A to 1D.Because other are any directly not related to the present invention such as add ons such as anode reactor, buffer resistance device and buffering energy regeneration circuit, thus among the figure with its omission.

The connection of buffer circuit is described below, and they are used for suppressing any precipitous voltage build-up rate that is produced when each GTO that forms this three-level inverter cuts off electric current.The buffering diode 2C that the buffer circuit structure that this three-level inverter adopted comprises buffer circuit that the buffer condenser 3B that links to each other by the buffer circuit of forming with the buffer condenser 3A of GTO 1A parallel connection and buffering diode 2A, by the negative electrode with the anode of clamping diode 19A and GTO 1B and buffering diode 2B form, linked to each other by the negative electrode with the anode of GTO 1C and clamping diode 19B and cushion the buffer circuit that capacitor 3C forms, and the buffering diode 2D in parallel and cushion the buffer circuit of capacitor 3D composition with GTO1D.For example, about GTO 1A, shown in Figure 23 A, when GTO 1A cut off electric current (a), electric current was split into electric current (b), thereby the charging effect of buffer condenser 3A can suppress the voltage build-up rate of relevant GTO 1A in the buffer circuit.For GTO) 1D, also can obtain identical effect.Simultaneously, about GTO 1B, shown in Figure 23 B, when GTO 1B cut off electric current (a), electric current was split into electric current (b), thereby the charging effect of buffer condenser 3B can suppress the voltage build-up rate of relevant GTO 1B in the buffer circuit.For GTO 1C, also can obtain identical effect.

Need not to revise,, just can form the buffer circuit shown in Figure 22 about GTO 1A and 1D by using the buffer circuit structure among above-mentioned any embodiment.But, about the buffer circuit of GTO 1B and 1C, because Figure 23 A is different with the effect of the failure of current shown in the 23B, so obviously the foregoing description directly is not suitable for.

Now, specify the structure of the buffer circuit that can reduce inductance of relevant GTO 1B and 1C referring to accompanying drawing.At first, Figure 24 is the end view that shows about the buffer circuit structure of GTO 1B.This figure comprise GTO 1B, buffering diode 2B, buffer condenser 3B, with Pressure Welding be connected to GTO 1B anode fin (or conductor) 10B, with Pressure Welding be connected to the negative electrode of GTO 1B and fin (or conductor) 11B that links to each other with output O, be equipped with for clamping diode 19A and fin (or conductor) 20B that links to each other with intermediate potential point C, electrode 12B and the 13B of buffer condenser 3B.Be used for being electrically connected the wide conductor 15B of the electrode 12B of the wide conductor 14B of the negative electrode of fin 11B and buffering diode 2B, the anode that is used for being electrically connected buffering diode 2B and buffering capacitor 3B, and be used for being electrically connected another electrode 13B of buffer condenser 3B and the wide conductor 16B of fin 20B.Can be by assemble wide conductor 14B for fin 11B, the perhaps additional function that obtains to cool off buffering diode 2B such as suitable heat abstractors such as independent fin that is equipped with.

Among Figure 24, all electrode surfaces become parallel position relationship and linear position relation.But also the regulation of satisfied relevant wide conductor width.As for the clamping diode 19A that adds in Fig. 1 structure, under the opposite polarity each other situation of electric current in the dash area that flows into clamping diode 19A and wide conductor 15B, think the relation of intercoupling that keeps.In addition, though

wide conductor

Figure 25 is the end view that shows about the buffer circuit structure of GTO 1C.This figure comprises GTO 1C, buffering diode 2C, buffer condenser 3C, fin (or conductor) 10C that is connected to the anode of GTO1C and links to each other with Pressure Welding with output O, be connected to fin (or conductor) 11C of GTO 1C negative electrode with Pressure Welding, be equipped with and fin (or conductor) 20C that link to each other with intermediate potential point C for clamping diode 19B, electrode 12C and the 13C of buffer condenser 3C, be used for being electrically connected the wide conductor 14C of fin 10C and the anode of buffering diode 2C, be used for being electrically connected the negative electrode of buffering diode 2C and the wide conductor 15C of the electrode 12C of buffering capacitor 3C, and be used for being electrically connected another electrode 13C of buffer condenser 3C and the wide conductor 16C of fin 20C.Can be by assemble wide conductor 14C for fin 10C, the perhaps additional function that obtains to cool off buffering diode 2C such as suitable heat abstractors such as independent fin that is equipped with.

Be similar to Figure 24, all electrode surfaces become parallel position relationship and linear position relation among Figure 25.But also the regulation of satisfied relevant wide conductor width.As for the clamping diode 19B that adds in Fig. 1 structure, under the opposite polarity each other situation of electric current of the dash area that flows into clamping diode 19B and wide conductor 15C, think the relation of intercoupling that keeps.In addition, though

wide conductor

15C and 16C have part not satisfy parallel position relationship, major part is keeping parallelism position relation still.Therefore, still the design philosophy of first embodiment can be applied to present embodiment, thereby be similar to first embodiment, can obtain to reduce the effect of total inductance in the buffer circuit.

Naturally, by above-mentioned other embodiment are applied in the buffer circuit of relevant GTO 1B and 1C, can reduce the inductance in the buffer circuit.For example, buffer condenser shown in Figure 10 is applicable to the buffer condenser 3C among Figure 25 naturally.Embodiment 13:

Next referring to accompanying drawing the 13 embodiment of the present invention described.Figure 26 and 27 has shown that the design philosophy by partly improving first embodiment is the structure of the formed buffer circuit of thyristor.This figure comprise GTO 1, buffering diode 2, buffer condenser 3, with Pressure Welding be connected to GTO 1 anode fin (or conductor) 10, be connected to the wide conductor 15 of an electrode 12 of the

electrode

12 and 13 of fin (or conductor) 11, the buffer condenser 3 of GTO 1 negative electrode, the wide conductor 14 that is used for being electrically connected the anode of fin 11 and buffering diode 2, the negative electrode that is used for being electrically connected buffering diode 2 and buffering capacitor 3 with Pressure Welding, and be used for being electrically connected another electrode 13 of buffer condenser 3 and the wide conductor 16 of fin 11.

The places different with Fig. 1 are, the interelectrode space of GTO 1 is more much bigger than the space sum between the

electrode

12 and 13 of the interelectrode space of buffering diode 2 and buffering capacitor 3.In this case, in order to reduce the inductance of buffer circuit, can obtain benefit by the structure that forms Figure 26 and 27.In this structure, install all electrode surfaces to such an extent that have linear position relation, and satisfy the regulation of relevant wide conductor width, make in addition wide conductor to 15 and 16 and wide conductor to 14 and 16 mutually near to keep the relation of intercoupling.Embodiment 14:

Referring to accompanying drawing the 14 embodiment of the present invention described below.Figure 28 has shown that the design philosophy by partly improving first embodiment is the structure of the formed buffer circuit of thyristor.This figure comprise GTO 1, buffer condenser 2, buffer condenser 3, with Pressure Welding be connected to GTO 1 and buffering diode 2 fin (or conductor) 10, be connected to the wide conductor 15 of an electrode 12 of the

electrode

12 and 13 of fin (or conductor) 11, the buffer condenser 3 of GTO 1 negative electrode, the negative electrode that is used for being electrically connected buffering diode 2 and buffering capacitor 3 with Pressure Welding, and be used for being electrically connected another electrode 13 of buffer condenser 3 and the wide conductor 16 of fin 11.

The places different with Fig. 1 are that GTO 1 is installed in the identical pressure Welding Structure with buffering diode 2.In the figure of any expression previous embodiment, be configured under the following prerequisite and carry out, be the diameter of the diameter of GTO 1 electrode surface greater than buffering diode 2, if thereby GTO 1 is installed in the identical pressure Welding Structure with buffering diode 2 boths, then each electrode surface each other can not average contact.More precisely, precondition is to be installed in GTO 1 in the different pressure Welding Structures with buffering diode 2.But, as shown in figure 28, when each electrode surface of GTO 1 and buffering diode 2 has the appropriate diameter that allows to be installed in the identical pressure Welding Structure, then the formation of Figure 28 structure can help reducing the inductance in the buffer circuit, wherein all electrode surfaces are installed to such an extent that have a linear position relation, and the regulation of satisfied relevant wide conductor width, make wide conductor close mutually to keep the relation of intercoupling in addition to 15 and 16.Embodiment 15:

In fact, be used for describing among the figure of previous embodiment, must provide, thereby guarantee that heat conduction is satisfactory and obtain the even temperature distribution with the additional pressure welder that thyristor, diode and fin are welded to each other of pressure any.Though,, in actual use, still need add these insulators of outfit so omitted some insulators for guaranteeing that distance is inserted between required clearance for insulation or edge because insulator depends on the voltage that adds to thyristor.For example, among Fig. 1,, then be equivalent to the direct capacitance of rising buffer condenser if specially that dielectric constant is high dielectric is inserted between

wide conductor

15 and 16 as insulator, voltage build-up rate when the result reduces the thyristor failure of current, thus the loss of this semiconductor element reduced.

Claims

1. power converter, it has the semiconductor switch element; One buffer circuit that is connected between the electrode of described thyristor and forms by a buffering diode and a buffer condenser of mutual series connection; And a plurality of using described thyristor, described buffering diode and the wide conductor of the interconnective band shape of described buffer condenser;

It is characterized in that, with parallel position relationship anode surface and cathode plane, the anode surface of described buffering diode and two electrode surfaces of cathode plane and described buffer condenser of all described thyristors are installed, and all described wide conductors are installed with parallel position relationship.

2. power converter according to claim 1, it is characterized in that, negative and positive pole-face, the negative and positive pole-face of described buffering diode and the center separately of described buffer condenser two electrode surfaces of described thyristor so are installed, they are positioned on the straight line in the plane graph of described power converter.

3. power converter according to claim 1 and 2 is characterized in that, the width of described wide conductor is greater than passing through the narrowest one width in the interconnective described electrode surface of described conductor.

4. according to any one described power converter in claim 1 or 2, it is characterized in that, two described wide conductors that are superimposed with each other shown in the plane graph of the described power converter of installation like this, narrower conductor is included in the conductor of broad when seeing from described plane graph with box lunch.

5. according to any one described power converter in claim 1 or 2, it is characterized in that, install two adjacent described wide conductors that are connected with current in opposite close mutually, so that make its inductance coupling high.

6. power converter, it has the semiconductor switch element; One buffer circuit that is connected between the described thyristor electrode and forms by a buffering diode and a buffer condenser of mutual series connection; And a plurality ofly be used for making described thyristor, described buffering diode and the wide conductor of the interconnective band shape of described buffer condenser;

It is characterized in that two adjacent described wide conductors that are connected with current in opposite have described wide conductor close parallel portion mutually, thereby make its inductance coupling high.

7. power converter, it has the semiconductor switch element; One buffer circuit that is connected between the described thyristor electrode and forms by a buffering diode and a buffer condenser of mutual series connection; And a plurality ofly be used for making the interconnective wide conductor of described thyristor, described buffering diode and described buffer condenser;

It is characterized in that, so form the circuit of forming by described thyristor, described buffering diode, described buffer condenser and described wide conductor, make circuit surrounded in the end view area less than total sectional area.

8. according to any one described power converter in the claim 1,6 or 7, it is characterized in that, the wide conductor that parallel installation links to each other with two electrodes of described buffer condenser also makes it mutually near a pair of to form, and described wide conductor between insert dielectric.

9. an electric power variable flow device that comprises a plurality of as claim 1,6 or 7 described power converters is characterized in that each thyristor is connected in series mutually.

10. an electric power variable flow device that comprises a plurality of as claim 1,6 or 7 described power converters is characterized in that, the mutual connection in series-parallel of each thyristor connects.

11. a three-level inverter is characterized in that, it comprises a kind of combination as claim 1,6 or 7 described power converters.

12. the buffer circuit that a method of making power converter, described power converter comprise that semiconductor switch element, is connected between the described thyristor electrode and be made up of a buffering diode and a buffer condenser of mutual series connection and a plurality ofly be used for making described thyristor, described buffering diode and the wide conductor of the interconnective band shape of described buffer condenser; Described method is characterised in that it comprises following step:

Described thyristor, described buffering diode and described buffer condenser are installed by this way, are made the placement that is parallel to each other of its all electrode surfaces; And

With a plurality of wide conductors that are parallel to each other the electrode of described thyristor, described buffering diode and described buffer condenser is interconnected.