CN104735913B - The preparation method of package substrate via - Google Patents

The preparation method of package substrate via Download PDF

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Publication number
CN104735913B
CN104735913B CN201510126595.XA CN201510126595A CN104735913B CN 104735913 B CN104735913 B CN 104735913B CN 201510126595 A CN201510126595 A CN 201510126595A CN 104735913 B CN104735913 B CN 104735913B
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China
Prior art keywords
ring
copper
6mil
diameter
adjacent conductor
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CN201510126595.XA
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Chinese (zh)
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CN104735913A (en
Inventor
宋阳
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN201510126595.XA priority Critical patent/CN104735913B/en
Publication of CN104735913A publication Critical patent/CN104735913A/en
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047—Drilling of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0214—Back-up or entry material, e.g. for mechanical drilling

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention relates to a kind of preparation method of package substrate via, it is characterized in that, comprise the following steps that：（1）Via is optimized：A, a diameter of 0.1mm via compensated to 0.15mm；B, 0.15mm via optimized by 0.15mm via+6mil ring widthes, i.e., the ring width of copper ring is 6mil；While via and ring width size meet 0.15mm+6mil, it is ensured that minimum spacing of the copper ring away from adjacent conductor is 3mil, the distance for crossing pitch-row adjacent conductor is more than 7mil；C, minimum spacing of the copper ring away from adjacent conductor is being met for 3mil, under conditions of the distance for crossing pitch-row adjacent conductor is more than 7mil, via and porose disc are optimized for 0.15mm via+8mil ring widthes；D, the via of 0.15mm via+8mil ring widthes is adjusted to a diameter of 0.2mm；（2）A diameter of 0.15mm via is bored using 0.15mm drill bit on drilling machine, a diameter of 0.2mm via is bored using 0.2mm drill bit；（3）Copper facing behind drill-through hole.The present invention can improve the efficiency and quality of Drilling operation, greatly reduce the processing cost of drilling.

Description

The preparation method of package substrate via
Technical field
The present invention relates to a kind of preparation method of package substrate via, belong to microelectronic packaging technology field.
Background technology
The design of present substrate is more and more intensive, also can be more and more using the plate of 0.1mm Via Designs.And small size mistake Hole can bring many technology problems in techniques such as progress machine drilling, plating, and the problem of processing cost.
At a high speed, highdensity wiring board design when, it is the smaller the better that designer always wants to via, can be with such plank Leave more wiring spaces；In addition, via is smaller, the parasitic capacitance of its own is also smaller, is particularly suited for high speed circuit.But The reduction of via size brings the increase of cost simultaneously, and the size of via unconfined can not possibly reduce, and it is bored The limitation of the technology such as hole and plating, via is smaller, and Drilling operation technique is more difficult to, it is necessary to the time spent is longer, is also more held Easy off-center position, via is smaller, and the radius-thickness ratio of wiring board is bigger, in follow-up electroplating technology, it is impossible to ensure that hole wall is plated The uniformity of copper.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art there is provided a kind of making side of package substrate via Method, improves the efficiency and quality of Drilling operation, greatly reduces the processing cost of drilling, improve wiring board following process Processing quality, while improving the reliability of wiring board.
The technical scheme provided according to the present invention, the preparation method of the package substrate via, it is characterized in that, including it is following Processing step：
（1）The via of package substrate is optimized：
A, in substrate design domain via carry out entire compensation：By a diameter of 0.1mm via pre-compensation extremely 0.15mm；
B, to after compensation via carry out porose disc optimization：0.15mm via is carried out by 0.15mm via+6mil ring widthes Optimization, the i.e. ring width of copper ring are 6mil, and the ring width of signified copper ring refers to the width sum of copper ring same diametrically both sides herein； While via and ring width size meet 0.15mm+6mil, minimum spacing of the copper ring away from adjacent conductor is met for 3mil, it is ensured that The distance for crossing pitch-row adjacent conductor is more than 7mil；
C, to porose disc optimize after via carry out double optimization：It is meeting minimum spacing of the copper ring away from adjacent conductor 3mil, crosses the distance of pitch-row adjacent conductor under conditions of more than 7mil, via and porose disc are optimized for into 0.15mm vias+8mil Ring width；
D, the via of 0.15mm via+8mil ring widthes is adjusted to a diameter of 0.2mm；
（2）Make via：A diameter of 0.15mm via is bored using 0.15mm drill bit on drilling machine, using 0.2mm Drill bit bore a diameter of 0.2mm via；
（3）Copper facing is carried out behind drill-through hole, crossing after hole plating copper for 0.15mm crosses hole surface copper ring ring width for 6mil, 0.2mm's It is 6mil to cross after hole plating copper and cross hole surface copper ring ring width.
The present invention has advantages below：（1）The present invention reduces adding for drilling by the selective Optimization Compensation to via Work cost, improves drilling quality, drilling efficiency.（2）The present invention improves the machinability of the subsequent manufacturing processes of wiring board And reliability（For example：The techniques such as plating, consent）, and improve the processing efficiency and quality of wiring board；To whole wiring board Subsequent machining technology problem bring advantage.（3）The present invention does not need new equipment and technique just to realize the system of wiring board It is standby, it is adapted to popularization and the scale of mass production of the technology assist side volume production manufacturer.
Brief description of the drawings
Fig. 1 was the schematic diagram of hole surface copper ring.
Embodiment
With reference to specific drawings and examples, the invention will be further described.
The preparation method of the package substrate via, is comprised the following steps that：
（1）The via of package substrate is optimized using INCAM softwares：
A, in substrate design domain via carry out entire compensation：By a diameter of 0.1mm via pre-compensation extremely 0.15mm；
B, to after compensation via carry out porose disc（Behind drill-through hole, copper facing is carried out to via, the copper ring for crossing hole surface is hole Disk）Optimization：0.15mm via is optimized by 0.15mm via+6mil ring widthes, i.e., the ring width of copper ring is 6mil, this place The ring width for referring to copper ring refers to the width sum of copper ring same diametrically both sides, as shown in figure 1, ring width is x1And x2Sum；In mistake While hole and ring width size meet 0.15mm+6mil, minimum spacing of the copper ring away from adjacent conductor is met for 3mil, it is ensured that via Distance away from adjacent conductor is more than 7mil, as shown in figure 1, A is conductor；
C, to porose disc optimize after via carry out double optimization：It is meeting minimum spacing of the copper ring away from adjacent conductor 3mil, crosses the distance of pitch-row adjacent conductor under conditions of more than 7mil, via and porose disc are optimized for into 0.15mm vias+8mil Ring width；
D, the via of 0.15mm via+8mil ring widthes is adjusted to a diameter of 0.2mm；
（2）Make via：A diameter of 0.15mm via is bored using 0.15mm drill bit on drilling machine, using 0.2mm Drill bit bore a diameter of 0.2mm via；
（3）Copper facing is carried out behind drill-through hole, crossing after hole plating copper for 0.15mm crosses hole surface copper ring ring width for 6mil, 0.2mm's It is 6mil to cross after hole plating copper and cross hole surface copper ring ring width.
Assist side of the present invention carries out selective Optimization Compensation before being drilled according to the design conditions of via, optimizes The size in hole, improves the crudy and efficiency of drilling, solves the drilling quality brought because bore size is small and drilling off normal Technical problem, while the aperture by optimizing via, the radius-thickness ratio of reduction wiring board in itself is improved due to via size It is small, the technical problem such as copper facing uniformity brought in follow-up electroplating technique.The design of selectivity Optimization Compensation via of the invention Structure can reduce the processing cost of production with processing technology（The cost of 0.2mm drill bits will be far smaller than 0.15mm drill bit）, carry The reliability of elevated track plate and good electric property；It has been pushed further into the technological industrialization.

Claims (1)

1. a kind of preparation method of package substrate via, it is characterized in that, comprise the following steps that：
（1）The via of package substrate is optimized：
A, in substrate design domain via carry out entire compensation：By a diameter of 0.1mm via pre-compensation to 0.15mm；
B, to after compensation via carry out porose disc optimization, the porose disc was the copper ring of hole surface：0.15mm via is pressed 0.15mm via+6mil ring widthes are optimized, i.e., the ring width of copper ring is 6mil, and the ring width of signified copper ring refers to that copper ring is same herein The width sum of bar diametrically both sides；While via and ring width size meet 0.15mm+6mil, meet copper ring and led away from adjacent The minimum spacing of body is 3mil, it is ensured that the distance for crossing pitch-row adjacent conductor is more than 7mil；
C, to porose disc optimize after via carry out double optimization：Minimum spacing of the copper ring away from adjacent conductor is being met for 3mil, mistake The distance of pitch-row adjacent conductor be more than 7mil under conditions of, via and porose disc are optimized for 0.15mm via+8mil ring widthes；
D, the via of 0.15mm via+8mil ring widthes is adjusted to a diameter of 0.2mm；
（2）Make via：A diameter of 0.15mm via is bored using 0.15mm drill bit on drilling machine, using 0.2mm brill Head bores a diameter of 0.2mm via；
（3）Copper facing is carried out behind drill-through hole, crossing after hole plating copper for 0.15mm crosses hole surface copper ring ring width for 6mil, 0.2mm via It is 6mil that hole surface copper ring ring width is crossed after copper facing.
CN201510126595.XA 2015-03-23 2015-03-23 The preparation method of package substrate via Active CN104735913B (en)

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Application Number Priority Date Filing Date Title
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CN104735913B true CN104735913B (en) 2017-09-29

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107520470A (en) * 2017-09-30 2017-12-29 奥士康科技股份有限公司 A kind of method for lifting drilling efficiency
CN110149770A (en) * 2019-06-12 2019-08-20 重庆方正高密电子有限公司 The manufacturing method and multilayer printed circuit board of multilayer printed circuit board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103942351A (en) * 2013-01-19 2014-07-23 鸿富锦精密工业（深圳）有限公司 Designing system and method for increasing number of layers of circuit board
CN104023484A (en) * 2014-05-09 2014-09-03 东莞市五株电子科技有限公司 Manufacturing method of printed circuit board overlaid through hole structure
CN104244590A (en) * 2014-08-28 2014-12-24 广州兴森快捷电路科技有限公司 Control method of outer layer deviation of circuit boards

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8729426B2 (en) * 2008-12-13 2014-05-20 M-Solv Ltd. Method and apparatus for laser machining relatively narrow and relatively wide structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103942351A (en) * 2013-01-19 2014-07-23 鸿富锦精密工业（深圳）有限公司 Designing system and method for increasing number of layers of circuit board
CN104023484A (en) * 2014-05-09 2014-09-03 东莞市五株电子科技有限公司 Manufacturing method of printed circuit board overlaid through hole structure
CN104244590A (en) * 2014-08-28 2014-12-24 广州兴森快捷电路科技有限公司 Control method of outer layer deviation of circuit boards

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