CN104734679B - Low voltage reset circuit - Google Patents
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- CN104734679B CN104734679B CN201510061770.1A CN201510061770A CN104734679B CN 104734679 B CN104734679 B CN 104734679B CN 201510061770 A CN201510061770 A CN 201510061770A CN 104734679 B CN104734679 B CN 104734679B
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Abstract
The present invention provides a kind of low voltage reset circuit, including：Current source, first resistor, second resistance, 3rd resistor, the 4th resistance, comparator and thyrite；Current source, first resistor, thyrite and second resistance are sequentially connected in series, and are connected between supply voltage and ground；3rd resistor and the 4th resistance are one another in series, and are connected between supply voltage and ground；The sampled voltage extracted out between the negative input end of comparator and 3rd resistor and the 4th resistance is connected；The positive input terminal of comparator is connected with the reference voltage extracted out between current source and first resistor；Current source system is used to generate a stable reference voltage by the electric current of band gap reference main circuit one zero-temperature coefficient of generation or the electric current of positive temperature coefficient.The present invention during system fast powering-up, can be correctly created the reset signal of high level pulse；In addition, when system power supply power down is to ultralow pressure, reset signal will not be mistakenly discharged.
Description
Technical field
The present invention relates to Analogous Integrated Electronic Circuits or hybrid digital-analog integrated circuit technical fields, and specifically, the present invention relates to
And a kind of low voltage reset circuit.
Background technology
Low voltage resetting (LVR：Low Voltage Reset) main function of circuit is in system electrification or power down process
In, when supply voltage is less than setting voltage value, generate the reset of the high level pulse (high pulse) of a proper width
(reset) signal resets system, to ensure the stability of all internal digital logics.LVR circuits are microcontroller (MCU) systems
It unites essential Important Circuit module, is widely used in Analogous Integrated Electronic Circuits and hybrid digital-analog integrated circuit field.
Figure 1A is a kind of configuration diagram of low voltage reset circuit of the prior art.Traditional high-precision LVR circuits are general
All over all using framework as shown in Figure 1A, i.e.,：Band gap reference (bandgap) circuit is realized plus comparator CMP.But this
Kind of framework there are two it is serious the problem of：
1. Figure 1B is a kind of low voltage reset circuit of the prior art shown in Figure 1A during system fast powering-up
The schematic diagram of failure.Since band-gap reference source circuit settling time is longer, system is in fast powering-up, from first resistor R1 and
What the rate of climb of the sampled voltage VSAMP drawn between two resistance R2 was faster than reference voltage V REF establishes speed, causes to sample
The voltage of voltage VSAMP is consistently greater than the voltage of reference voltage V REF, and LVR circuits can not generate the reset letter of high level pulse
Number, as shown in Figure 1B.Most systems need to increase other circuit modules to make up this problem that fast powering-up occurs, but
It is that the circuit newly increased not only needs to increase power consumption and area, but also more or less there are the defects of some other aspect.
2. Fig. 1 C are a kind of low voltage reset circuit of the prior art shown in Figure 1A during system power supply power down
The schematic diagram of failure.During system power supply VDD power down, sampled voltage VSAMP declines with system power supply vdd line, and
Reference voltage V REF is remained unchanged at this time, and when reaching setting voltage value, the curve of sampled voltage VSAMP is with reference voltage V REF's
There is first " intersection point " in curve, generates reset signal at this time.When system power supply VDD continues to drop to certain low pressure, band gap base
Quasi- source circuit can not work normally under low pressure so that the curve of reference voltage V REF declines rapidly, with sampled voltage VSAMP's
Second " intersection point " occurs for curve, the reset signal mistake of high level pulse is caused to discharge, as shown in Figure 1 C.
The content of the invention
A technical problem to be solved by this invention is to provide a kind of low voltage reset circuit, can be in system fast powering-up
During, it is correctly created the reset signal of high level pulse.
Another technical problem to be solved by this invention is to provide a kind of low voltage reset circuit, can fall in system power supply
When electricity is to ultralow pressure, the reset signal of high level pulse will not be mistakenly discharged.
In order to solve the above technical problems, the present invention provides a kind of low voltage reset circuit, including：Current source, first resistor,
Two resistance, 3rd resistor, the 4th resistance, comparator and thyrite；
The current source, the first resistor, the thyrite and the second resistance are sequentially connected in series, and are connected to power supply
Between voltage and ground；
The 3rd resistor and the 4th resistance are one another in series, and are connected between the supply voltage and ground；
The sampled voltage phase extracted out between the negative input end of the comparator and the 3rd resistor and the 4th resistance
Connection；The reference voltage extracted out between the positive input terminal of the comparator and the current source and the first resistor is connected；
The output terminal of the comparator obtains the output result of the low voltage reset circuit；
ZTC electric current or positive temperature of the current source system by band gap reference main circuit one zero-temperature coefficient of generation
The PTAT current of coefficient, and then for generating a stable reference voltage.
Optionally, the low voltage reset circuit further includes PNP triode, and emitter and its collector are connected to described the
Between two resistance and ground, base stage is also connected with ground.
Optionally, the low voltage reset circuit further includes RC delay circuits, and the RC delay circuits include：Time delay resistance and
Delay capacitor；
The time delay resistance and the delay capacitor are one another in series, and are connected between the supply voltage and ground, Huo Zhelian
It is connected between the internal voltage output and ground of the band gap reference main circuit；
The delay control extracted out between the voltage controling end of the thyrite and the time delay resistance and the delay capacitor
Voltage processed is connected.
Optionally, the thyrite includes NMOS tube.
The thyrite includes PMOS tube, and the gate terminal of the PMOS tube is connected inside the band gap reference main circuit
The gate terminal of the node either generated or the PMOS tube is extracted directly with ground connection, controls the delays time to control electricity
Pressure.
Optionally, the thyrite further includes PMOS tube, and the NMOS tube and the PMOS tube are one another in series, are connected to
Between the first resistor and the second resistance, the gate terminal of the PMOS tube is connected inside the band gap reference main circuit
The gate terminal of the node either generated or the PMOS tube is extracted directly with ground connection, controls the delays time to control electricity
Pressure.
Optionally, the realization method of the time delay resistance is the transistor of conventional, electric-resistance, NMOS types or PMOS types,
The NMOS either the transistor of PMOS types gate terminal using fixed voltage control or use the band gap reference
The internal node control of main circuit.
Optionally, the internal voltage output of the band gap reference main circuit is lower 1.0V than the supply voltage.
Optionally, the low voltage reset circuit further includes：Back biased diode, positive terminal and the delays time to control voltage phase
Connection, negative pole end are connected with the internal voltage output of the supply voltage or the band gap reference main circuit.
Optionally, the back biased diode is the transistor of Schottky diode, PMOS types or NMOS types.
Compared with prior art, the invention has the characteristics that and advantage：
The low voltage reset circuit of the present invention breaches the limitation of conventional low reset circuit, is that one kind can meet quickly
The high reliability applied under upper electricity demanding and/or ultralow pressure, high precision low pressure reset circuit.The low voltage reset circuit only needs to increase
One thyrite, it becomes possible to when system power supply power down is to ultralow pressure, not discharge the reset signal of high level pulse mistakenly；
And if increase a thyrite and a RC delay circuit simultaneously, form clamp circuit, then can be in system fast powering-up
In the process, it is correctly created the reset signal of high level pulse.
The present invention, almost without chip area, power consumption and cost is increased, just can significantly improve electricity compared with the prior art
Road performance does not introduce the defects of other new again.
Description of the drawings
The above and other features of the present invention, property and advantage will pass through retouching with reference to the accompanying drawings and examples
It states and becomes readily apparent from, wherein：
Figure 1A is a kind of configuration diagram of low voltage reset circuit of the prior art；
Figure 1B is that a kind of low voltage reset circuit of the prior art shown in Figure 1A loses during system fast powering-up
The schematic diagram of effect；
Fig. 1 C are that a kind of low voltage reset circuit of the prior art shown in Figure 1A loses during system power supply power down
The schematic diagram of effect；
Fig. 2A is the frame of the low voltage reset circuit based on current-type band gap reference source main circuit of one embodiment of the invention
Structure schematic diagram；
Fig. 2 B are the frame of the low voltage reset circuit based on voltage-type band gap reference main circuit of one embodiment of the invention
Structure schematic diagram；
Fig. 3 A are that work of the low voltage reset circuit of one embodiment of the invention under system power supply power down to ultralow pressure is former
Manage schematic diagram；
Fig. 3 B are operation principle of the low voltage reset circuit of one embodiment of the invention during system fast powering-up
Schematic diagram；
Fig. 4 A1 are the frame of the low voltage reset circuit based on current-type band gap reference source main circuit of one embodiment of the invention
Structure schematic diagram；
Fig. 4 A2 are the frame of the low voltage reset circuit based on voltage-type band gap reference main circuit of one embodiment of the invention
Structure schematic diagram；
Fig. 4 B1 are the low voltage reset circuit based on current-type band gap reference source main circuit of another embodiment of the present invention
Configuration diagram；
Fig. 4 B2 are the low voltage reset circuit based on voltage-type band gap reference main circuit of another embodiment of the present invention
Configuration diagram；
Fig. 5 A1 to Fig. 5 A5 be one embodiment of the invention low voltage reset circuit in time delay resistance several different work(
The schematic diagram of energy realization method；
Fig. 5 B are the internal node that band gap reference main circuit is used in the low voltage reset circuit of one embodiment of the invention
The gate terminal of PMOS tube is controlled to realize the configuration diagram of the function of time delay resistance；
Fig. 6 is to use the internal node of band gap reference main circuit real in the low voltage reset circuit of one embodiment of the invention
The configuration diagram of existing RC delay functions；
Fig. 7 is the low voltage reset circuit of one embodiment of the invention in delays time to control voltage and supply voltage or other level
Between add in back biased diode local configuration diagram.
Specific embodiment
The circuit framework and circuit operation principle of the present invention are described further with reference to specific embodiments and the drawings,
Elaborate more details in the following description to facilitate a thorough understanding of the present invention, still the present invention obviously can with it is a variety of not
The other manner of this description is same as to implement, those skilled in the art can be without violating the connotation of the present invention according to reality
Border applicable cases make similar popularization, deduce, therefore should not be limited the scope of the invention with the content of this specific embodiment.
Fig. 2A is the frame of the low voltage reset circuit based on current-type band gap reference source main circuit of one embodiment of the invention
Structure schematic diagram；Fig. 2 B are the frame of the low voltage reset circuit based on voltage-type band gap reference main circuit of one embodiment of the invention
Structure schematic diagram.Fig. 3 A are that work of the low voltage reset circuit of one embodiment of the invention under system power supply power down to ultralow pressure is former
Manage schematic diagram；Fig. 3 B are operation principle of the low voltage reset circuit of one embodiment of the invention during system fast powering-up
Schematic diagram.It should be noted that these and follow-up other attached drawings are only as an example, should not be in this, as to the present invention
The protection domain of actual requirement is construed as limiting.
As shown in Fig. 2A Fig. 2 B, which mainly includes：Current source, first resistor R21, second resistance
R22,3rd resistor R3, the 4th resistance R4, comparator CMP and thyrite V-R.Wherein, current source, first resistor R21, voltage-controlled
Resistance V-R and second resistance R22 are sequentially connected in series, and are connected between supply voltage VDD and ground.3rd resistor R3 and the 4th resistance R4
It is one another in series, is connected between supply voltage VDD and ground.The negative input end of comparator CMP and 3rd resistor R3 and the 4th resistance
The sampled voltage VSAMP extracted out between R4 is connected；Between the positive input terminal and current source of comparator CMP and first resistor R21
The reference voltage V REF of extraction is connected；The output terminal of comparator CMP obtains the output result LVR_ of the low voltage reset circuit
OUT.The current source system by band gap reference main circuit (not shown) generate a zero-temperature coefficient electric current (ZTC electric currents) or
The electric current (PTAT current) of one positive temperature coefficient of person, and then it is respectively used to generate the base of a stabilization for varying with temperature very little
Quasi- voltage VREF.
As shown in Figure 2 B, for the low voltage reset circuit based on voltage-type band gap reference main circuit, current source passes through
What band gap reference main circuit generated is the PTAT current of a positive temperature coefficient.The low voltage reset circuit is in the group described in leading portion
A PNP triode is further included on the basis of into element, emitter and its collector are connected to second resistance R22 and ground
Between, base stage is also connected with ground.
Continuing with as shown in Figure 2 B, the PTAT current stream of this positive temperature coefficient is in first resistor R21, second resistance R22
With the reference voltage V REF that a stabilization for varying with temperature very little can be generated in PNP triode.In view of most of
CMOS technology can only provide parasitic PNP triode, and collector (Collector) is manufactured using p- substrates, so selection
Thyrite V-R is connected between the emitter (Emitter) of PNP triode and second resistance R22 or first resistor
At some node between R21 and second resistance R22, i.e. the specific ratio of first resistor R21 and second resistance R22 need basis
Depending on actual circuit characteristic and system correlation properties.The resistance value of thyrite V-R is directly or indirectly by supply voltage VDD
Control：As supply voltage VDD higher, thyrite V-R resistance value very littles, thereon pressure drop can be ignored, so ensure that
Reference voltage V REF characteristics (such as temperature coefficient) in the range of normal working voltage will not be impacted；But work as supply voltage
When VDD is reduced to low voltage reset circuit setting voltage value, the resistance value of thyrite V-R increased dramatically, and reference voltage V REF is lifted
Height, so as to solve previous circuit under low pressure reference voltage V REF rapidly decline caused by reset signal mistake discharge ask
Topic.As shown in Figure 3A, dash area therein is exactly the reset signal period that can generate high level pulse.
It please transfer as shown in Figure 2 A, for the low voltage reset circuit based on current-type band gap reference source main circuit, electric current
Source by band gap reference main circuit generate be a zero-temperature coefficient ZTC electric currents.This electric current stream is in first resistor R21
With the reference voltage V REF that a stabilization for varying with temperature very little can be generated on second resistance R22.Thyrite V-R can
It is positioned at some node between first resistor R21 and second resistance R22, i.e. the tool of first resistor R21 and second resistance R22
Body ratio is needed depending on actual circuit characteristic and system correlation properties.The operation principle of thyrite V-R is the same as based on electricity
Described by the low voltage reset circuit framework of die mould band gap reference main circuit.
The reset signal of high level pulse can not be generated during in order to solve the problems, such as system fast powering-up, in voltage-controlled electricity
The voltage controling end of resistance V-R can add in RC delay circuits.As shown in Figure 2 A and 2 B, still it is based on whether based on voltage-type
The low voltage reset circuit of the band gap reference main circuit of current mode, further includes RC delay circuits.The RC delay circuits mainly wrap
It includes：Time delay resistance R0 and delay capacitor C0.Wherein, time delay resistance R0 and delay capacitor C0 are one another in series, and are connected to supply voltage
Between VDD and ground.Certainly, time delay resistance R0 and delay capacitor C0 can also be connected to band gap reference main circuit after being one another in series
Some internal voltage output (i.e. " other level " in Fig. 2A and Fig. 2 B) between ground, this situation will be described below
It arrives.And the delays time to control voltage that the voltage controling end of thyrite V-R is then extracted out between time delay resistance R0 and delay capacitor C0
VK is connected.
After the voltage controling end of thyrite V-R adds RC delay circuits, when supply voltage VDD is quickly raised,
Delays time to control voltage VK (depends on RC design loads, the i.e. product of RC) less than supply voltage VDD whithin a period of time, during which voltage-controlled
Resistance V-R resistance values are very big, so as to which reference voltage V REF be raised, low voltage reset circuit helped to generate reset signal.Such as Fig. 3 B institutes
Show, dash area therein is exactly the reset signal period that can generate high level pulse.
For the device in low voltage reset circuit framework proposed by the invention (including thyrite V-R, time delay resistance R0
With supply voltage VDD etc.), different modes may be employed to realize.It is following to provide a variety of circuit implementations successively.
1) on thyrite V-R
Fig. 4 A1 are the frame of the low voltage reset circuit based on current-type band gap reference source main circuit of one embodiment of the invention
Structure schematic diagram；Fig. 4 A2 are the low voltage reset circuit based on voltage-type band gap reference main circuit of one embodiment of the invention
Configuration diagram.As shown in Fig. 4 A1 and Fig. 4 A2, wherein employing NMOS tube N1 to realize the function of thyrite V-R.This
Kind way is easily achieved the requirement of thyrite V-R, i.e.,：During delays time to control voltage VK higher, the conducting resistance of NMOS tube N1
Very little；When delays time to control voltage VK is relatively low, the conducting resistance of NMOS tube N1 is larger, plays the work of lifting reference voltage V REF
With.
Fig. 4 B1 are the low voltage reset circuit based on current-type band gap reference source main circuit of another embodiment of the present invention
Configuration diagram；Fig. 4 B2 are the electricity of the low voltage resetting based on voltage-type band gap reference main circuit of another embodiment of the present invention
The configuration diagram on road.As shown in Fig. 4 B1 and Fig. 4 B2, wherein employing the function that PMOS tube P1 realizes thyrite V-R.
At this point, PMOS cannot be controlled by the mode of RC delay circuits with the supply voltage VDD shown in above-mentioned Fig. 4 A1 and Fig. 4 A2 again
The gate terminal of pipe P1, but need to extract a node inside band gap reference main circuit or generate a node (in i.e.
Portion's output voltage), which needs to meet following requirement：During system power source voltage VDD higher, delays time to control voltage VK is very low；
And supply voltage VDD it is relatively low when, delays time to control voltage VK higher.Also a kind of fairly simple way is：Land used (GND) is direct
Delays time to control voltage VK is controlled, i.e., is directly connected the gate terminal of PMOS tube P1 with ground.The gate source voltage VGS of PMOS tube P1 at this time
=k*VREF (k is a proportionality coefficient).As reference voltage V REF higher, the conducting resistance very little of PMOS tube P1；And work as base
When quasi- voltage VREF is relatively low, the conducting resistance increase of PMOS tube P1 avoids the occurrence of what reference voltage V REF under low pressure declined rapidly
Problem.But, because this mode not necessarily can thoroughly solve the problems, such as that reset signal can not be generated during system fast powering-up,
So it is generally only applicable in the system of no fast powering-up demand.
In the present invention, using Fig. 4 A1 Fig. 4 B1 or Fig. 4 A2 can also be added to add the mode of Fig. 4 B2 in circuit simultaneously
Two thyrites are added in control reference voltage V REF, if circuit design is reasonable, effect should be able to be more preferable.Press
Control resistance V-R can include NMOS tube N1 simultaneously and PMOS tube P1, the two are one another in series, and is connected to first resistor R21 and second
Between resistance R22.Wherein, the node extracted inside the gate terminal connection band gap reference main circuit of PMOS tube P1 or production
A raw node or the gate terminal of PMOS tube P1 are directly connected with ground, to control delays time to control voltage VK.
2) on time delay resistance R0
The realization method of time delay resistance R0 is also very much, and Fig. 5 A1 to Fig. 5 A5 are the low voltage resetting electricity of one embodiment of the invention
The schematic diagram of several different function realization methods of time delay resistance in road.As shown in Fig. 5 A1 to Fig. 5 A5, time delay resistance R0
Realization method be conventional, electric-resistance, NMOS types or PMOS types transistor.Meanwhile the crystal of NMOS PMOS types
The control of fixed voltage may be employed in the gate terminal of pipe, can also using some internal node VX of band gap reference main circuit come
Control.
Fig. 5 B are the internal node that band gap reference main circuit is used in the low voltage reset circuit of one embodiment of the invention
The gate terminal of PMOS tube is controlled to realize the configuration diagram of the function of time delay resistance.As shown in Figure 5 B, this control mode has
Following two advantages：
A. in supply voltage VDD power up, due to the presence of larger electric capacity of voltage regulation CP, internal voltage output OUT with
Supply voltage VDD is raised together, and gate source voltage VGS=(VDD-OUT) very little of PMOS tube P1, conducting resistance is very big, RC delays
Circuit delay effect is apparent so that delays time to control voltage VK, less than supply voltage VDD, is during which used as pressure in longer period of time
It is very big to control the conducting resistance of the NMOS tube N1 of resistance, so as to which reference voltage V REF be raised, is generated convenient for low voltage reset circuit multiple
Position signal, when can solve the problems, such as system fast powering-up.
The gate source voltage VGS=(VDD-OUT) of b.PMOS pipes P1 is mainly determined by the size of current of band gap reference main circuit
It is fixed, it is kept constant when circuit works normally, so controlling the grid of PMOS tube P1 using a certain internal voltage output OUT
End, can make the electric current for flowing through PMOS tube P1 and main circuit proportional, can so substantially reduce the conducting of PMOS tube P1
The range of variation of resistance, you can to substantially reduce the variation model of the reset signal high-level pulse width of low voltage reset circuit generation
It encloses.
3) on supply voltage VDD
Fig. 6 is to use the internal node of band gap reference main circuit real in the low voltage reset circuit of one embodiment of the invention
The configuration diagram of existing RC delay functions.As shown in fig. 6, such improvement has following two advantages：
A. under normal conditions, the internal voltage output OUT of band gap reference main circuit is less than supply voltage VDD about 1.0V,
It goes to make to be delayed that with smaller internal voltage output OUT required RC values can be reduced, you can to save certain chip area.
B. during system electrification, the start-up circuit (start-up) inside band gap reference can be to inside output electricity
Pressure OUT, so as to which delays time to control voltage VK is also dragged down, is considerably increased as pressure there are one low level action is pulled down to
Control the conducting resistance of the NMOS tube N1 of resistance.
4) on adding in other devices further to improve circuit characteristic
Fig. 7 is the low voltage reset circuit of one embodiment of the invention in delays time to control voltage and supply voltage or other level
Between add in back biased diode local configuration diagram.As shown in fig. 7, its positive terminal of back biased diode D0 is controlled with delay
Voltage VK processed is connected, negative pole end and supply voltage VDD or other level (such as the inside of band gap reference main circuit exports
Voltage OUT) it is connected.Therefore, back biased diode is added between delays time to control voltage VK and supply voltage VDD or other level
After D0, when supply voltage VDD is quickly reduced, the charge stored at delays time to control voltage VK can be quick by back biased diode D0
Release reduces delays time to control voltage VK, and RC delay circuits, which can play, during to power on again raises reference voltage V REF's
Effect.In the present embodiment, back biased diode D0 be preferably able to selection conduction voltage drop small (such as conduction voltage drop be less than 0.6V) and
Reverse leakage also small diode (such as Schottky diode)；If processing procedure is not supported, also may be selected PMOS types or
The transistor of NMOS types replaces.
In conclusion the low voltage reset circuit of the present invention breaches the limitation of conventional low reset circuit, it is a kind of
The high reliability applied under fast powering-up demand and/or ultralow pressure, high precision low pressure reset circuit can be met.Low voltage resetting electricity
Road need to only increase a thyrite, it becomes possible to when system power supply power down is to ultralow pressure, not discharge high level pulse mistakenly
Reset signal；And if increase a thyrite and a RC delay circuit simultaneously, form clamp circuit, then can be in system
During fast powering-up, the reset signal of high level pulse is correctly created.
The present invention, almost without chip area, power consumption and cost is increased, just can significantly improve electricity compared with the prior art
Road performance does not introduce the defects of other new again.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this field skill
Art personnel without departing from the spirit and scope of the present invention, can make possible variation and modification.Therefore, it is every without departing from
The content of technical solution of the present invention, any modification that technical spirit according to the invention makees above example, equivalent variations
And modification, it each falls within the protection domain that the claims in the present invention are defined.
Claims (10)
1. a kind of low voltage reset circuit, including：Current source, first resistor (R21), second resistance (R22), 3rd resistor (R3),
4th resistance (R4), comparator (CMP) and thyrite (V-R)；
The current source, the first resistor (R21), the thyrite (V-R) and the second resistance (R22) are gone here and there successively
Connection, is connected to supply voltage (VDD) between ground；
The 3rd resistor (R3) and the 4th resistance (R4) are one another in series, and are connected to the supply voltage (VDD) and ground
Between；
That is extracted out between the negative input end of the comparator (CMP) and the 3rd resistor (R3) and the 4th resistance (R4) adopts
Sample voltage (VSAMP) is connected；The positive input terminal of the comparator (CMP) and the current source and the first resistor (R21)
Between the reference voltage (VREF) extracted out be connected；The output terminal of the comparator (CMP) obtains the low voltage reset circuit
Export result (LVR_OUT)；
The current source system generates the ZTC electric currents or positive temperature coefficient of a zero-temperature coefficient by band gap reference main circuit
PTAT current, and then for generate a stable reference voltage (VREF).
2. low voltage reset circuit according to claim 1, which is characterized in that further include PNP triode, emitter and its
Collector is connected to the second resistance (R22) between ground, and base stage is also connected with ground.
3. low voltage reset circuit according to claim 1 or 2, which is characterized in that further include RC delay circuits, the RC prolongs
When circuit include：Time delay resistance (R0) and delay capacitor (C0)；
The time delay resistance (R0) and the delay capacitor (C0) are one another in series, and are connected to the supply voltage (VDD) and ground
Between or be connected to the internal voltage output (OUT) of the band gap reference main circuit between ground；
It is extracted out between the voltage controling end of the thyrite (V-R) and the time delay resistance (R0) and the delay capacitor (C0)
Delays time to control voltage (VK) be connected.
4. low voltage reset circuit according to claim 3, which is characterized in that the thyrite (V-R) includes NMOS tube
(N1)。
5. low voltage reset circuit according to claim 3, which is characterized in that the thyrite (V-R) includes PMOS tube
(P1), the gate terminal of the PMOS tube (P1) connects the section for extracting or generating inside the band gap reference main circuit
The gate terminal of point or the PMOS tube (P1) is directly connected with ground, controls the delays time to control voltage (VK).
6. low voltage reset circuit according to claim 4, which is characterized in that the thyrite (V-R) further includes PMOS
It manages (P1), the NMOS tube (N1) and the PMOS tube (P1) be one another in series, and is connected to the first resistor (R21) and described the
Between two resistance (R22), the gate terminal of the PMOS tube (P1), which connects, to extract or is produced inside the band gap reference main circuit
A raw node or the gate terminal of the PMOS tube (P1) are directly connected with ground, control the delays time to control voltage (VK).
7. the low voltage reset circuit according to claim 4 or 6, which is characterized in that the realization side of the time delay resistance (R0)
Formula is conventional, electric-resistance, the grid of the NMOS types either transistor of the transistor NMOS PMOS types of PMOS types
End is controlled using fixed voltage or is controlled using the internal node (VX) of the band gap reference main circuit.
8. low voltage reset circuit according to claim 7, which is characterized in that the inside of the band gap reference main circuit is defeated
It is lower 1.0V than the supply voltage (VDD) to go out voltage (OUT).
9. low voltage reset circuit according to claim 8, which is characterized in that the low voltage reset circuit further includes：It is reverse-biased
Diode (D0), positive terminal are connected with the delays time to control voltage (VK), negative pole end and the supply voltage (VDD) or
The internal voltage output (OUT) of band gap reference main circuit described in person is connected.
10. low voltage reset circuit according to claim 9, which is characterized in that the back biased diode (D0) is Schottky
The transistor of diode, PMOS types or NMOS types.
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| CN201510061770.1A CN104734679B (en) | 2015-02-05 | 2015-02-05 | Low voltage reset circuit |
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| CN201510061770.1A CN104734679B (en) | 2015-02-05 | 2015-02-05 | Low voltage reset circuit |
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| CN104734679B true CN104734679B (en) | 2018-05-22 |
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|---|---|---|---|---|
| CN102624369A (en) * | 2012-01-12 | 2012-08-01 | 苏州华芯微电子股份有限公司 | POR (Power-on Reset) circuit with variable reset point on basis of band gap reference source |
| CN103633974A (en) * | 2013-12-04 | 2014-03-12 | 安徽理工大学 | Power-on reset circuit with fixed resistance-capacitance time delay characteristic |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1168539A (en) * | 1997-08-08 | 1999-03-09 | Oki Electric Ind Co Ltd | Power-on-reset circuit |
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2015
- 2015-02-05 CN CN201510061770.1A patent/CN104734679B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102624369A (en) * | 2012-01-12 | 2012-08-01 | 苏州华芯微电子股份有限公司 | POR (Power-on Reset) circuit with variable reset point on basis of band gap reference source |
| CN103633974A (en) * | 2013-12-04 | 2014-03-12 | 安徽理工大学 | Power-on reset circuit with fixed resistance-capacitance time delay characteristic |
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| CN104734679A (en) | 2015-06-24 |
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