CN104734679A - Low-voltage reset circuit - Google Patents
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Abstract
The invention provides a low-voltage reset circuit. The low-voltage reset circuit comprises a current source, a first resistor, a second resistor, a third resistor, a fourth resistor, a comparator and a voltage-controlled resistor; the current source, the first resistor, the voltage-controlled resistor and the second resistor are sequentially connected in series and are connected between a supply voltage and the ground; the third resistor and the fourth resistor are connected with each other in series and are connected between the current source and the ground; the negative input end of the comparator is connected with sampling voltages extracted from the third resistor and the fourth resistor; the positive input end of the comparator is connected with sampling voltages extracted from the current source and the first resistor, and the current source generates a current with a zero-temperature coefficient or a current with a positive-temperature coefficient and then is used for generating a stable reference voltage. According to the low-voltage reset circuit, a high-level pulse reset signal is generated correctly; in addition, when a system power source powers down to an ultra-low voltage, the reset signal cannot be released wrongly.
Description
Technical field
The present invention relates to analog integrated circuit or hybrid digital-analog integrated circuit technical field, specifically, the present invention relates to a kind of low voltage reset circuit.
Background technology
The Main Function of low voltage resetting (LVR:Low Voltage Reset) circuit is in system electrification or power down process, when supply voltage is lower than setting voltage value, reset (reset) signal producing the high level pulse (highpulse) of a proper width carrys out resetting system, to ensure the stability of all internal digital logic.LVR circuit is the requisite Important Circuit module of microcontroller (MCU) system, is widely used in analog integrated circuit and hybrid digital-analog integrated circuit field.
Figure 1A is the configuration diagram of a kind of low voltage reset circuit of the prior art.Traditional high accuracy LVR circuit generally all adopts framework as shown in Figure 1A, that is: band gap reference (bandgap) circuit adds comparator CMP to realize.But there are two serious problems in this framework:
1. the schematic diagram that lost efficacy in the process of system fast powering-up for the of the prior art a kind of low voltage reset circuit shown in Figure 1A of Figure 1B.Because band-gap reference source circuit is longer for settling time, system is when fast powering-up, speed is set up faster than reference voltage V REF from the rate of climb of the sampled voltage VSAMP drawn between the first resistance R1 and the second resistance R2, the voltage of sampled voltage VSAMP is caused to be greater than the voltage of reference voltage V REF all the time, LVR circuit cannot produce the reset signal of high level pulse, as shown in Figure 1B.Most systems needs to increase this problem that other circuit modules occur to make up fast powering-up, but the circuit newly increased not only needs to increase power consumption and area, and more or less there is the defect of some other aspect.
2. the schematic diagram that lost efficacy in the process of system power supply power down for the of the prior art a kind of low voltage reset circuit shown in Figure 1A of Fig. 1 C.In the process of system power supply VDD power down, sampled voltage VSAMP declines with system power supply vdd line, and now reference voltage V REF remains unchanged, when arriving setting voltage value, the curve of sampled voltage VSAMP and the curve of reference voltage V REF occur first " intersection point ", now produce reset signal.When system power supply VDD continues to drop to certain low pressure, band-gap reference source circuit cannot under low pressure normally work, the curve of reference voltage V REF is declined rapidly, occur second " intersection point " with the curve of sampled voltage VSAMP, the reset signal mistake of high level pulse is caused to discharge, as shown in Figure 1 C.
Summary of the invention
A technical problem to be solved by this invention is to provide a kind of low voltage reset circuit, in the process of system fast powering-up, can correctly produce the reset signal of high level pulse.
Another technical problem to be solved by this invention is to provide a kind of low voltage reset circuit, when system power supply power down is to ultralow pressure, can not discharge the reset signal of high level pulse mistakenly.
For solving the problems of the technologies described above, the invention provides a kind of low voltage reset circuit, comprising: current source, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, comparator and thyrite;
Described current source, described first resistance, described thyrite and described second resistance are connected successively, are connected between supply voltage and ground;
Described 3rd resistance and described 4th resistance are one another in series, and are connected between described supply voltage and ground;
The negative input end of described comparator is connected with the sampled voltage extracted out between described 3rd resistance and described 4th resistance; The positive input terminal of described comparator is connected with the reference voltage extracted out between described current source and described first resistance; The output of described comparator obtains the Output rusults of described low voltage reset circuit;
Described current source system produces the ZTC electric current of a zero-temperature coefficient or the PTAT electric current of positive temperature coefficient by band gap reference main circuit, and then for generation of a stable described reference voltage.
Alternatively, described low voltage reset circuit also comprises PNP triode, and its emitter and its collector electrode are connected between described second resistance and ground, and its base stage is also connected with ground.
Alternatively, described low voltage reset circuit also comprises RC delay circuit, and described RC delay circuit comprises: time delay resistance and delay capacitor;
Described time delay resistance and described delay capacitor are one another in series, and are connected between described supply voltage and ground, or between the internal voltage output being connected to described band gap reference main circuit and ground;
The voltage controling end of described thyrite is connected with the delays time to control voltage extracted out between described time delay resistance and described delay capacitor.
Alternatively, described thyrite comprises NMOS tube.
Described thyrite comprises PMOS, and the gate terminal of described PMOS connects the node extracting or produce in described band gap reference main circuit inside, or the gate terminal of described PMOS is directly connected with ground, controls described delays time to control voltage.
Alternatively, described thyrite also comprises PMOS, described NMOS tube and described PMOS are one another in series, be connected between described first resistance and described second resistance, the gate terminal of described PMOS connects the node extracting or produce in described band gap reference main circuit inside, or the gate terminal of described PMOS is directly connected with ground, controls described delays time to control voltage.
Alternatively, the implementation of described time delay resistance is the transistor of conventional, electric-resistance, NMOS type or PMOS type, and the gate terminal of the transistor of described NMOS or PMOS type adopts fixing voltage control or adopts the described internal node of described band gap reference main circuit to control.
Alternatively, the internal voltage output of described band gap reference main circuit forces down 1.0V than described power electric.
Alternatively, described low voltage reset circuit also comprises: back biased diode, and its positive terminal is connected with described delays time to control voltage, and its negative pole end is connected with the internal voltage output of described supply voltage or described band gap reference main circuit.
Alternatively, described back biased diode is the transistor of Schottky diode, PMOS type or NMOS type.
Compared with prior art, the present invention has following characteristics and advantage:
Low voltage reset circuit of the present invention breaches the limitation of conventional low reset circuit, its be a kind of meet fast powering-up demand and/or ultralow pressure under high reliability, the high precision low pressure reset circuit applied.This low voltage reset circuit only need increase a thyrite, just when system power supply power down is to ultralow pressure, can not discharge the reset signal of high level pulse mistakenly; And if increase a thyrite and a RC delay circuit simultaneously, form clamp circuit, then in the process of system fast powering-up, can correctly produce the reset signal of high level pulse.
The present invention does not almost increase chip area, power consumption and cost relative to prior art, just can improve circuit performance significantly and not introduce again other new defect.
Accompanying drawing explanation
The above and other features of the present invention, character and advantage become more obvious by passing through below in conjunction with the description of drawings and Examples, wherein:
Figure 1A is the configuration diagram of a kind of low voltage reset circuit of the prior art;
The schematic diagram that Figure 1B lost efficacy in the process of system fast powering-up for the of the prior art a kind of low voltage reset circuit shown in Figure 1A;
The schematic diagram that Fig. 1 C lost efficacy in the process of system power supply power down for the of the prior art a kind of low voltage reset circuit shown in Figure 1A;
Fig. 2 A is the configuration diagram of the low voltage reset circuit based on current-type band gap reference source main circuit of one embodiment of the invention;
Fig. 2 B is the configuration diagram of the low voltage reset circuit based on voltage-type band gap reference main circuit of one embodiment of the invention;
Fig. 3 A is the operation principle schematic diagram of low voltage reset circuit under system power supply power down to ultralow pressure of one embodiment of the invention;
Fig. 3 B is the operation principle schematic diagram of low voltage reset circuit in the process of system fast powering-up of one embodiment of the invention;
Fig. 4 A1 is the configuration diagram of the low voltage reset circuit based on current-type band gap reference source main circuit of one embodiment of the invention;
Fig. 4 A2 is the configuration diagram of the low voltage reset circuit based on voltage-type band gap reference main circuit of one embodiment of the invention;
Fig. 4 B1 is the configuration diagram of the low voltage reset circuit based on current-type band gap reference source main circuit of another embodiment of the present invention;
Fig. 4 B2 is the configuration diagram of the low voltage reset circuit based on voltage-type band gap reference main circuit of another embodiment of the present invention;
Fig. 5 A1 to Fig. 5 A5 is the schematic diagram of several different functional realiey mode of time delay resistance in the low voltage reset circuit of one embodiment of the invention;
Fig. 5 B adopts the internal node of band gap reference main circuit to control the gate terminal of PMOS to realize the configuration diagram of the function of time delay resistance in the low voltage reset circuit of one embodiment of the invention;
Fig. 6 adopts the internal node of band gap reference main circuit to realize the configuration diagram of RC delay function in the low voltage reset circuit of one embodiment of the invention;
Fig. 7 is the local configuration diagram that the low voltage reset circuit of one embodiment of the invention adds back biased diode between delays time to control voltage and supply voltage or other level.
Embodiment
Below in conjunction with specific embodiments and the drawings, circuit framework of the present invention and circuit working principle are described further; set forth more details in the following description so that fully understand the present invention; but the present invention obviously can implement with multiple this alternate manner described that is different from; those skilled in the art can when doing similar popularization, deduction without prejudice to when intension of the present invention according to practical situations, therefore should with content constraints protection scope of the present invention of this specific embodiment.
Fig. 2 A is the configuration diagram of the low voltage reset circuit based on current-type band gap reference source main circuit of one embodiment of the invention; Fig. 2 B is the configuration diagram of the low voltage reset circuit based on voltage-type band gap reference main circuit of one embodiment of the invention.Fig. 3 A is the operation principle schematic diagram of low voltage reset circuit under system power supply power down to ultralow pressure of one embodiment of the invention; Fig. 3 B is the operation principle schematic diagram of low voltage reset circuit in the process of system fast powering-up of one embodiment of the invention.It should be noted that these and follow-up other accompanying drawing all only exemplarily, should not be construed as limiting in this, as to the protection range of actual requirement of the present invention.
As shown in Fig. 2 A or Fig. 2 B, this low voltage reset circuit mainly comprises: current source, the first resistance R21, the second resistance R22, the 3rd resistance R3, the 4th resistance R4, comparator CMP and thyrite V-R.Wherein, current source, the first resistance R21, thyrite V-R and the second resistance R22 connect successively, are connected between supply voltage VDD and ground.3rd resistance R3 and the 4th resistance R4 is one another in series, and is connected between supply voltage VDD and ground.The negative input end of comparator CMP is connected with the sampled voltage VSAMP extracted out between the 3rd resistance R3 and the 4th resistance R4; The positive input terminal of comparator CMP is connected with the reference voltage V REF extracted out between current source and the first resistance R21; The output of comparator CMP obtains the Output rusults LVR_OUT of this low voltage reset circuit.This current source system produces the electric current (ZTC electric current) of a zero-temperature coefficient or the electric current (PTAT electric current) of a positive temperature coefficient by band gap reference main circuit (not shown), and then is respectively used to generation one and varies with temperature very little stable reference voltage V REF.
As shown in Figure 2 B, for the low voltage reset circuit based on voltage-type band gap reference main circuit, what its current source was produced by band gap reference main circuit is the PTAT electric current of a positive temperature coefficient.This low voltage reset circuit also comprises a PNP triode on the basis of the element described in leading portion, and its emitter and its collector electrode are connected between the second resistance R22 and ground, and its base stage is also connected with ground.
Please continue as shown in Figure 2 B, the PTAT electric current stream of this positive temperature coefficient just can produce one and vary with temperature very little stable reference voltage V REF in the first resistance R21, the second resistance R22 and PNP triode.Consider the PNP triode that most of CMOS technology can only provide parasitic, its collector electrode (Collector) utilizes p-substrate to manufacture, so select thyrite V-R to be connected between the emitter (Emitter) of PNP triode and the second resistance R22, or certain Nodes between the first resistance R21 and the second resistance R22, namely the concrete ratio of the first resistance R21 and the second resistance R22 needs to determine according to side circuit characteristic and system correlation properties.The resistance value of this thyrite V-R directly or indirectly controls by supply voltage VDD: when supply voltage VDD is higher, thyrite V-R resistance is very little, on it, pressure drop is negligible, so just ensures to impact the reference voltage V REF characteristic (as temperature coefficient etc.) in normal operating voltage range; But when supply voltage VDD is reduced to low voltage reset circuit setting voltage value, the resistance of thyrite V-R sharply increases, reference voltage V REF is elevated, thus solve previous circuit under low pressure reference voltage V REF decline rapidly cause reset signal mistake release problem.As shown in Figure 3A, dash area is wherein exactly the reset signal time period that can produce high level pulse.
Please then as shown in Figure 2 A, for the low voltage reset circuit based on current-type band gap reference source main circuit, what its current source was produced by band gap reference main circuit is the ZTC electric current of a zero-temperature coefficient.This electric current stream just can produce one and vary with temperature very little stable reference voltage V REF on the first resistance R21 and the second resistance R22.Thyrite V-R can be positioned over certain Nodes between the first resistance R21 and the second resistance R22, and namely the concrete ratio of the first resistance R21 and the second resistance R22 needs to determine according to side circuit characteristic and system correlation properties.The operation principle of thyrite V-R is with described by the low voltage reset circuit framework based on voltage-type band gap reference main circuit.
In order to the reset signal problem of high level pulse cannot be produced in the process of resolution system fast powering-up, RC delay circuit can be added at the voltage controling end of thyrite V-R.As shown in Figure 2 A and 2 B, be no matter the low voltage reset circuit based on voltage-type or the band gap reference main circuit based on current mode, it also comprises RC delay circuit.This RC delay circuit mainly comprises: time delay resistance R0 and delay capacitor C0.Wherein, time delay resistance R0 and delay capacitor C0 is one another in series, and is connected between supply voltage VDD and ground.Certainly, also can be connected to after time delay resistance R0 and delay capacitor C0 is one another in series between certain internal voltage output (" other level " namely in Fig. 2 A and Fig. 2 B) of band gap reference main circuit and ground, this situation will be described to later.The voltage controling end of thyrite V-R is then connected with the delays time to control voltage VK extracted out between time delay resistance R0 and delay capacitor C0.
After the voltage controling end of thyrite V-R adds RC delay circuit, when supply voltage VDD raises fast, delays time to control voltage VK (depends on RC design load within a period of time, the i.e. product of RC) lower than supply voltage VDD, period thyrite V-R resistance is very large, thus reference voltage V REF is raised, help low voltage reset circuit to produce reset signal.As shown in Figure 3 B, dash area is wherein exactly the reset signal time period that can produce high level pulse.
For the device (comprising thyrite V-R, time delay resistance R0 and supply voltage VDD etc.) in low voltage reset circuit framework proposed by the invention, can realize in different ways.Followingly provide multiple circuit implementations successively.
1) about thyrite V-R
Fig. 4 A1 is the configuration diagram of the low voltage reset circuit based on current-type band gap reference source main circuit of one embodiment of the invention; Fig. 4 A2 is the configuration diagram of the low voltage reset circuit based on voltage-type band gap reference main circuit of one embodiment of the invention.As shown in Fig. 4 A1 and Fig. 4 A2, wherein all have employed NMOS tube N1 to realize the function of thyrite V-R.This way is easy to the requirement realizing thyrite V-R, that is:, when delays time to control voltage VK is higher, the conducting resistance of NMOS tube N1 is very little; When delays time to control voltage VK is lower, the conducting resistance of NMOS tube N1 is comparatively large, plays the effect of lifting reference voltage V REF.
Fig. 4 B1 is the configuration diagram of the low voltage reset circuit based on current-type band gap reference source main circuit of another embodiment of the present invention; Fig. 4 B2 is the configuration diagram of the low voltage reset circuit based on voltage-type band gap reference main circuit of another embodiment of the present invention.As shown in Fig. 4 B1 and Fig. 4 B2, wherein all have employed the function that PMOS P1 realizes thyrite V-R.Now, the gate terminal of PMOS P1 can not be controlled again through the mode of RC delay circuit with the supply voltage VDD shown in above-mentioned Fig. 4 A1 and Fig. 4 A2, but need to extract a node in band gap reference main circuit inside or produce a node (i.e. internal voltage output), this node demand fulfillment requires as follows: when system power source voltage VDD is higher, and delays time to control voltage VK is very low; And supply voltage VDD lower time, VK is higher for delays time to control voltage.A kind of fairly simple way is in addition: land used (GND) directly controls delays time to control voltage VK, and the gate terminal by PMOS P1 is directly connected with ground.The now gate source voltage VGS=k*VREF (k is a proportionality coefficient) of PMOS P1.When reference voltage V REF is higher, the conducting resistance of PMOS P1 is very little; And when reference voltage V REF is lower, the conducting resistance of PMOS P1 increases, avoid occurring the problem that reference voltage V REF declines rapidly under low pressure.But, because this mode not necessarily can thoroughly resolution system fast powering-up time cannot produce the problem of reset signal, so be generally only applicable in the system without fast powering-up demand.
In the present invention, Fig. 4 A1 also can be adopted to add Fig. 4 B1, or Fig. 4 A2 mode of adding Fig. 4 B2 adds two thyrites in circuit and controls reference voltage V REF, circuit design is reasonably talked about, and effect should be able to be better simultaneously.Namely thyrite V-R can comprise NMOS tube N1 and PMOS P1 simultaneously, and both are one another in series, and is connected between the first resistance R21 and the second resistance R22.Wherein, the gate terminal of PMOS P1 connects a node of a node or the generation extracted band gap reference main circuit inside, or the gate terminal of PMOS P1 is directly connected with ground, to control delays time to control voltage VK.
2) about time delay resistance R0
The implementation of time delay resistance R0 is also a lot, and Fig. 5 A1 to Fig. 5 A5 is the schematic diagram of several different functional realiey mode of time delay resistance in the low voltage reset circuit of one embodiment of the invention.As shown in Fig. 5 A1 to Fig. 5 A5, the implementation of this time delay resistance R0 is the transistor of conventional, electric-resistance, NMOS type or PMOS type.Meanwhile, the gate terminal of the transistor of NMOS or PMOS type can adopt fixing voltage control, and some internal node VX of band gap reference main circuit also can be adopted to control.
Fig. 5 B adopts the internal node of band gap reference main circuit to control the gate terminal of PMOS to realize the configuration diagram of the function of time delay resistance in the low voltage reset circuit of one embodiment of the invention.As shown in Figure 5 B, this control mode has following two advantages:
A. in supply voltage VDD power up, due to the existence of larger electric capacity of voltage regulation CP, internal voltage output OUT raises together along with supply voltage VDD, the gate source voltage VGS=(VDD-OUT) of PMOS P1 is very little, conducting resistance is very large, RC delay circuit time-lag action is obvious, make delays time to control voltage VK within longer a period of time lower than supply voltage VDD, period is very large as the conducting resistance of the NMOS tube N1 of thyrite, thus reference voltage V REF is raised, be convenient to low voltage reset circuit produce reset signal, can resolution system fast powering-up time problem.
The gate source voltage VGS=(VDD-OUT) of b.PMOS pipe P1 determines primarily of the size of current of band gap reference main circuit, it keeps constant when circuit normally works, so adopt a certain internal voltage output OUT to control the gate terminal of PMOS P1, electric current and the main circuit that can make to flow through PMOS P1 are proportional, greatly can reduce the range of variation of the conducting resistance of PMOS P1 like this, namely greatly can reduce the range of variation of the reset signal high-level pulse width that low voltage reset circuit produces.
3) about supply voltage VDD
Fig. 6 adopts the internal node of band gap reference main circuit to realize the configuration diagram of RC delay function in the low voltage reset circuit of one embodiment of the invention.As shown in Figure 6, such improvement has following two advantages:
A. under normal circumstances, the internal voltage output OUT of band gap reference main circuit is about 1.0V lower than supply voltage VDD, goes to do time delay and can reduce required RC value, namely can save certain chip area with less internal voltage output OUT.
B. in the process of system electrification, the start-up circuit (start-up) of band gap reference inside can have one to be pulled down to low level action to internal voltage output OUT, thus delays time to control voltage VK also can be dragged down, considerably increase the conducting resistance of the NMOS tube N1 as thyrite.
4) about adding other device to improve circuit characteristic further
Fig. 7 is the local configuration diagram that the low voltage reset circuit of one embodiment of the invention adds back biased diode between delays time to control voltage and supply voltage or other level.As shown in Figure 7, its positive terminal of this back biased diode D0 is connected with delays time to control voltage VK, and its negative pole end is connected with supply voltage VDD or other level (the internal voltage output OUT of such as band gap reference main circuit).Therefore, add back biased diode D0 between delays time to control voltage VK and supply voltage VDD or other level after, when supply voltage VDD reduces fast, the electric charge that delays time to control voltage VK place stores discharges fast by back biased diode D0, delays time to control voltage VK is reduced, so that RC delay circuit can play the effect of raising reference voltage V REF when again powering on.In the present embodiment, this back biased diode D0 preferably can select conduction voltage drop little (as conduction voltage drop is less than 0.6V) and the also little diode (such as Schottky diode) of reverse leakage; If processing procedure is not supported, the transistor of PMOS type or NMOS type also can be selected to replace.
In sum, low voltage reset circuit of the present invention breaches the limitation of conventional low reset circuit, its be a kind of meet fast powering-up demand and/or ultralow pressure under high reliability, the high precision low pressure reset circuit applied.This low voltage reset circuit only need increase a thyrite, just when system power supply power down is to ultralow pressure, can not discharge the reset signal of high level pulse mistakenly; And if increase a thyrite and a RC delay circuit simultaneously, form clamp circuit, then in the process of system fast powering-up, can correctly produce the reset signal of high level pulse.
The present invention does not almost increase chip area, power consumption and cost relative to prior art, just can improve circuit performance significantly and not introduce again other new defect.
Although the present invention with preferred embodiment openly as above, it is not that any those skilled in the art without departing from the spirit and scope of the present invention, can make possible variation and amendment for limiting the present invention.Therefore, every content not departing from technical solution of the present invention, any amendment done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all fall within protection range that the claims in the present invention define.
Claims (10)
1. a low voltage reset circuit, comprising: current source, the first resistance (R21), the second resistance (R22), the 3rd resistance (R3), the 4th resistance (R4), comparator (CMP) and thyrite (V-R);
Described current source, described first resistance (R21), described thyrite (V-R) and described second resistance (R22) are connected successively, are connected between supply voltage (VDD) and ground;
Described 3rd resistance (R3) and described 4th resistance (R4) are one another in series, and are connected between described supply voltage (VDD) and ground;
The negative input end of described comparator (CMP) is connected with the sampled voltage (VSAMP) extracted out between described 3rd resistance (R3) and described 4th resistance (R4); The positive input terminal of described comparator (CMP) is connected with the reference voltage (VREF) extracted out between described current source and described first resistance (R21); The output of described comparator (CMP) obtains the Output rusults (LVR_OUT) of described low voltage reset circuit;
Described current source system produces the ZTC electric current of a zero-temperature coefficient or the PTAT electric current of positive temperature coefficient by band gap reference main circuit, and then for generation of a stable described reference voltage (VREF).
2. low voltage reset circuit according to claim 1, is characterized in that, also comprises PNP triode, and its emitter and its collector electrode are connected between described second resistance (R22) and ground, and its base stage is also connected with ground.
3. low voltage reset circuit according to claim 1 and 2, is characterized in that, also comprises RC delay circuit, and described RC delay circuit comprises: time delay resistance (R0) and delay capacitor (C0);
Described time delay resistance (R0) and described delay capacitor (C0) are one another in series, be connected between described supply voltage (VDD) and ground, or be connected between the internal voltage output (OUT) of described band gap reference main circuit and ground;
The voltage controling end of described thyrite (V-R) is connected with the delays time to control voltage (VK) extracted out between described time delay resistance (R0) and described delay capacitor (C0).
4. low voltage reset circuit according to claim 3, is characterized in that, described thyrite (V-R) comprises NMOS tube (N1).
5. low voltage reset circuit according to claim 1 and 2, it is characterized in that, described thyrite (V-R) comprises PMOS (P1), the gate terminal of described PMOS (P1) connects the node extracting or produce in described band gap reference main circuit inside, or the gate terminal of described PMOS (P1) is directly connected with ground, controls described delays time to control voltage (VK).
6. low voltage reset circuit according to claim 4, it is characterized in that, described thyrite (V-R) also comprises PMOS (P1), described NMOS tube (N1) and described PMOS (P1) are one another in series, be connected between described first resistance (R21) and described second resistance (R22), the gate terminal of described PMOS (P1) connects the node extracting or produce in described band gap reference main circuit inside, or the gate terminal of described PMOS (P1) is directly connected with ground, controls described delays time to control voltage (VK).
7. the low voltage reset circuit according to claim 4 or 6, it is characterized in that, the implementation of described time delay resistance (R0) is the transistor of conventional, electric-resistance, NMOS type or PMOS type, and the gate terminal of the transistor of described NMOS or PMOS type adopts fixing voltage control or adopts the described internal node (VX) of described band gap reference main circuit to control.
8. low voltage reset circuit according to claim 7, is characterized in that, internal voltage output (OUT) 1.0V lower than described supply voltage (VDD) of described band gap reference main circuit.
9. low voltage reset circuit according to claim 8, it is characterized in that, described low voltage reset circuit also comprises: back biased diode (D0), its positive terminal is connected with described delays time to control voltage (VK), and its negative pole end is connected with the internal voltage output (OUT) of described supply voltage (VDD) or described band gap reference main circuit.
10. low voltage reset circuit according to claim 9, is characterized in that, described back biased diode (D0) is Schottky diode, the transistor of PMOS type or NMOS type.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110739944A (en) * | 2019-11-01 | 2020-01-31 | 西安中颖电子有限公司 | low-voltage reset circuit |
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| JPH1168539A (en) * | 1997-08-08 | 1999-03-09 | Oki Electric Ind Co Ltd | Power-on-reset circuit |
| CN102624369A (en) * | 2012-01-12 | 2012-08-01 | 苏州华芯微电子股份有限公司 | POR (Power-on Reset) circuit with variable reset point on basis of band gap reference source |
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| CN110739944A (en) * | 2019-11-01 | 2020-01-31 | 西安中颖电子有限公司 | low-voltage reset circuit |
| CN110739944B (en) * | 2019-11-01 | 2023-05-02 | 西安中颖电子有限公司 | Low-voltage reset circuit |
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Address after: 710075 Kam Road No. 70, Xi'an high tech Zone, Shaanxi Province, 2 Applicant after: XI'AN ZHONGYING ELECTRONIC CO., LTD. Address before: 710075 Xi'an Software Park, Xi'an Software Park, Han Yun Pavilion A202, Xi'an hi tech Zone, Xi'an City, Shaanxi Applicant before: XI'AN ZHONGYING ELECTRONIC CO., LTD. |
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