CN104716956B - PLL device and its method with circuit bandwidth calibration function - Google Patents
PLL device and its method with circuit bandwidth calibration function Download PDFInfo
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- CN104716956B CN104716956B CN201310676121.3A CN201310676121A CN104716956B CN 104716956 B CN104716956 B CN 104716956B CN 201310676121 A CN201310676121 A CN 201310676121A CN 104716956 B CN104716956 B CN 104716956B
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Abstract
The invention discloses a kind of PLL devices and its method with circuit bandwidth calibration function, wherein bearing calibration generates an output signal including the use of phase-locked loop circuit according to a reference signal and a feedback signal, modulation feedback factor makes feedback signal and reference signal unlock, detect phase difference between reference signal and feedback signal two effective crossover points calculate frequencies of oscillation, and the control parameter according to frequency of oscillation setting phase-locked loop circuit according to two effective crossover points.In this, feedback signal is related to output signal and has this feedback factor between feedback signal and output signal.
Description
Technical field
The present invention relates to a kind of alignment techniques of circuit bandwidth, having circuit bandwidth calibration function especially with regard to one kind
PLL device and its method.
Background technology
Phase-locked loop（Phase Lock Loop；PLL）It is the typical technology for synthesized frequency signal.All radio waves
Frequency tuning or digital product clock pulse control, all phase-locked loop can be used to carry out design frequency control loop.
In general, in phase-locked loop, there is given phase relation between input and the cyclical signal of output.Locking phase
The circuit structure in circuit includes mainly phase frequency detector（phase frequency detector；PFD）, charge pump（charge
pump）, loop filter（loop filter）, voltage controlled oscillator（voltage controlled oscillator；VCO）And
Feedback unit.
The general running of phase-locked loop is as follows.It is at the beginning the frequency acquisition stage, in the frequency acquisition stage, internal frequency meeting
Pursue to 90 the percent of target frequency.After internal frequency is differed with target frequency in 10, that is, enter frequency
Locked stage.In the Frequency Locking stage, phase acquisition is carried out, phase and Frequency Locking are finally then reached.Because of different lockings
Frequency has different control voltage, will reflect different loop control parameters for phase-locked loop, and then influence stability.
The circuit bandwidth of phase-locked loop（loop bandwidth）It can influence transient state response, whole phase noise
（integrated phase noise；IPN）, residual phase noise（relative phase noise；RPN）, intercarrier it is dry
It disturbs（inter-carrier interference；ICI）And other effectiveness parameters etc. of phase-locked loop.In order to reach phase-locked loop
Best efficiency, it is considerable that the circuit bandwidth of phase-locked loop, which is well controllled,.However, the circuit bandwidth set is usual
It can be influenced by factors such as semiconductor process variations, external module variation, power source change and environmental conditions and generate variation, and
Lead to circuit bandwidth drift.
Have been developed the alignment technique of many circuit bandwidths now, but its there are still have correcting mode to cannot respond to return every time
Road operation result limits the problems such as framework of applied phase-locked loop.
Invention content
In one embodiment, a kind of PLL device with circuit bandwidth calibration function, including：One phase-locked loop electricity
Road and a correcting circuit.
Phase-locked loop circuit generates a control voltage according to a reference signal and a feedback signal, and according to control voltage production
A raw output signal.Wherein, feedback signal is related to output signal and has a feedback system between feedback signal and output signal
Number.
Correcting circuit by modulation feedback factor so that feedback signal and reference signal unlock, according to reference signal and
Two effective crossover points of the phase difference between feedback signal calculate frequency of oscillation and adjust phase-locked loop electricity according to frequency of oscillation
The control parameter on road.
In one embodiment, a kind of bearing calibration of circuit bandwidth is applied to a phase-locked loop circuit.This bearing calibration packet
It includes：One output signal is generated according to a reference signal and a feedback signal using phase-locked loop circuit, modulation feedback factor makes instead
Feedback signal and reference signal unlock, detects two effective crossover points, the root of phase difference between reference signal and feedback signal
Frequency of oscillation is calculated according to two effective crossover points, and sets the control parameter of phase-locked loop circuit according to frequency of oscillation.
Wherein, feedback signal is related to output signal and has this feedback factor between feedback signal and output signal.
To sum up, PLL device and its method according to the present invention with circuit bandwidth calibration function are suitable for various
PLL device to provide accurate and digital circuit bandwidth correction, and is easy to be incorporated into one chip.According to this hair
The alignment technique of the bright PLL device and its method offer response corrections result with circuit bandwidth calibration function, to keep away
Exempt from the efficiency variation caused by the correlative factors such as environmental condition.
Description of the drawings
Fig. 1 is the schematic diagram according to the PLL device of first embodiment of the invention.
Fig. 2 is the flow chart according to the bearing calibration of the circuit bandwidth of first embodiment of the invention.
Fig. 3 is the sequence diagram of the reference signal of an embodiment, feedback signal, selection signal and switching signal.
Fig. 4 is the switching signal of an embodiment and the sequence diagram of phase difference.
Fig. 5 is the schematic diagram according to the PLL device of second embodiment of the invention.
Fig. 6 is the schematic diagram according to the PLL device of third embodiment of the invention.
Fig. 7 is the particular flow sheet of the step S290 of an embodiment.
Fig. 8 is the schematic diagram of the setup unit of an embodiment.
Fig. 9 is the schematic diagram of the setup unit of another embodiment.
Figure 10 is the reference signal of another embodiment and the sequence diagram of feedback signal.
Wherein, the reference numerals are as follows：
10 PLL devices
110 phase-locked loop circuits
111 phase frequency detectors
113 charge pumps
115 loop filters
117 voltage controlled oscillators
119 frequency eliminators
130 correcting circuits
131 control units
133 setup units
1331 multiplexers
1333 delta-sigma modulators
R1 resistance
C1 capacitances
C2 capacitances
Sr reference signals
Sf feedback signals
Sc controls signal
Ic controls electric current
Vc controls voltage
So output signals
SW is switched
Ns selection signals
EN switching signals
T0 time points
T1 time points
T2 time points
Pe phase differences
The effective crossover points of P1
The effective crossover points of P2
The effective crossover points of P3
T a cycles
T/2 half periods
Sb setting signals
S1 setting signals
S2 setting signals
S201 sets a control parameter with median
S210 comparison reference signals generate control signal with feedback signal and according to comparison result
S220 generates control electric current according to control signal
S230 generates control voltage according to control electric current
S240 generates output signal according to control voltage
S250 handles output signal to obtain feedback signal with a feedback factor
S260 modulation feedback factors
S270 detects two effective crossover points of the phase difference between reference signal and feedback signal
S280 calculates frequency of oscillation according to two effective crossover points
S290 sets the control parameter of phase-locked loop circuit according to frequency of oscillation
Whether S291 frequencies of oscillation are less than set frequency
S293 adjustment setting value resets control parameter according to this
Specific implementation mode
Referring to Fig.1, PLL device 10, including：One phase-locked loop circuit 110 and a correcting circuit 130.Correction electricity
Road 130 is applicable in correct the circuit bandwidth of phase-locked loop circuit 110.It should be noted that the phase-locked loop circuit 110 of the present embodiment can be
The circuit of close function is provided in current existing existing phase-locked loop or future development, and skilled person should be able to understand this
The framework and function mode of a little devices.
By taking single loop as an example, phase-locked loop circuit 110 includes phase frequency detector 111, charge pump 113, loop filter
115, voltage controlled oscillator 117 and frequency eliminator 119.
Phase frequency detector 111, charge pump 113, loop filter 115, voltage controlled oscillator 117 and frequency eliminator 119 are sequentially
It is electrically connected into primary Ioops.Loop filter 115 includes a resistance R1 and two capacitance C1, C2.The output electric property of charge pump 113
It is connected to the first end of resistance R1 and the first end of capacitance C2.Capacitance C1 is electrically connected at second end and the ground connection of resistance R1
Between.The second end of capacitance C2 is electrically connected to ground connection.
Fig. 2 is the flow chart according to the bearing calibration of the circuit bandwidth of first embodiment of the invention.With reference to Fig. 2, in initial
When can with median set a control parameter（Step S201）.Phase frequency detector 111 receives a reference signal Sr and a feedback letter
Number Sf.111 comparison reference signal Sr of phase frequency detector and feedback signal Sf, and control signal Sc is generated according to comparison result（Step
Rapid S210）.
Charge pump 113 generates control electric current Ic according to control signal Sc（Step S220）.Loop filter 115 is according to control
Electric current Ic generates control voltage Vc（Step S230）.In this, control electric current Ic can fill the capacitance C1 and C2 of loop filter 115
Electric discharge, thus generate control voltage Vc in the first end of resistance R1.
Voltage controlled oscillator 117 generates output signal So according to control voltage Vc（Step S240）.Frequency eliminator 119 is with a feedback
Coefficient（That is, divisor）Frequency elimination is carried out to output signal So to obtain feedback signal Sf, and feedback signal Sf is fed back to phase frequency inspection
Survey the input terminal of device 111（Step S250）.
Circuit bandwidth timing is being carried out, 130 modulation feedback factor of correcting circuit is so that feedback signal Sf and reference signal
Sr unlocks（Step S260）.
In some embodiments.Correcting circuit 130 includes a control unit 131, a switch SW and a setup unit 133.
Switch SW is connected across on resistance R1.Control unit 131 be electrically connected to the output of frequency eliminator 119, switch SW control terminal and set
The control terminal of order member 133.Setup unit 133 is electrically connected to the setting end of frequency eliminator 119.In correction course, control is single
Member 131 generates the running of selection signal Ns control setup units 133, and generates the running of switching signal EN control switches SW.
Collocation is with reference to Fig. 3, it is assumed that before correction executes, the divisor of frequency eliminator 119 is N1.Proceed by correction（Time point
t0）Afterwards, setup unit 133, which is changed the divisor of frequency eliminator 119 by N1 according to selection signal Ns, is set to N2, until time point t1 again
Divisor is switched back into N1 by N2.Wherein, N1 is not equal to N2.Wherein, time point t0 is different from time point t1.
It is connected according to switching signal EN in time point t2, switch SW（ON）Keep resistance R1 short-circuit, to cause to control voltage
Vc generates oscillation effect.In this, time point t1 is different from time point t2.But in some embodiments, time point t1 and time point
T2 also can be identical, i.e., divisor switches back into N1 while opening switch SW.
Then, collocation receives reference signal Sr and feedback signal Sf with reference to Fig. 4, control unit 131, and starts detection reference
The phase difference Pe of signal Sr and feedback signal Sf, to find out two effective crossover point P1, P2 in phase difference Pe（Or P1, P3）（Step
Rapid S270）.
In this, the time gap between the 1st effective crossover point P1 and the 2nd effective crossover point P2 is half period T/
2, and the time gap between the 1st effective crossover point P1 and the 3rd effective crossover point P3 is a cycle T, that is, two hand over
Time gap between more putting can be the positive integer times of half period T/2.Control unit 131 is based on this and is got over the 1st effectively friendship
Point P1 and the 2nd effective crossover point P2 calculates phase difference Pe with the 1st effective crossover point P1 and the 3rd effective crossover point P3
Frequency of oscillation（Step S280）.
Then, control unit 131 sets the control parameter of phase-locked loop circuit 110 according to frequency of oscillation, such as：Charge pump
113 charging and discharging currents（As shown in Figure 1）, in loop filter 115 capacitance C1 filtering capacitance（As shown in Figure 5）Or it is voltage-controlled
The gain of oscillator 117（As shown in Figure 6）（Step S290）.
In some embodiments, before correction, control unit 131 first resets a control using a median as setting signal Sb
Parameter processed（Step S201）.
In step S290, with reference to Fig. 7, control unit 131 compares frequency of oscillation and a set frequency, to judge oscillation frequency
Whether rate is less than set frequency（Step S291）.
When frequency of oscillation is less than set frequency, indicate that the transient response of current loop bandwidth is too slow, at this time control unit
131 correspond to adjustment setting value and export the setting signal Sb of corresponding setting value, to reset a control parameter（Step S293）.It resets
Afterwards, it then re-executes（It returns to step S210 and connects execution）To reaffirm correction result.Therefore, by repeatedly executing step repeatedly
Rapid S210 to step S290 obtains desired circuit bandwidth to cause frequency of oscillation close or be equal to set frequency.
In some embodiments, number is executed repeatedly and is preferably 5 times.
When frequency of oscillation is not less than set frequency, indicate that the transient response of current loop bandwidth meets expection, this time control
Unit 131 processed completes correction program.In some embodiments, when transient response meets it is expected when, can also execute repeatedly repeatedly,
To determine that this meets expected transient response as stabilization.
Although the set frequency of previous embodiment is presented with single numerical value, however, the present invention is not limited thereto.In some embodiments
In, set frequency can be the given area being made of the first numerical value and second value（Wherein the first numerical value is more than the second number
Value）.In step S291, then by frequency of oscillation compared with given area.When frequency of oscillation is more than the first numerical value, expression is current to return
The transient response of road bandwidth is too fast.When being less than second value when frequency of oscillation, indicate that the transient response of current loop bandwidth is too slow.
When frequency of oscillation is fallen between the first numerical value and second value, the transient response of expression current loop bandwidth meets expection.When temporary
When state response is too fast or too slow, control unit 131 can all correspond to adjustment setting value to reset control parameter.
For setting the charging and discharging currents of charge pump 113, control unit 131 is with the binary bit setting signal Sb of 5 bits
Set charge pump 113.
Control unit 131 first exports the setting signal Sb of " 10000 ", and the electric current of charge pump 113 is set as median
（Step S201）.Counted frequency of oscillation, which is counted, when control unit 131 is less than set frequency（Step S291）When, control unit 131
The setting signal Sb of output corresponding " 11000 ", to reset the electric current of charge pump 113（Step S293）.
In some embodiments, frequency eliminator 119 can perform integer frequency elimination, i.e. divisor N1, N2 is integer.With reference to Fig. 8, setting
Unit 133 includes multiplexer 1331.Two inputs of multiplexer 1331 receive the setting signal S1 of corresponding divisor N1 and right respectively
Answer the setting signal S2 of divisor N2.The control terminal of multiplexer 1331 is electrically connected control unit 131, and multiplexer 1331 is defeated
Outlet is electrically connected frequency eliminator 119.Multiplexer 1331 exports one in setting signal S1, S2 extremely according to selection signal Ns selections
The control terminal of frequency eliminator 119, to determine the divisor of frequency eliminator 119 for N1 or N2.
In some embodiments, frequency eliminator 119 can perform score frequency elimination, i.e. divisor N1, N2 is score.With reference to Fig. 9, setting
Unit 133 includes multiplexer 1331 and delta-sigma modulator（sigma delta modulation；SDM）1333.Multiplexer
1331 two input terminals are electrically connected delta-sigma modulator 1333.The control terminal of multiplexer 1331 is electrically connected control unit
131, and the output end of multiplexer 1331 is electrically connected frequency eliminator 119.
Delta-sigma modulator 1333 provides the setting signal of the setting signal S1 and corresponding divisor N2 of corresponding divisor N1
S2 to multiplexer 1331 two input terminals.Multiplexer 1331 is defeated by one of setting signal S1, S2 according to selection signal Ns selections
Go out to the control terminal of frequency eliminator 119, to determine the divisor of frequency eliminator 119 for N1 or N2.
Under the feedback of score frequency elimination, since the edge of feedback signal Sf can be shaken, as shown in Figure 10.In this,
In step S270, control unit 131 then detects crossover point to obtain each effective crossover point in a manner of over sampling.In other words, it controls
When unit 131 detects the crossover point in phase difference Pe, it can start to calculate the crossover point occurred in succession（That is, adjacent two crossover point
Less than a given time）Quantity.When detecting the crossover point of given amount occurred in succession, control unit 131 then judges
One effective crossover point exists.In this, given amount is preferably 10.
In other words, when applying in integer type PLL device 10, control unit 131 detects appointing in phase difference Pe
One crossover point is an effective crossover point.When applying in fractional-type PLL device 10, control unit 131 detects phase
When the quantity of the crossover point occurred in succession in potential difference Pe reaches given amount, one effective crossover point of judgement exists.
Although previous embodiment is illustrated with single loop PLL device, however, the present invention is not limited thereto.At some
In embodiment, present invention can apply to multi-loop phase-locked loop devices.In this, it is assumed that multi-loop phase-locked loop device includes first
Road and the second tunnel, a power switch are then coupled between the second tunnel and supply power supply, and make resistance R1 short circuits without setting
Switch SW.When being corrected, power switch is cut off according to switching signal（Off）, to close the running on the second tunnel.At this point,
Then the running of the first via connects such as single loop PLL device and is corrected program.
To sum up, PLL device and its method according to the present invention with circuit bandwidth calibration function are suitable for various
PLL device to provide accurate and digital circuit bandwidth correction, and is easy to be incorporated into one chip.According to this hair
The alignment technique of the bright PLL device and its method offer response corrections result with circuit bandwidth calibration function, to keep away
Exempt from the efficiency variation caused by the correlative factors such as environmental condition.
Although the present invention is disclosed as above with embodiment above-mentioned, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore the patent of the present invention is protected
Protecting range must be depending on applying for a patent subject to right claimed range institute defender appended by this specification.
Claims (24)
1. a kind of PLL device with circuit bandwidth calibration function, including：
One phase-locked loop circuit, to generate a control voltage according to a reference signal and a feedback signal, and according to the control
Voltage generates an output signal, and the wherein feedback signal is related to the output signal and between the feedback signal and the output signal
With a feedback factor；And
One correcting circuit, to by the modulation feedback factor so that the feedback signal and the reference signal unlock, basis
Two effective crossover points of the phase difference between the reference signal and the feedback signal calculate a frequency of oscillation and according to the oscillation
Frequency adjusts the control parameter of the phase-locked loop circuit；
Wherein, which includes：
Loop filter, including：
One resistance, to provide the control voltage；And
One capacitance is electrically connected between the resistance and ground connection；And
Wherein the correcting circuit includes：
One control unit, to be shaken according to two effective crossover point calculating of the phase difference between the reference signal and the feedback signal
It swings frequency and the control parameter is adjusted according to the frequency of oscillation；
One switch, is connected across on the resistance；And
One setup unit, to set the feedback factor；
Wherein, for the control unit to control the setup unit modulation feedback factor, then controlling the switch keeps the resistance short
Road, to cause the control voltage to generate oscillation effect.
2. the PLL device with circuit bandwidth calibration function, wherein two effective crossover point as described in claim 1
Between at a distance of half period positive integer times time gap.
3. the PLL device with circuit bandwidth calibration function, the wherein phase-locked loop circuit as described in claim 1
Further include a phase frequency detector, a charge pump, a voltage controlled oscillator and a frequency eliminator；The phase frequency detector, is somebody's turn to do at the charge pump
Loop filter, the voltage controlled oscillator and the frequency eliminator are sequentially electrically connected into primary Ioops.
4. the PLL device with circuit bandwidth calibration function as claimed in claim 3, wherein：
The phase frequency detector receives the reference signal and the feedback signal, which compares the reference signal and the feedback
Signal, and a control signal is generated according to comparison result；
The charge pump generates a control electric current according to the control signal, which generates the control according to the control electric current
Voltage.
5. the PLL device with circuit bandwidth calibration function as claimed in claim 3, wherein：
The voltage controlled oscillator generates the output signal according to the control voltage.
6. the PLL device with circuit bandwidth calibration function as claimed in claim 3, wherein：
The frequency eliminator carries out frequency elimination to obtain the feedback signal with the feedback factor to the output signal, and the feedback signal is returned
It is fed to the input terminal of the phase frequency detector.
7. the PLL device with circuit bandwidth calibration function as described in claim 1, wherein：
After one time point t0, which, which is changed the feedback factor by N1 according to a selection signal, is set to N2；In the time
The feedback factor is switched back into N1 by point t1 by N2；Wherein, N1 is the feedback factor before correction executes, and N1 is not equal to N2, time
Point t0 is different from time point t1；
In a time point t2, which is connected according to a switching signal.
8. the PLL device with circuit bandwidth calibration function as claimed in claim 7, wherein time point t1 is different
In time point t2；Alternatively, time point t1 is identical as time point t2.
9. the PLL device with circuit bandwidth calibration function as described in claim 1, wherein before correction executes,
The control unit first resets the control parameter using a median as setting signal.
10. the PLL device with circuit bandwidth calibration function as claimed in claim 9, wherein the control unit ratio
Compared with the frequency of oscillation and a set frequency, to judge whether the frequency of oscillation is less than the set frequency：When the frequency of oscillation is less than
When the set frequency, which adjusts a setting value and exports corresponding setting signal, to reset the control parameter.
11. the PLL device with circuit bandwidth calibration function as claimed in claim 10, wherein the set frequency is
One single numerical value or a given area.
12. the PLL device with circuit bandwidth calibration function as described in claim 1, the wherein feedback factor are whole
Number and the setup unit include：
One multiplexer is electrically connected the control unit and the phase-locked loop circuit.
13. the PLL device with circuit bandwidth calibration function as described in claim 1, the wherein feedback factor are point
Number and the setup unit include：
One multiplexer is electrically connected the control unit and the phase-locked loop circuit；And
One trigonometric integral adjuster, is electrically connected the multiplexer.
14. the PLL device with circuit bandwidth calibration function as described in claim 1, the wherein control parameter are to fill
At least one of the gain of discharge current, filtering capacitance and voltage controlled oscillator.
15. a kind of bearing calibration of circuit bandwidth is applied to a phase-locked loop circuit, including：
One control voltage is generated according to a reference signal and a feedback signal using the phase-locked loop circuit, and according to control electricity
Pressure generates an output signal, and wherein the feedback signal is related to the output signal and has between the feedback signal and the output signal
There is a feedback factor；
The modulation feedback factor makes the feedback signal unlock with the reference signal；
Detect two effective crossover points of the phase difference between the reference signal and the feedback signal；
A frequency of oscillation is calculated according to two effective crossover point；And
The control parameter of the phase-locked loop circuit is set according to the frequency of oscillation；
Wherein, which includes loop filter；The loop filter includes：One resistance, to provide the control
Voltage processed, and, a capacitance is electrically connected between the resistance and ground connection；The bearing calibration further includes：
Control, which is connected across an ohmically switch, makes the resistive short, to cause the control voltage to generate oscillation effect.
16. the bearing calibration of circuit bandwidth as claimed in claim 15, wherein：
After one time point t0, the feedback factor is changed by N1 according to a selection signal and is set to N2；It is in a time point t1, this is anti-
Feedforward coefficient switches back into N1 by N2；Wherein, N1 is the feedback factor before correction executes, and N1 is not equal to N2, and time point, t0 was different from
Time point t1；
In a time point t2, which is connected according to a switching signal.
17. the bearing calibration of circuit bandwidth as claimed in claim 16, wherein time point t1 is different from time point t2；
Alternatively, time point t1 is identical as time point t2.
18. the bearing calibration of circuit bandwidth as claimed in claim 15, wherein before correction executes, first made with a median
The control parameter is reseted for setting signal.
19. the bearing calibration of circuit bandwidth as claimed in claim 18, wherein compare the frequency of oscillation and a set frequency,
To judge whether the frequency of oscillation is less than the set frequency：When the frequency of oscillation is less than the set frequency, a setting value is adjusted
And corresponding setting signal is exported, to reset the control parameter.
20. the bearing calibration of circuit bandwidth as claimed in claim 19, wherein the set frequency is a single numerical value or one
Given area.
21. the bearing calibration of circuit bandwidth as claimed in claim 15, at a distance of half week wherein between two effective crossover point
The positive integer times time gap of phase.
22. the bearing calibration of circuit bandwidth as claimed in claim 15, wherein respectively the detecting step of effective crossover point includes：
Multiple crossover points of the phase difference between the reference signal and the feedback signal are detected in a manner of over sampling to be somebody's turn to do
Effective crossover point.
23. the bearing calibration of circuit bandwidth as claimed in claim 15, the wherein feedback factor are in the phase-locked loop circuit
A frequency eliminator divisor.
24. the bearing calibration of circuit bandwidth as claimed in claim 15, the setting procedure of the wherein control parameter include：
The increasing of the charging and discharging currents, filtering capacitance and voltage controlled oscillator of the phase-locked loop circuit is adjusted according to the frequency of oscillation
At least one of benefit.
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| US7995630B2 (en) * | 2008-04-01 | 2011-08-09 | Rakuljic George A | High performance tunable lasers utilizing optical phase-locked loops |
| US9401722B2 (en) * | 2011-06-20 | 2016-07-26 | Texas Instruments Incorporated | Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency |
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