KR101780630B1 - Sub-sampling phase locked loop based spread spectrum clock generator and method the same - Google Patents

Sub-sampling phase locked loop based spread spectrum clock generator and method the same Download PDF

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KR101780630B1
KR101780630B1 KR1020150177266A KR20150177266A KR101780630B1 KR 101780630 B1 KR101780630 B1 KR 101780630B1 KR 1020150177266 A KR1020150177266 A KR 1020150177266A KR 20150177266 A KR20150177266 A KR 20150177266A KR 101780630 B1 KR101780630 B1 KR 101780630B1
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ref
reference clock
frequency
controlled oscillator
output
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KR1020150177266A
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Korean (ko)
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KR20170069710A (en
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김철우
황세욱
배상근
이연호
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고려대학교 산학협력단
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

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Abstract

The spread spectrum clock generator of the present invention includes a voltage controlled oscillator, a subsampling phase locked loop for fixing the phase by subsampling a high frequency signal output from the voltage controlled oscillator at a reference clock (F REF ) period; A frequency locked loop for fixing the frequency of the voltage controlled oscillator output signal to the frequency of the reference clock (F REF ); And a control voltage regulator for regulating a control voltage of the voltage controlled oscillator based on a control signal generated by pulse width modulation of the reference clock (F REF ) to spread the spectrum of the voltage controlled oscillator output signal . Thus, the present invention has the advantage of being able to precisely adjust even a small range of frequencies. This also has the advantage of maximizing the jitter reduction efficiency and effectively reducing electromagnetic interference (EMI).

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a spread spectrum clock generator based on a sub-sampling phase locked loop circuit,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum clock generator (SSCG), and more particularly, to a spread spectrum clock generator based on a sub-sampling phase locked loop (SSPLL) and a method thereof.

A phase locked loop (PLL) generates an oscillation signal having a fixed frequency in response to an externally input reference clock signal. The generated oscillation signal is supplied to an operation clock . In addition, the in-band phase noise and jitter of the clock determine the performance of the overall system. The subsampling phase-locked loop is a circuit that achieves low phase noise and jitter performance by removing the divider by noting that the internal divider adds and amplifies noise.

However, if the spectral power of a signal is concentrated on only one frequency component, electromagnetic interference (EMI) may be generated, which may affect other peripheral circuits, and further, the entire system may fail. That is, a high-frequency signal having a high energy (i.e., a clock signal) affects the surrounding system and causes malfunction. To reduce this effect, the spread spectrum clock generator (SSCG) is a method of spreading the spectrum power to surrounding frequency components to lower the power of the highest frequency components.

However, this spread spectrum clock generator (SSCG) modulates the frequency of the phase locked loop (PLL), resulting in additional jitter, which is increasingly problematic in high-speed serial communications (eg, 10 Gbps or faster) ≪ / RTI >

As a result, attempts have been made to implement a spread spectrum clock generator (SSCG) based on a subsampling phase locked loop (SSPLL), which is basically known to have significantly less jitter.

However, in the case of a conventional spread spectrum clock generator (SSCG), it is common to make a profile by changing the division ratio of the phase locked loop using a sigma-delta modulator (SDM) , And the subsampling phase locked loop (SSPLL) can not apply this method. This is because, in the subsampling phase locked loop (SSPLL), the noise of the charge pump is multiplied by N 2 , eliminating the frequency divider to reduce jitter.

Accordingly, in the conventional spread spectrum clock generator (SSCG) based sub-sampling phase locked loop (SSPLL) implementation, frequency modulation has been a problem. For example, since a sigma-delta modulator (SDM) can not be applied to a spread spectrum clock generator (SSCG) in the past, a clock generator having a structure capable of accurately changing even a small range of frequencies has not been realized.

Korea Registered Patent Registration No. 10-1135872 (Spread Spectrum Clock Generator, Silicon Works Inc., April 19, 2012)

Accordingly, the present invention provides a spread spectrum clock generator (SSCG) based on a subsampling phase locked loop circuit (SSCG) that effectively reduces electromagnetic interference noise (EMI) by pulse width modulation in a high-speed wired transmission interface .

The present invention also relates to a sub-sampling phase locked loop circuit (SSPLL) -based spread spectrum clock generator (SSCG), which can precisely change even a small range of frequencies to achieve a sub-sampling phase locked loop circuit (SSPLL) Based spread spectrum clock generator (SSCG) and method therefor.

In order to achieve the above object, a spread spectrum clock generator provided in the present invention includes a voltage controlled oscillator, and a high frequency signal output from the voltage controlled oscillator is subsampled with a reference clock (F REF ) Subsampling phase locked loop; A frequency locked loop for fixing the frequency of the voltage controlled oscillator output signal to the frequency of the reference clock (F REF ); And a control voltage regulator for regulating a control voltage of the voltage controlled oscillator based on a control signal generated by pulse width modulation of the reference clock (F REF ) to spread the spectrum of the voltage controlled oscillator output signal .

Advantageously, the subsampling phase locked loop comprises a voltage controlled oscillator; A loop filter that includes a plurality of capacitors and adjusts a control voltage of the voltage controlled oscillator based on an amount of charge charged / discharged to / from the capacitor; A sampler for sub-sampling a high frequency signal output from the voltage controlled oscillator at a cycle of a reference clock (F REF ); A first charge pump for controlling charging / discharging of the capacitors included in the loop filter based on the sampling result; And a pulser that controls an operation time of the first charge pump based on the reference clock (F REF ) period.

Advantageously, the spread spectrum clock generator further comprises a frequency divider dividing the frequency of the voltage controlled oscillator output signal into multiple and feeding the divided signal (F DIV ) back to the frequency locked loop and the control voltage regulator can do.

Preferably, the frequency locked loop compares the reference clock F REF with a voltage-controlled oscillator output signal F DIV divided at the frequency divider and outputs a control signal FAST or SLOW for frequency fixing Detector; And a second charge pump for controlling charging / discharging of the capacitors included in the loop filter based on the control signal FAST or SLOW output from the frequency detector.

Preferably, the frequency detector is the reference clock (F REF) being of a predetermined pulse width around the falling edge, the pulse width of the reference clock (F REF) pulse width narrower than the reference pulse (F REF1 of A reference pulse generator for generating a reference pulse; And the reference clock (F REF) and the reference pulse (F REF1) and receives the output signal (F DIV) of said frequency divider the voltage-controlled oscillator as an input, the output signal (F DIV) of said frequency divider the voltage-controlled oscillator Input frequency detector that outputs the control signal FAST or SLOW for the frequency fixing based on the reference clock F REF and the state value of the reference pulse F REF1 when the reference clock F REF1 is triggered have.

Preferably, the 3-input frequency detector comprises a first and a second frequency divider for outputting a current value and a previous value of the reference clock (F REF ) when the output signal (F DIV ) of the frequency- D-flip flop; Third and fourth D flip-flops for outputting a current value and a previous value of the reference pulse (F REF1 ) when the output signal (F DIV ) of the divided voltage controlled oscillator is triggered; A fifth and a sixth D flip-flop for outputting the two values when the current value and the previous value of the reference clock signal (F REF ) output from the first and second D flip-flops differ from each other; A seventh and an eighth D flip-flop outputting the two values when the current value and the previous value of the reference pulse (F REF1 ) output from the third and fourth D flip-flops differ from each other; And first and second control signal determination units respectively connected to output terminals of the fifth and sixth D-flip flops and output terminals of the seventh and eighth D-flip flops.

Preferably, the 3-input frequency detector includes a first EX-OR gate for identifying whether the current value of the reference clock (F REF ) output from the first and second D flip-flops is the same as or different from the previous value ; And a second EX-OR gate for identifying whether or not the current value of the reference pulse (F REF1 ) output from the third and fourth D flip-flops is the same as or different from the previous value.

Preferably, the control voltage regulator includes a plurality of switches, each of which controls charging and discharging of the capacitors included in the loop filter based on an adjustment signal for controlling ON / OFF of each of the plurality of switches, 3 charge pump; A third order sigma delta modulator for modulating the reference clock (F REF ) and outputting an adjustment signal for adjusting on / off of each of the switches of the third charge pump as a result; A first frequency divider dividing the reference clock signal (F REF ) to determine a modulation frequency of the third order sigma delta modulator; And a modulation width determiner for determining a modulation width of the third order sigma delta modulator based on the reference clock F REF and the voltage controlled oscillator output signal F DIV divided by the frequency divider.

Preferably, the modulation width determination unit includes: a second frequency divider that divides the reference clock signal (F REF ) by two; The second frequency divider with the reference clock (F REF / 2) and the division voltage from the frequency divider controlled oscillator output signal (F DIV) the two of the voltage controlled oscillator output signal (F DIV) frequency division in the frequency divider by comparing frequency divider A frequency detector for outputting a control signal for fixing the reference clock signal to a reference clock signal (F REF / 2); And an SDM input array generator for outputting n array values for determining the modulation width of the third order sigma delta modulator based on the control signal output from the frequency detector.

Preferably, the frequency detector is the 2-frequency division of the reference clock (F REF / 2) polling the edge around the back of a predetermined pulse width, the pulse width of the second dispensed reference clock (F REF / 2) A reference pulse generator for generating a reference pulse F REF1 narrower than the pulse width of the reference pulse F REF1 ; And an output signal (F DIV ) of the divided voltage-controlled oscillator, wherein the divided reference clock (F REF / 2), the reference pulse (F REF1 ) when the signal (F DIV) is triggered wherein the second frequency divider reference clock (F REF / 2) and a three-input frequency on the basis of the state value of the reference pulse (F REF1) outputs a control signal for the fixed frequency Detector.

Preferably, the 3-input frequency detector outputs a current value and a previous value of the divided reference clock (F REF / 2) when the output signal (F DIV ) of the divided voltage controlled oscillator is triggered An eleventh and twelfth D-flip flops; A thirteenth and fourteenth D flip-flops for outputting a current value and a previous value of the reference pulse (F REF1 ) when an output signal (F DIV ) of the divided voltage controlled oscillator is triggered; The fifteenth and sixteenth D-flip-flops, which output the two values when the present value and the previous value of the two divided reference clocks (F REF / 2) output from the eleventh and twelfth D- ; A seventeenth and eighteenth D flip-flops for outputting the two values when the current value and the previous value of the reference pulse (F REF1 ) output from the thirteenth and fourteenth D-flip flops differ from each other; And an eleventh and twelfth control signal determination sections respectively connected to output terminals of the fifteenth and sixteenth D-flip flops and output terminals of the seventeenth and eighteenth D-flip flops.

Preferably, the 3-input frequency detector comprises: a divider for comparing the current value of the divided reference clock F REF / 2 output from the 11th and 12th D flip-flops with the previous value, 11 EX-OR gate; And a twelfth EX-OR gate for discriminating whether or not the current value of the reference pulse (F REF1 ) output from the thirteenth and fourteenth D-flip flops is the same as or different from the previous value.

In order to achieve the above object, a spread spectrum clock generating method according to the present invention is a spread spectrum clock generating method based on a sub-sampling phase locked loop circuit including a voltage controlled oscillator and a loop filter, Modulating a reference clock (F REF ) of the subsampling phase locked loop circuit with a third-order sigma delta modulation scheme; And adjusting the output voltage of the loop filter based on the control signal output as the modulation result.

Advantageously, said modulating comprises: determining a modulation frequency based on a reference clock (F REF ) of said subsampling phase locked loop circuit; And determining a modulation width based on the reference clock (F REF ) and the voltage controlled oscillator output signal (V VCO ) of the subsampling phase locked loop circuit.

Preferably, the loop filter output voltage adjustment step may directly control the charge / discharge of the capacitors constituting the loop filter based on the control signal output as a result of the modulation.

The spread spectrum clock generator and method of the present invention is a spread spectrum clock generator based on a subsampling phase locked loop circuit in which a loop voltage is controlled by a connection structure of a third order sigma delta modulator and a charge pump, By controlling the control voltage of the voltage controlled oscillator, it is possible to precisely control even a small range of frequencies. This also has the advantage of maximizing the jitter reduction efficiency and effectively reducing electromagnetic interference (EMI).

1 is a circuit diagram of a spread spectrum clock generator based on a subsampling phase locked loop circuit according to an embodiment of the present invention.
2 is a schematic block diagram of a frequency detector according to an embodiment of the present invention.
3 is a timing diagram illustrating signals generated and operated in a frequency detector according to an embodiment of the present invention.
4 is a schematic block diagram of a 3-input frequency detector according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a connection structure between a third order sigma delta modulator and a charge pump according to an embodiment of the present invention. Referring to FIG.
6 is a timing diagram illustrating input / output signals of a third order sigma delta modulator in the structure illustrated in FIG.
7 is a timing diagram showing a relationship between a frequency and a phase difference of a spread spectrum clock generator according to an embodiment of the present invention.
8 is a flowchart illustrating a process flow for a spread spectrum clock generating method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings, which will be described in detail to facilitate a person skilled in the art to which the present invention pertains. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification. And a detailed description thereof will be omitted to omit descriptions of portions that can be readily understood by those skilled in the art.

Throughout the specification and claims, where a section includes a constituent, it does not exclude other elements unless specifically stated otherwise, but may include other elements.

1 is a circuit diagram of a spread spectrum clock generator based on a subsampling phase locked loop circuit according to an embodiment of the present invention.

Referring to FIG. 1, a spread spectrum clock generator (SSCG) based on a sub-sampling phase locked loop (SSPLL) according to an embodiment of the present invention includes a sub-sampling phase locked loop (SSPLL) 110, a frequency locked loop (FLL) 120, a control voltage regulator 130, and a frequency divider (MMD) 140.

The subsampling phase locked loop circuit (SSPLL) 110 includes a sampler 111, a pulser 112, a charge pump 113, a loop filter 114, (VCO) 115, and serves to fix the phase by sub-sampling a high frequency signal output from the voltage controlled oscillator (VCO) 115 at a reference clock (F REF ) cycle . For this purpose, the sampler 111 outputs feedback of the high frequency signal output from the voltage controlled oscillator (VCO) 115 and its inverted signals (for example, F VCO and F VCOB ) to the reference clock F REF) to give the sub-sampling (sub sampling), and a voltage controlled oscillator (VCO) (115) output signal (F VCO) and an inverted signal (F VCOB) and the reference clock (direct current the phase difference and F REF) each Value (SAMP, SAMN). The pulser 112 controls the operation time of the charge pump 113 based on the reference clock (F REF ) period. That is, the pulser 112 controls the switches constituting the charge pump 113 to be turned on / off regardless of the phase difference (SAMP, SAMN). The charge pump 113 controls charging / discharging of the capacitors C1 and C2 included in the loop filter 114 so that the phase differences SAMP and SAMN become equal to each other. This is for phase locking the phase difference (SAMP, SAMN) at the same point. The loop filter 114 includes a plurality of capacitors C1 and C2 and adjusts the control voltage of the voltage controlled oscillator (VCO) 115 based on the amount of charges charged to or discharged from the capacitors C1 and C2.

The frequency locked loop (FLL) 120 fixes the frequency of the output signal of the voltage controlled oscillator (VCO) 115 to the frequency of the reference clock (F REF ). In particular, it is preferred that the frequency locked loop circuit (FLL) 120 operates prior to the subsampling phase locked loop circuit (SSPLL) 110 and only operates for a certain period until the frequency is fixed. For this purpose, the frequency locked loop circuit (FLL) 120 includes a frequency detector (FD) 200 and a charge pump (CP) The frequency detector (FD) 200 compares the divided voltage controlled oscillator output signal (F DIV ) via a reference clock (F REF ) and a frequency divider (MMD) (140) Signal (FAST or SLOW). A schematic block diagram of this frequency detector (FD) 200 is illustrated in FIG. A detailed description of the configuration and operation of the frequency detector (FD) 200 will be given with reference to Fig. On the other hand, the charge pump (CP) 121 amplifies the charge / discharge of the capacitors C1 and C2 included in the loop filter 114 based on the control signal (FAST or SLOW) output from the frequency detector (FD) And controls the discharge. This is to acquire the frequency at the point where the control signal (FAST or SLOW) is equal.

The control voltage regulator 130 generates a signal for directly controlling the control voltage of the voltage controlled oscillator 115 to spread the spectrum of the voltage controlled oscillator (VCO) 115 output signal (F OUT ). This is because the characteristics of the subsampling phase locked loop (SSPLL) 110 from which the frequency divider is removed require the control voltage VCO 115 of the voltage controlled oscillator 115 to diffuse the spectrum of the output signal F OUT of the voltage controlled oscillator Because it has to be controlled directly. In particular, the control voltage regulator 130 regulates the control voltage of the voltage controlled oscillator (VCO) 115 based on the control signal generated by the pulse width modulation of the reference clock F REF . This is to enable finer changes to be reflected in the control voltage control. For this, the control voltage regulator 130 includes a plurality of frequency dividers 131 and 133, a frequency detector (FD) 200, a sigma delta modulation input decision unit (SDM input decision) 132) and, a third order sigma-delta modulator (3 rd order SDM) (134 ) , and a charge pump (charge pump, CP) (135 ).

The charge pump (CP) 135 includes a plurality of switches, and the capacitors C1, C2, and C3 included in the loop filter 114, based on the adjustment signals for controlling ON / OFF of each of the plurality of switches, C2, respectively. This is to generate a Spread Spectrum Clock (SSC). The third order sigma-delta modulator (3 rd order SDM) (134 ) is controlled to control the switch, each of the on / off included in the reference clock modulation, the (F REF), and as a result the charge pump (CP) (135) to And outputs a signal. The dispenser (DIVIDER) (133) determines the modulation frequency of the reference clock by a frequency divider (F REF) 3 tea order sigma-delta modulator (3 rd order SDM) (134 ). In the example of Figure 1, a frequency divider (DIVIDER) (133) the reference clock (F REF) by frequency division to and generating frequency (F 30kHz) of 30kHz, the frequency (F 30kHz) a third order sigma-delta modulator (3 rd order SDM (134).

Meanwhile, another frequency divider (DIV2) 131, a frequency detector (FD) 200, and a sigma delta modulation input decision unit (SDM input decision) (3 rd order SDM) 134 based on an output signal (F DIV ) of a voltage controlled oscillator (VCO) 115 that is divided via a frequency divider (F REF ) and a frequency divider (MMD) ) Is determined. The divider DIV2 131 divides the reference clock F REF by two and applies the frequency to the frequency detector FD 200. The frequency detector FD 200 divides the frequency divider DIV2 131 And outputs a control signal for fixing the frequency with reference to the output signal of the inverter That is, the frequency detector (FD) 200 includes a voltage controlled oscillator (VCO) 130 divided by a reference frequency (F REF / 2) divided by two in a frequency divider (DIV2) 131 and a frequency divider (MMD) (115) output signal (F DIV ) and outputs the divide-by-2 voltage-controlled oscillator (VCO) 115 output signal (F DIV ) via the frequency divider (MMD) F REF / 2). Sigma-delta modulating the input array generator (Sigma Delta Modulation input decision, SDM input decision) (132) includes a frequency detector (FD) (200) to the third order sigma-delta modulator (3 rd order SDM) based on the control signal output from the N < / RTI >

For example, when it is desired to set the modulation width of the spread spectrum clock to 20 ns, a 50 MHz reference clock (F REF ) having one period of 20 ns is input, and the frequency divider (DIV2) To the frequency detector (FD) (200). The frequency detector (FD) 200 applies a 20-bit sigma delta modulation input array (SDM [19: 0]) by applying a SAR (Success Approximate Register) algorithm to determine the modulation width in a range where the phase difference does not exceed 20 ns ]) Are derived. To do this, the frequency detector (FD) 200 first compares the output of 20'h80001 with 20 ns and outputs 1 if the output of 20'h80001 is greater than 20 ns, otherwise outputs 0, 20`h40001, 20`h20001, ... , The output value is compared with 20 ns, and 1 or 0 is output according to the result. The output values are stored in order from the MSB to the LSB of the 20-bit sigma-delta modulation input array (SDM [19: 0]). This process is repeated 20 times to derive all the values corresponding to the 20-bit sigma delta modulation input array (SDM [19: 0]). The Sigma Delta Modulation Input Decision ) 132 transfers the value to a third order sigma delta modulator (3 rd order SDM) The third order sigma-delta modulator (3 rd order SDM) (134 ) is for generating and outputting a pulse value (UPB SDM, DN SDM) to be applied to the charge pump (CP) (135) on the basis of the value of the example Fig. Lt; / RTI >

At this time, the modulation width affects the jitter characteristics and the EMI characteristics. The jitter characteristics are improved as the modulation width is reduced, but the EMI improvement effect is reduced when the modulation width is too narrow. Therefore, it is important to determine the modulation width at an appropriate level. In the above description, the case where the modulation width is 20 ns is described as an example. However, this is a preferable example, and the modulation width is not limited to 20 ns in the present invention. The frequency of the reference clock F REF , the frequency division ratio of the frequency divider 131 and the Sigma Delta Modulation input decision unit (SDM input decision) 132 ) Are preferably linked together.

The MMD 140 divides the output frequency of the voltage controlled oscillator (VCO) 115 into a plurality of signals and outputs the divided signals F DIV to a frequency locked loop (FLL) And the control voltage regulator 130, respectively. More precisely, to the frequency detector (FD) 200 included in the frequency locked loop (FLL) 120 and the control voltage regulator 130. This is to change the output frequency of the voltage controlled oscillator (VCO) 115 to a frequency band that can be processed by the frequency detector (FD) 200.

2 is a schematic block diagram of a frequency detector according to an embodiment of the present invention. That is, FIG. 2 is a schematic block diagram of the frequency detector (FD) 200 illustrated in FIG. Referring to FIGS. 1 and 2, a frequency detector (FD) 200 includes a reference pulse generator (RP_GEN) 210 and a 3-input frequency detector 220 do.

The reference pulse generator RP_GEN 210 receives a reference pulse F REF for detecting the speed difference of the output signal F DIV of the divided voltage controlled oscillator via the reference clock F REF and the frequency divider 140, F REF1 ). At this time, the reference pulse (F REF1) may be of a predetermined pulse width around the falling edge of the reference clock (F REF), the pulse width is preferably narrower than the pulse width of the reference clock (F REF). FIG. 3 illustrates a timing diagram between signals generated and operated in the frequency detector according to an embodiment of the present invention. Referring to FIG. 3, the reference pulse F REF1 is divided into a reference clock F REF and a frequency divider (MMD) 140 and an output signal (F DIV ) of the frequency-divided voltage-controlled oscillator. In this case, the reference clock F REF0 is different from the reference clock F REF displayed at the input terminal of the reference pulse generator (RP_GEN) 210, and is different from the reference clock F REF . Referring to FIG. 3, a reference pulse F REF1 generated in a reference pulse generator (RP_GEN) 210 is a pulse having a predetermined width A around a polling edge of a reference clock F REF0 And a polling edge of the reference clock F REF0 . At this time, when the position of the output signal F DIV of the divided voltage controlled oscillator via the frequency divider (MMD) 140 appears on the left side with respect to the position illustrated in FIG. 3, the voltage controlled oscillator (VCO) 115 And the output frequency of the voltage controlled oscillator (VCO) 115 is fast when it is displayed on the right side.

The 3-input frequency detector 220 receives the reference clock F REF0 , the reference pulse F REF1 , and the output signal F DIV of the frequency- divided voltage controlled oscillator And generates a control signal FAST for frequency fixing based on the reference clock F REF0 and the state value of the reference pulse F REF1 when an output signal F DIV of the divided voltage controlled oscillator is triggered, Or SLOW). The reference clock F REF0 , the reference pulse F REF1 and the output signal F DIV of the divided voltage controlled oscillator at a specific point are compared and analyzed by referring to the timing chart shown in FIG. 3 And outputs a control signal (FAST or SLOW) for frequency fixing. For example, a 3-input frequency detector 220 detects the reference clock F REF0 every time the output signal F DIV of the divided voltage controlled oscillator is triggered, (F REF1 ) are accumulated and compared, and when the values are not changed, it is determined that the frequency is fixed. If not, the 3-input frequency detector 220 outputs a control signal FAST or SLOW for fixing the frequency, and the reference clock F REF0 , which is accumulated, It is determined that the output signal F DIV of the divided voltage controlled oscillator is slow when the values of the reference clock F REF1 change in the order of 10, 11, 01, 00, and the accumulated reference clock F REF0 , When the values of the pulse F REF1 change in the order of 00, 01, 11, and 10, it is determined that the output signal F DIV of the divided voltage controlled oscillator is fast and the corresponding control signal can be output.

4 is a schematic block diagram of a 3-input frequency detector according to an embodiment of the present invention. That is, FIG. 4 is a schematic block diagram of a 3-input frequency detector 220 illustrated in FIG.

Referring to FIG. 4, a 3-input frequency detector 220 includes a plurality of D flip flops DFF0, DFF1, DFF2, DFF3, DFF4, DFF5, DFF6, EX-OR gates XOR0 and XOR1, and a plurality of control signal determinants (Decision 1, Decision 2). The plurality of D flip-flops DFF0 and DFF1 receive the current value FD0 [0] of the reference clock F REF0 and the previous value FD0 [0] of the reference clock F REF0 when the output signal F DIV of the divided voltage- The plurality of D flip-flops DFF2 and DFF3 outputs the current value FD1 of the reference pulse F REF1 when the output signal F DIV of the divided voltage controlled oscillator is triggered, 0] and the previous value FD1 [1].

The EX-OR gate XOR0 receives the current value FD0 [0] and the previous value FD0 [1] of the reference clock F REF0 output from the plurality of D-flip flops DFF0 and DFF1 Identify whether they are the same or different. That is, when the current value FD0 [0] of the reference clock F REF0 is different from the previous value FD0 [1], a clock is generated and the clock signal CLK is transferred to the D flip-flops DFF4 and DFF5 The current value FD0 [0] and the previous value FD0 [1] of the reference clock F REF0 are output as FD_M [0] and FD_M [1]. That is, to the control signal determination unit (Decision 1).

The EX-OR gate XOR1 receives the current value FD1 [0] and the previous value FD1 [1] of the reference pulse F REF1 output from the plurality of D-flip flops DFF2 and DFF3 Identify whether they are the same or different. That is, when the current value FD1 [0] of the reference pulse F REF1 is different from the previous value FD1 [1], a clock is generated and the clock signal CLK1 is transferred to the D flip- The current value FD1 [0] and the previous value FD1 [1] of the reference pulse F REF1 are output as FD_M [0] and FD_M [1]. That is, to the control signal determination unit (Decision 2).

FIG. 5 is a diagram illustrating a connection structure between a third order sigma delta modulator and a charge pump according to an embodiment of the present invention. Referring to FIG. 1 and 5, the input to the charge pump (CP) (135) structure, and a third order sigma-delta modulator (3 rd order SDM) (134 ) of the implementation in order to generate a spread spectrum clock (SSC) the type of signal (F 30kHz, SDM_IN [19: 0], F REF) , a third order sigma-delta modulator (3 rd order SDM) and the output signal (UPB SDM, DN SDM) of 134, a charge pump ( (CP) 135 and the route through which the output signal of the charge pump (CP) 135 is delivered to the loop filter 114 of the subsampling phase locked loop circuit (SSPLL) Respectively.

6 is a timing diagram illustrating input / output signals of a third order sigma delta modulator in the structure illustrated in FIG. 6, the third order sigma-delta modulator (3 rd order SDM) of the signal input to the 134: a (F 30kHz, SDM_IN [19 0 ], F REF), over time, the state change .

7 is a timing diagram showing a relationship between a frequency and a phase difference of a spread spectrum clock generator according to an embodiment of the present invention. Referring to FIG. 7, the relationship between the spread spectrum clock and the phase difference output by the present invention can be known.

8 is a flowchart illustrating a process flow for a spread spectrum clock generating method according to an embodiment of the present invention. Referring to FIGS. 1 and 8, a spread spectrum clock generating method according to an embodiment of the present invention is as follows.

First, in step S110, the control voltage regulator 130 sets the modulation conditions based on the reference clock F REF and the voltage control oscillator output signal F VCO . For example, the divider 133 determines the modulation frequency based on the reference clock F REF , and includes one frequency divider DIV2 131, a frequency detector FD 200, A sigma delta modulation input decision unit (SDM input decision) unit 132 generates a modulation width Dm based on the reference clock F REF and the output signal F VCO of the voltage controlled oscillator (VCO) .

In step S120, the third order sigma-delta modulator (3 rd order SDM) (134 ), on the basis of the modulation condition set in step S110, and performs the modulation. That is, the third order sigma-delta modulator (3 rd order SDM) (134 ) is modulated to the reference clock (F REF) by delta-sigma modulation scheme tertiary.

In step S130, 3 car order sigma-delta modulator (3 rd order SDM) (134 ) is, by applying a pulse value (UPB SDM, DN SDM) generated by the modulation result to the charge pump (CP) (135) charge pump (CP) 135 is controlled.

In step S140, the charge pump (CP) 135 adjusts the output voltage of the loop filter 114 based on the pulse values (UPB SDM , DN SDM ) generated as a result of the modulation. That is, the charge pump (CP) 135 adjusts the amount of charges to the pulse values (UPB SDM , DN SDM ) generated as a result of the modulation, and the charges (C1, C2) of the capacitors Directly controls the discharge.

In the above-described exemplary system, the methods are described on the basis of a flowchart as a series of steps or blocks, but the present invention is not limited to the order of the steps, and some steps may occur in different orders .

It will also be understood by those skilled in the art that the steps shown in the flowchart are not exclusive and that other steps may be included or that one or more steps in the flowchart may be deleted without affecting the scope of the invention.

Claims (15)

In a spread spectrum clock generator,
A subsampling phase locked loop including a voltage controlled oscillator and fixing the phase by subsampling the signal output from the voltage controlled oscillator with a reference clock (F REF ) period;
A frequency locked loop for fixing the frequency of the voltage controlled oscillator output signal to the frequency of the reference clock (F REF ); And
And a control voltage regulator for regulating a control voltage of the voltage controlled oscillator based on a control signal generated by pulse width modulation of the reference clock (F REF ) to spread the spectrum of the voltage controlled oscillator output signal,
The frequency locked loop
And a frequency detector for comparing the reference clock signal (F REF ) with the divided voltage-controlled oscillator output signal (F DIV ) to output a control signal (FAST or SLOW) for frequency fixing,
The frequency detector
Reference pulse generator for being of a predetermined pulse width around the falling edge of the reference clock (F REF), the pulse width is caused to narrow reference pulses (F REF1) than the pulse width of the reference clock (F REF); And
The reference clock F REF , the reference pulse F REF1 and the output signal F DIV of the divided voltage controlled oscillator as input and the output signal F DIV of the divided voltage controlled oscillator And a 3-input frequency detector for outputting the control signal (FAST or SLOW) for frequency fixing based on the reference clock (F REF ) and the state value of the reference pulse (F REF1 ) when triggered Spread spectrum clock generator. 2. The method of claim 1, wherein the subsampling phase locked loop
Voltage controlled oscillator;
A loop filter that includes a plurality of capacitors and adjusts a control voltage of the voltage controlled oscillator based on an amount of charge charged / discharged to / from the capacitor;
A sampler for sub-sampling a signal output from the voltage controlled oscillator at a reference clock (F REF ) period;
A first charge pump for controlling charging / discharging of the capacitors included in the loop filter based on the sampling result; And
And a pulser for controlling an operating time of the first charge pump based on the reference clock (F REF ) period. 3. The method of claim 2,
Further comprising a frequency divider dividing the frequency of the voltage controlled oscillator output signal into a plurality of frequencies and feeding the divided signal (F DIV ) back to the frequency locked loop and the control voltage regulator. 4. The apparatus of claim 3, wherein the frequency locked loop
And a second charge pump for controlling the charging / discharging of the capacitors included in the loop filter based on the control signal (FAST or SLOW) output from the frequency detector. delete 5. The apparatus of claim 4, wherein the 3-
First and second D flip-flops for outputting a current value and a previous value of the reference clock (F REF ) when an output signal (F DIV ) of the divided voltage controlled oscillator is triggered;
Third and fourth D flip-flops for outputting a current value and a previous value of the reference pulse (F REF1 ) when the output signal (F DIV ) of the divided voltage controlled oscillator is triggered;
A fifth and a sixth D flip-flop for outputting the two values when the current value and the previous value of the reference clock signal (F REF ) output from the first and second D flip-flops differ from each other;
A seventh and an eighth D flip-flop outputting the two values when the current value and the previous value of the reference pulse (F REF1 ) output from the third and fourth D flip-flops differ from each other; And
And a first and a second control signal determination unit connected to the output terminals of the fifth and sixth D-flip flops and the output terminals of the seventh and eighth D-flip flops, respectively. 7. The apparatus of claim 6, wherein the 3-
A first EX-OR gate for identifying whether the current value of the reference clock signal (F REF ) output from the first and second D flip-flops is equal to or different from a previous value; And
Further comprising a second EX-OR gate for identifying whether the current value of the reference pulse (F REF1 ) output from the third and fourth D flip-flops is equal to or different from a previous value, generator. 4. The apparatus of claim 3, wherein the control voltage regulator
A third charge pump including a plurality of switches, each of which controls charging and discharging of the capacitors included in the loop filter based on an adjustment signal for controlling ON / OFF of each of the plurality of switches;
A third order sigma delta modulator for modulating the reference clock (F REF ) and outputting an adjustment signal for adjusting on / off of each of the switches of the third charge pump as a result;
A first frequency divider dividing the reference clock signal (F REF ) to determine a modulation frequency of the third order sigma delta modulator; And
And a modulation width determination unit for determining a modulation width of the third order sigma delta modulator based on the reference clock signal (F REF ) and the voltage controlled oscillator output signal (F DIV ) divided by the frequency divider Spectrum Clock Generator. 9. The apparatus of claim 8, wherein the modulation width determination unit
A second frequency divider for dividing the reference clock (F REF ) by two;
The second frequency divider with the reference clock (F REF / 2) and the division voltage from the frequency divider controlled oscillator output signal (F DIV) the two of the voltage controlled oscillator output signal (F DIV) frequency division in the frequency divider by comparing frequency divider A frequency detector for outputting a control signal for fixing the reference clock signal to a reference clock signal (F REF / 2); And
And an SDM input array generator for outputting n array values for determining the modulation width of the third order sigma delta modulator based on the control signal output from the frequency detector. 10. The apparatus of claim 9, wherein the frequency detector
The two are of a predetermined pulse width around the falling edge of the frequency divider reference clock (F REF / 2), the pulse width is narrow reference pulses than the pulse width of the second dispensed reference clock (F REF / 2) ( A reference pulse generator for generating F REF1 ; And
The reference clock F REF1 and the output signal F DIV of the divided voltage controlled oscillator from the divided reference clock F REF / 2 and outputting an output signal of the divided voltage controlled oscillator, (F DIV) is triggered when the three-input frequency detector based on a state value of said second reference clock, a frequency divider (F REF / 2) and the reference pulse (F REF1) outputs a control signal for the fixed frequency ≪ / RTI > 11. The apparatus of claim 10, wherein the 3-
An eleventh and twelfth D flip-flops for outputting a current value and a previous value of the divided reference clock (F REF / 2) when the output signal (F DIV ) of the divided voltage controlled oscillator is triggered;
A thirteenth and fourteenth D flip-flops for outputting a current value and a previous value of the reference pulse (F REF1 ) when an output signal (F DIV ) of the divided voltage controlled oscillator is triggered;
The fifteenth and sixteenth D-flip-flops, which output the two values when the present value and the previous value of the two divided reference clocks (F REF / 2) output from the eleventh and twelfth D- ;
A seventeenth and eighteenth D flip-flops for outputting the two values when the current value and the previous value of the reference pulse (F REF1 ) output from the thirteenth and fourteenth D-flip flops differ from each other; And
And an eleventh and twelfth control signal determiners connected respectively to the output ends of the fifteenth and sixteenth D-flip flops and to the output ends of the seventeenth and eighteenth D-flip flops. 12. The apparatus of claim 11, wherein the 3-
An eleventh EX-OR gate for identifying whether the current value of the divided reference clock (F REF / 2) output from the eleventh and twelfth D-flip flops is the same as or different from the previous value; And
And a twelfth EX-OR gate for discriminating whether or not the current value of the reference pulse (F REF1 ) output from the thirteenth and fourteenth D-flip flops is the same as or different from the previous value. generator. A spread spectrum clock generation method based on a sub-sampling phase locked loop circuit including a voltage controlled oscillator and a loop filter,
Modulating the reference clock (F REF ) of the subsampling phase locked loop circuit with a third-order sigma delta modulation scheme based on a preset modulation condition; And
And adjusting the output voltage of the loop filter based on the control signal output as the modulation result,
The modulating step
Determining a modulation frequency based on a reference clock (F REF ) of the subsampling phase locked loop circuit; And
Further comprising determining a modulation width based on the reference clock (F REF ) and the voltage controlled oscillator output signal (V VCO ) of the subsampling phase locked loop circuit
Wherein the spread spectrum clock generating method comprises the steps of: delete 14. The method of claim 13, wherein the step of adjusting the loop filter output voltage comprises:
And the charge / discharge of the capacitors constituting the loop filter is directly controlled based on the control signal output as a result of the modulation.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879914B1 (en) 2019-07-18 2020-12-29 Samsung Electronics Co.. Ltd. Phase-locked loop (PLL) circuit and clock generator including sub-sampling circuit
US11817863B2 (en) 2021-07-21 2023-11-14 Chung Ang University Industry Academic Cooperation Foundation Fractional-n sub-sampling phase locked loop using phase rotator

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102452496B1 (en) * 2020-06-26 2022-10-11 한국과학기술원 Sub-sampling phase locked-loop circuit, wireless communication device and method of operating the same
KR102430227B1 (en) 2020-07-17 2022-08-08 고려대학교 산학협력단 Dual domain sub sampling phase lock loop
CN112202424A (en) * 2020-11-06 2021-01-08 珠海市一微半导体有限公司 N-time pulse width expansion circuit and pulse width expanded phase-locked loop system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100778374B1 (en) * 2007-02-16 2007-11-22 인하대학교 산학협력단 Multi spread ratio spread spectrum clock generator
KR101401504B1 (en) 2012-12-28 2014-06-11 성균관대학교산학협력단 A spread spectrum clock generator with a hershey-kiss modulation profile using multiple charge pumps
US9197224B2 (en) 2011-07-13 2015-11-24 The Trustees Of Columbia University In The City Of New York Circuits and methods for a combined phase detector

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100778374B1 (en) * 2007-02-16 2007-11-22 인하대학교 산학협력단 Multi spread ratio spread spectrum clock generator
US9197224B2 (en) 2011-07-13 2015-11-24 The Trustees Of Columbia University In The City Of New York Circuits and methods for a combined phase detector
KR101401504B1 (en) 2012-12-28 2014-06-11 성균관대학교산학협력단 A spread spectrum clock generator with a hershey-kiss modulation profile using multiple charge pumps

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879914B1 (en) 2019-07-18 2020-12-29 Samsung Electronics Co.. Ltd. Phase-locked loop (PLL) circuit and clock generator including sub-sampling circuit
US11817863B2 (en) 2021-07-21 2023-11-14 Chung Ang University Industry Academic Cooperation Foundation Fractional-n sub-sampling phase locked loop using phase rotator

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