CN104704642B - Method for manufacturing opto-electronic device - Google Patents
Method for manufacturing opto-electronic device Download PDFInfo
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- CN104704642B CN104704642B CN201380050764.5A CN201380050764A CN104704642B CN 104704642 B CN104704642 B CN 104704642B CN 201380050764 A CN201380050764 A CN 201380050764A CN 104704642 B CN104704642 B CN 104704642B
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- 230000005693 optoelectronics Effects 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
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Abstract
The present invention relates to a kind of opto-electronic devices and a kind of method for manufacturing opto-electronic device, the wherein grown layer structure in growth substrates, the layer structure has the semiconductor layer (2 or 3) just adulterated and the semiconductor layer (3 or 2) of negative doping together with the active area and mirror layer (4) for generating light, wherein the layer structure is fixed on the first side of carrier (10) via articulamentum (8), and the electrical contacts for being used for layer structure are wherein introduced via second side of carrier (10), and remove growth substrates.
Description
Technical field
The method and a kind of opto-electronic device that the present invention relates to a kind of for manufacturing opto-electronic device.
Background technique
A kind of opto-electronic device known and a kind of for manufacturing the opto-electronic device from 10 2,010 025 320 A1 of DE
Method.
In described method, the growing optics active layer in growth substrates.And then, by optically active layer from vacating
Side rise structuring, wherein introducing electrical contacts.Electrical contacts are connect with the layer just adulterated and with the layer of negative doping.It is tying
Device is fixed on carrier after beam structuring.And then growth substrates are removed.
Summary of the invention
The purpose of the present invention is: propose a kind of improved method for manufacturing the device and a kind of device of simple structure
Part.
The purpose of the present invention with device according to the present invention by realizing according to the method for the present invention.
The advantages of described method and described device is: carrier is integrated into device.Thus it eliminates for carrying
Body manufactures through-hole, pad etc. in extremely necessary work step, such as composition through-hole, filling front side.
Furthermore it is possible to not only make the structure of carrier by the way that carrier to be integrated into opto-electronic device but also make the size of carrier
Most preferably match device.
Other Advantageous embodiments of the method and the device are described herein.
In one embodiment, use electrically insulating material, especially binding material as articulamentum.Use electrical isolation material
Material offers the advantage that conductive material or semiconductive material can also act as carrier as articulamentum.Particularly, make
Following possibility is provided with binding material: safety and the jail between layer structure and carrier are realized in the case where thickness degree is small
Solid connection.It is furthermore possible to the saving by using binding material cost of implementation.
In another embodiment, use material that is semiconductive or conductive, being especially in form of film as load
Body.Material that is semiconductive or conductive, being especially in form of film is used to provide the advantage that processing is as carrier
Simple possible.It is furthermore possible to constitute thin carrier, the carrier shows enough stability for opto-electronic device.Especially
Ground is performed quickly using thin carrier and introduces recess portion in the carrier for being constituted contact portion.It therefore saves on
Process time is to save cost.
In another embodiment, contact portion is constituted in a common method and step separately or together.Contact portion
Recess portion is especially represented respectively completely filled up, center dant extends through carrier and especially additionally passes through semiconductor layer.With
It can continuously, for example be constituted between carrier and the semiconductor layer of pending contact in the contact portion of electrical contact semiconductor layer,
Including carrier and semiconductor layer.This means that: contact portion seamlessly constitute and do not have articulamentum, for example welding layer or
Person's adhesive layer.Particularly, contact portion only has a kind of material that can be conductive, and the material for example can be that metal or metal close
Gold.Contact portion for example manufactures in a method and step one-piece.
In another embodiment, in order to improve reflection characteristic, electrical contacts are equipped with mirror layer.
In another embodiment, in order to improve reflection characteristic of the device on the side of carrier, connecting material, institute are used
It is substantially passable for the light emitted by device to state connecting material.Furthermore following carrier is used, the carrier
Side is constituted towards articulamentum and in a manner of mirror surface.Thus by active area along the light radiated towards the direction of carrier by carrying
The lateral reflection of the mirror reflection of body.Which thereby enhance the luminous flux issued via radiation side.
In another embodiment, the first contact portion is constituted as follows: the first contact portion is in negative half adulterated of direction
It is constituted in a manner of mirror surface on the side of conductor layer.Thus the reflection in the direction towards radiation side of emitted light is also improved.
In another embodiment, using the packing material with inhomogeneity, wherein packing material is for example with photosensitive
Material.It can be realized simple processing in this way.In addition, in order to introduce contact portion, packing material can for example by means of
DRIE (deep reaction ion etching) technique quickly and easily removes.
Recess portion in articulamentum can for example be generated by laser ablation, and wherein the opening of carrier can be acted on herein as light
Door screen.Processing rapidly and simply is also possible as a result,.
Detailed description of the invention
Of the invention hereinbefore described characteristic, feature and advantage and realize these characteristics, feature and advantage
Methods combine the description of following pairs of embodiments to become more apparent upon and be more readily understood, and the implementation is elaborated in conjunction with attached drawing
Example, wherein
Fig. 1 to 3 shows first method step,
Fig. 4 shows second method step,
Figures 5 and 6 show third method step,
Fig. 7 and 8 shows fourth method step,
Fig. 9 and 10 shows the 5th method and step,
Figure 11 shows the 6th method and step,
Figure 12 shows the view observed above the carrier according to the first embodiment of Figure 11,
Figure 13 is shown in the top view according to the carrier of the second embodiment of the 6th method and step,
Figure 14 is shown in the top view according to the carrier of third embodiment,
Figure 15 to 17 shows the 4th processing step,
Figure 18 shows thinned chip,
Figure 19 shows the schematic diagram with the opto-electronic device for using thinned chip as carrier,
Figure 20 shows the device with converter and lens, and
Figure 21 shows the device with carrier structure.
Specific embodiment
Fig. 1 shows first method step, wherein the semiconductor layer 2 of negative doping is grown into growth substrates 1.Half just adulterated
Conductor layer 3 is grown on the semiconductor layer 2 of negative doping.Between the semiconductor layer 2 for bearing doping and the semiconductor layer 3 just adulterated
Edge surface is equipped with active area, and the active area is constituted for generating light.The semiconductor layer 2 of negative doping is hereinafter referred to as first
Semiconductor layer 2 and the semiconductor layer 3 just adulterated hereinafter referred to as the second semiconductor layer 3.As an alternative, the first semiconductor layer 2
It also can be p-type doping and the second semiconductor layer can be n-type doping.First and second semiconductor layers, 2,3 such as shape
At thin film diode.First and second semiconductor layers 2,3 forming layer structures.
Growth substrates 1 can for example be constituted in the form of sapphire or silicon metal.In addition, growth substrates 1 can be by carbon
SiClx is constructed by gallium nitride.First and second semiconductor layers 2,3 are epitaxially grown in growth substrates 1.According to selected
Embodiment, middle layer can be applied in growth substrates 1, the middle layer substantially has and layer structure phase to be grown
Same lattice structure.The growth of the first semiconductor layer 2 can be improved in this way, so that in growth in the first semiconductor layer
Lattice structure in generate less defect or do not generate defect.
And then, as illustrated in Figure 2, mirror layer 4 is applied on the second semiconductor layer 3.Mirror layer 4 can include
Metal with high reflection coefficient such as silver and/or titanium.Furthermore in mirror layer 4 be equipped with opening 5 so that apply mirror layer 4 it
The surface of the semiconductor layer 3 just adulterated in the region of opening 5 afterwards is exposed, as illustrated in Figure 2.Opening 5 can
Simultaneously it is arranged with application mirror layer 4 or is introduced into mirror layer 4 afterwards.In the following method and step being shown in FIG. 3, lead
Electric layer 6 is applied in mirror layer 4.According to selected embodiment, conductive layer 6 can be also abandoned.Conductive layer 6 is as mirror layer 4
It is same that there is opening 5.The opening can generate individually or together with the opening in mirror layer 4.Thus in the two layers 4 and 6
Opening 5 can be having the same or different recess portion.
The layer structure that first and second semiconductor layers 2,3 can be configured to epitaxial layer sequence, be configured to epitaxial growth.?
This, layer sequence 2,3 can for example be constituted based on InGaAlN.Layer structure based on InGaAlN especially includes such layer
Structure: wherein the layer structure of extension manufacture usually has the sequence of layer being made of different single layers, and the sequence of layer includes at least
One single layer, the single layer have the material for coming from III-IV group iii v compound semiconductor material system InxAlyGa1-x-yN,
In 0≤x≤1,0≤y≤1 and x+y≤1.With at least one active layer or active region based on InGaAlN
Layer structural example such as being capable of electromagnetic radiation of the preferred emission in UV wavelength range into green color wavelength range.
Alternatively or additionally, semiconductor layer 2,3 or semiconductor chip can also be based on InGaAlP, that is to say, that
Layer structure can have different single layers, and wherein at least one single layer, which has, comes from III-IV group iii v compound semiconductor material system
The material of InxAlyGa1-x-yP, wherein 0≤x≤1,0≤y≤1 and x+y≤1.With based on InGaAlP at least
The layer structural example of one active layer or active region such as can preferred emission have green into red wavelength range one
The electromagnetic radiation of a or multiple spectral components.
Alternatively or additionally, semiconductor layer 2,3 can also have other III-IV group iii v compound semiconductor materials
System, for example based on the material of AlGaAs, or have II-VI group compound semiconductor materials system.Particularly, have and be based on
The active layer of the material of AlGaAs can be suitable for transmitting with one or more spectrum in red into infrared wavelength range
The electromagnetic radiation of component.
II-VI group compound semiconductor materials system can have at least one element for coming from the second main group, such as Be,
Mg, Ca, Sr, and come from the element of the 6th main group, such as O, S, Se.Particularly, II-VI group compound semiconductor materials system packet
Compound that include divalent, trivalent or tetravalence, the compound include coming from least one element of the second main group and going out
From at least one element of the 6th main group.Furthermore such divalent, trivalent or tetravalence compound can for example have
One or more dopants and additional component part.II-VI group compound semiconductor materials for example including ZnSe, ZnTe,
ZnO、ZnMgO、ZnS、CdS、ZnCdS、MgBeO。
Growth substrates 1 can include semiconductor material, such as above compound semiconductor material system herein.Particularly,
Growth substrates 1 can include sapphire, GaAs, GaP, GaN, InP, SiC, Si and/or Ge or consist of such materials.
Semiconductor layer 2,3 can be as active region for example with traditional pn-junction, double-heterostructure, single quantum well knot
Structure (SQW structure) or multi-quantum pit structure (MQW structure).Term quantum well structure especially includes in the scope of this application
It is all such as flowering structure, two carriers can be subjected to the quantization of its energy state due to limitation (" confinement ").Especially
Ground, term quantum well structure do not include the explanation about quantized dimension.Thus furthermore quantum well structure includes Quantum Well, amount
Any combination of sub-line and quantum dot and these structures.Semiconductor layer 2,3 can also include other functions in addition to active region
Layer and functional area, such as p-type doping or the carrier transport layer of n-type doping, i.e. electrontransporting layer or hole transport
Layer, undoped or p-type doping or n-type doping limiting layer, coating or wave conductor layer, barrier layer, planarization
Layer, buffer layer, protective layer, contact layer and/or electrode and their combination.It is such to be related to active region or other function
Can layer and region structure for those skilled in the art especially with respect to construction, known to function and structure to about this
Point is not illustrated in detail.
In the following method and step being shown in FIG. 4, channel 7 is introduced into the first and second semiconductor layers 2,3,
The channel makes a part for the layer structure being made of the first and second semiconductor layers 2,3 and the rest part point of layer structure
It opens.Circumferentially a part of of surrounding layer structure 2,3 constitutes and guides until growth substrates 1 channel 7.
According to selected embodiment, the method and step of Fig. 1 to 3 is implemented on the biggish area of growth substrates 1,
In simultaneously will corresponding mirror layer 4 separated from each other and conduction for multiple opto-electronic devices in the method and step of Fig. 2 and 3
Layer 6 is applied on the first and second semiconductor layers 2,3 of large area.In the method and step according to Fig. 4, the layer structure of large area
Region be structured to be respectively used to each sub-regions an of device.
Fig. 5 shows the set-up mode of Fig. 4, wherein the set-up mode is to reverse.According to the set-up mode of Fig. 5 via even
Layer 8 is connect fixed on the upside 9 of carrier 10.The material of articulamentum is also filled into the region of opening 5.According to selected implementation
Mode, opening 5 can be filled up with other packing materials 11.In figs. 6 and 7, packing material 11 is completely filling up opening 5.It fills out
Material is filled to be adjacent to the second semiconductor layer 3, conducting shell 6 herein and be adjacent to mirror layer 4.In order to constitute the first recess portion 14 locally
Packing material 11 and the second semiconductor layer 3 are removed, so that locally exposing the first semiconductor layer 2 in the first recess portion 14.Especially
Ground, remaining packing material 11 surround the first recess portion 14 along transverse direction.Remaining packing material 11 is herein along lateral side
To setting between the first recess portion 14 and mirror layer 4.Packing material 11 can be configured to reflexive.Packing material is for example comprising use
In the particle, such as titan oxide particles that improve reflectivity.By means of articulamentum 8 by the first and second semiconductor layers 2,3 and mirror layer 4
It is fixed on the upside 9 of carrier 10 with conducting shell 6.In one embodiment, using with inhomogeneity packing material 11,
Such as cavity and/or filler and/or scattering particles.In addition, packing material 11 can for example be configured to photosensitive material.With this
Mode can be realized simple processing.
Articulamentum 8 can be formed by binding material, such as be configured to nonconducting binder.In another embodiment,
Articulamentum 8 also can for example be consisted of metal in the form of conductive material, and the metal is via soldering connection by semiconductor layer 2,3
It is fixed on the upside 9 of carrier 10.
Materials described below is suitable for composition in the articulamentum of binder form: thermoplastic (such as Brewer Science
Waferbond), the polyurethane (DELO-PUR 9604) of two components, two components epoxy resin (be based on bisphenol-A, phenolic resin
Deng two rings or polyepoxide, polyamine curing agent, mercaptan), polyimides (adhesive HD 3007/HD 7010Dupont)/
HD micro-system), acrylic acid, silicone (dimethyl silscone).
It is for example executed in film cementing machine according to the bonding process of Fig. 6.According to selected embodiment, articulamentum 8
Thickness degree can be in the range less than 10 μm in the free upside or conducting shell 6 of the upside of carrier 10 and free mirror layer
It is realized between free upside.The thickness of articulamentum 8 for example also can be less than 1 μm.
Using nonconducting articulamentum 8, be also able to use conductive material such as metal (Mo, W, C, CuW,
AlSi, AlSiC) or semiconductive material such as Si, Ge, GaAs carrier 10.Carrier 10 also being capable of structure in membrane form
For example can be in 100 μm of range at, intima-media thickness, but it also can be in the smaller range within 10 μm.?
In the case that carrier 10 consists of metal, carrier for example can be equipped with electricity by means of ALD technique, CVD technique or PVD process absolutely
Edge layer.Carrier 10 can also be constituted in the form of electric insulation layer, especially be constituted in membrane form, for example in the form of plastic foil
It constitutes.
Furthermore opening 5 can be filled up with packing material 11 before bonding process.It can be shelled again by means of DRIE technique
The photosensitive material (ProTEK) or coating of erosion are for example suitable as packing material 11.
By provide in form membrane, especially in metal form membrane carrier 10 in the Joining Technology according to Fig. 6 energy
Enough use roll-to-roll manufacture.In addition, carrier 10 arrives the interconnecting piece of semiconductor layer 2,3 since process sequence can flatly, very
It unfertile land and equably constitutes.In addition, ESD diode can be directly integrated into system, such as it is integrated on the downside of carrier
Contact disc between.When constituting the carrier 10 in silicon form, ESD diode can be also directly integrated into silicon.This can lead to
It crosses local implantation to realize, wherein connecting via pad metal portion or routing planes again associated there progress.
When using the articulamentum on carrier made of silicon 10 of the brazed joints as passivation, structuring passes through channel
7 (mesa structure, Mesastrukturierung) are executed after removing growth substrates 1.Passivation is for example existed by means of ALD method
Mirror layer 4 is etched back to carry out later.
In the following method and step being shown in FIG. 7, in the area of the opening 5 of mirror layer 4 from the downside of carrier 10 13
The first recess portion 14 is introduced in domain.Furthermore the second recess portion 15 is introduced in the region of mirror layer.First and second recess portions 14,15 and carrier
10 material relatedly is introduced by means of corresponding method.When constituting the carrier 10 in semiconductive material forms, such as can
Enough use etching method.When constituting the carrier 10 in metallic forms, it is able to use the method such as laser ablation for degrading metal.It should
The method stage is shown in FIG. 7.
And then articulamentum 8 is removed in following method and step and removes the filling above the first recess portion 14 when necessary
Material 11, so that recess portion 14 is abutted to the semiconductor layer 2 of negative doping, active area 16 is arranged in the semiconductor layer of the negative doping
Top.In addition, articulamentum 8 is removed in the region of the second recess portion 15, so that the guidance of the second recess portion 15 is to conducting shell 6 or not
It guides in the case where there are conducting shell 6 to mirror layer 4.This method stage is shown in FIG. 8.
According to the type of packing material 11 and articulamentum 8, such as DRIE technique is able to use for removing articulamentum 8 and filling out
Fill material 11.In addition, packing material 11 and articulamentum 8 can for example be removed by means of laser ablation method.It has been set herein
The first and/or second recess portion 14,15 in carrier 10 is used as diaphragm.
In the following method and step being shown in FIG. 9, it is recessed that insulating layer 17 is applied to downside 13 and first and second
On the side wall in portion 14,15.According to selected embodiment, insulating layer 17 can be on the side wall of recess portion 14 in the form of mirror layer
It constitutes.After applying insulating layer 17 and the structuring insulating layer, the first recess portion 14 not yet abuts directly against the first semiconductor layer 2.
In addition, the adjacent conducting shell 6 of the second recess portion 15 or the adjacent mirror layer 4 in the case where conducting shell 6 are not present.Insulating layer 17 for example can
It is enough to be deposited by means of ALD or based on the CVD technique of TEOS (ethyl orthosilicate).In another embodiment, energy is being introduced
Conductive material is for manufacturing the first contact portion before by conductive and mirror reflection metal layer in the area of the first recess portion 14
It is applied in domain on the face of the exposing of the semiconductor layer 2 of negative doping and the face of the exposing of insulating layer 17.
In following method and step, by the first and second conductive materials of recess portion 14,15, for example with metal by using
Galvanoplastic fill up and and then first or second contact disc 18,19 are applied on the downside of insulating layer 17.According to carrier 10
Embodiment, planarisation step can be carried out before or after applying contact disc 18,19, such as carried out by means of CMP.It should
Method process is shown in FIG. 10.
First contact portion 32 is constituted in the first recess portion 14.Second contact portion 33 can be constituted in the second recess portion 15.Draw
Entering the first contact portion 32 or the second contact portion 33 can execute in a method and step, for example, by with conductive material especially
It is to fill up recess portion 14 or 15 by using galvanoplastic.
First contact portion 32, which extends through carrier 10, articulamentum 8, mirror layer 4 and the second semiconductor layer 3 and enters the first half, leads
In body layer 2.The first contact portion 32 is constituted for being in electrical contact the first semiconductor layer 2 thus while in carrier 10 and second
It is executed in semiconductor layer 3.In the inside of the first recess portion 14, the first contact portion 32 is in the first semiconductor layer 2 and the first contact disc 18
Between be especially successively formed.This means that: the first contact portion 32 is inside the first recess portion in the first semiconductor layer 2 and first
It is for example constituted one-piece between contact disc 18.First contact portion 32 for example only has material that can be conductive, the energy conduction
Material is in the first recess portion 14 for being used to fill up between the first semiconductor layer 2 and the first contact disc 18 in a method and step.Especially
Ground, contact portion 32 do not have articulamentum, and the articulamentum makes the first part of contact portion 32 laterally surrounded by carrier 10 and connects
Another part connection of contact portion 32 laterally surrounded by the second semiconductor layer 3, wherein articulamentum has first with contact portion 32
Part or the different material of another part.
Second contact portion 33 extends through carrier 10 and articulamentum 8.In the inside of the second recess portion 15, the second contact portion 33 is outstanding
It is successively formed.Second contact portion 33 for example only has material that can be conductive, and the material that can be conductive is walked in a method
For filling up the second recess portion 15 in rapid.In Figure 10, the second contact portion 33 is via mirror layer 4 and conducting shell 6 and the second semiconductor layer 3
Electrical connection.In contrast to this, the second contact portion 33 also can be directly electrically connected with the second semiconductor layer 3.
In addition, using be made of semiconductive material, for example in the carrier of wafer form when, insulating layer 17 can
It is configured to silicon dioxide layer.
And then growth substrates 1 are removed.Can for example be stripped thus by means of laser method strip growth substrates 1 or by
Growth substrates are removed in CMP (chemical-mechanical planarization) method.And then it is roughened the side 20 on the top of the first semiconductor layer 2.
This method process is shown in FIG. 11, wherein the thickness of the first semiconductor layer 2 is shown in the way to enlarge.Furthermore divide each device
Part.
Figure 12 illustrates the first device 21 by the vertical view of the first and second contact discs 18,19.First and second contact discs
18,19 is electrically separated by the second channel 22.In addition, in shown embodiment be equipped with multiple first and second recess portions 14,
15, the first and second recess portions conductive material fills and is first or second electrical contacts 32,33.For negative doping
First electrical contacts of semiconductor layer 2 are arranged with 4 × 4 set-up mode.Second electrical contact of the semiconductor layer 3 for just adulterating
It is arranged in the form of the second electrical contacts that portion is arranged in series by four.
Figure 13 shows an embodiment of the second device 34, is provided with the second contact being arranged in four angular zones
Disk 19.Second contact disc 19 is separated via the second channel 22 with the first contact disc 18 respectively.Similar to setting for the second contact disc 19
Mode is set, the second electrical contacts 33 are also disposed in rectangular angular zone.
Similar to the composition scheme of the form of the first contact disc 18, the first electrical contacts 32 are equably in the first contact disc
The mode being distributed on 18 face is arranged.
Figure 14 shows an embodiment of third device 35, wherein second contact disc in angular zone is only arranged
19, second contact disc is electrically insulated via the second channel 22 with the first contact disc 18, and first contact disc is substantially square
Ground is constituted.It is also provided only with second electrical contacts 33 in a similar way for contacting the semiconductor layer 3 just adulterated.This
Outside, the first electrical contacts 32 are arranged in a manner of being equably distributed on the face of the first contact disc 18.
The embodiment shown in Figure 12 to 14 is only the first and second contact discs 18,19 and corresponding first and second
The example of the possible allocation plan of electrical contacts 32,33.
Figure 15 shows another embodiment, and the embodiment is constructed essentially according to Figure 11, however wherein additional exhausted
Edge layer 23 is partly applied on the first contact disc 18 in the region of adjacent second contact disc 19.In addition, the second contact disc 19
From side up to being more than to be constituted above additional insulating layer 23.In addition, the first contact disc 18 is constituted in two layers, wherein first
Layer is placed on insulating layer 17 and the second layer is placed on first layer and other insulating layers 23.Additional insulating layer 23 is
There is recess, the recess passes through the flatening process lacked and constitutes in the region of one recess portion 14.In a similar way, it first connects
Tactile disk 18 has crook 24 in the region of the second layer.Such crook can also generate in the region of recess portion 15.And then,
First and second contact discs 18,19 can be flattened, so that obtaining it according to the structure of Figure 16.
Figure 17 shows the top view of the first and second contact discs 18,19.By the way that additional insulating layer 23 is arranged it is possible that
The geometry of the first and second contact discs 18,19 is designed for greater flexibility and disengages it from the reality of the first and second contact portions
The plan of establishment.
Figure 18 shows the carrier 10 in semiconductor die sheet form, the edge 24 that the carrier has annular circular, the side
Edge has the thickness improved relative to central region 36.Chip is for example configured to silicon wafer.The shape of carrier passes through such as lower section
Formula is realized: the interior zone of chip is thinned, wherein circular fringe region retains biggish thickness.Thus be conducive to chip
Mechanical stability.It is for example manufactured by means of the Taiko technique of Disco company according to the carrier of Figure 18.The thickness of silicon wafer is in
For example with 10 μm in portion region 36.
The carrier being shown in FIG. 18 is used as the carrier 10 according to Fig. 6.And then, corresponding structuring measure is executed,
Wherein Figure 19 shows the method stage according to Fig. 8.Similar to the set-up mode being shown in FIG. 19, can process according to Figure 19
Carrier on multiple devices.
Figure 20 shows a method stage, and two of them are arranged over the carrier 10 according to the device of Figure 16, wherein in frame
The circular separated structure 25 of form has for example been applied between device 21 by means of photoresist.In addition, will conversion in frame
Layer 26 and lens 27 are applied on the semiconductor layer 2 of negative doping.
The separated structure 25 of frame-shaped is for example manufactured by means of photoetching process.Mount structure for example can be by plastics, such as benzene
And cyclobutane manufactures.For example with silicone, luminous transformational substance such as YAG:Ce or other materials are embedded into conversion layer 26
In the silicone.
It is schematically that ESD diode 28 is introduced into carrier 10 by doping accordingly in Figure 20.In addition, ESD bis-
Pole pipe 28 can also be constituted on the downside of carrier 10, such as be constituted between contact disc 18,19.
The device being shown in FIG. 20 can be applied to another carrier followed by through-hole 30 and other contact portions 31
In structure 29, as illustrated in the schematic cross-sectional in Figure 21.Other contact portions 31 are arranged in carrier structure 29
Downside on and device 21 be arranged on the upside of carrier structure 29.
Other contact portions are arranged on the downside of carrier structure 29 and contact via through-hole 30 with the corresponding of device
Disk 18,19 connects.
Although the present invention is by preferred embodiment detailed illustration and description in details, the present invention does not pass through
Disclosed example and be restricted and those skilled in the art can therefrom derive other variations, without departing from
Protection scope of the present invention.
The priority of patent application claims German patent application 10 2,012 217 533.4, the disclosure of which are logical with regard to this
Reference is crossed to be incorporated herein.
Reference signs list
1 growth substrates
The semiconductor layer of 2 negative doping
3 semiconductor layers just adulterated
4 mirror layer
5 openings
6 conducting shells
7 channels
8 articulamentums
9 upsides
10 carriers
11 packing materials
13 downsides
14 first recess portions
15 second recess portions
16 active areas
17 insulating layers
18 first contact discs
19 second contact discs
20 upsides
21 first devices
22 second channels
23 additional insulating layers
24 edges
25 separated structures
26 conversion layers
27 lens
28 ESD diodes
29 carrier structures
30 through-holes
31 other contact portions
32 first electrical contacts
33 second electrical contacts
34 second devices
35 third devices
36 central regions
Claims (23)
1. a kind of method for manufacturing opto-electronic device,
The wherein grown layer structure on growth substrates (1), the layer structure have the first semiconductor layer (2), the second semiconductor layer
(3), and with the active area (16) for generating light, wherein being applied to mirror layer (4) away from described in the growth substrates
On second semiconductor layer, wherein the layer structure is fixed on the first side of carrier (10) via articulamentum (8), wherein via institute
The second side for stating carrier introduces the contact disc (18,19) for being used for the layer structure, wherein the first recess portion (14) is introduced into described
In carrier (10), the articulamentum (8) and second semiconductor layer (3), so that first recess portion adjacent described the first half
Conductor layer (2), wherein to be introduced into described first recessed for the first contact disc (18) that will be used to be in electrical contact first semiconductor layer (2)
In portion, so that first contact disc extends through the carrier (10), the articulamentum (8) and second semiconductor layer
(3) it enters in first semiconductor layer (2), and wherein removes the growth substrates.
2. according to the method described in claim 1,
Wherein recess portion is introduced into the articulamentum (8), the carrier (10) and second semiconductor layer (3), wherein institute
Adjacent first semiconductor layer (2) of recess portion is stated, wherein the side of the recess portion is covered by insulating layer, wherein will be used to be in electrical contact
The first contact portion (32) of first semiconductor layer is introduced into the recess portion, wherein the second recess portion is introduced into the carrier
In, wherein the adjacent mirror layer of second recess portion or the adjacent conductive layer for covering the mirror layer, wherein second recess portion
Side covered by another insulating layer, wherein the second contact portion (33) that will be used to be in electrical contact the second semiconductor layer (3) is introduced into
In second recess portion.
3. according to the method described in claim 2,
A. wherein before introducing first contact portion and/or second contact portion, another mirror layer is applied to described the
On the side of one recess portion and/or second recess portion,
B. perhaps wherein use for the light emitted by the active area (16) substantially transparent connecting material or
C. first contact portion (32) is wherein constituted as follows, first contact portion is towards first semiconductor
It is constituted in a manner of mirror surface on the side of layer.
4. according to the method in claim 2 or 3,
Wherein third insulating layer is applied on the carrier, wherein conductive the first contact disc (18) is applied to the third
It on insulating layer, connect, and is wherein applied to conductive the second contact disc (19) described with first contact portion (32)
On third insulating layer, connect with second contact portion (33), wherein first contact disc and second contact disc that
This electrical isolation, wherein the 4th insulating layer is applied on first contact disc, wherein at least partly by second contact disc
Ground is applied on the 4th insulating layer.
5. according to the method described in claim 1,
Wherein the articulamentum (8) is made of electrically insulating material.
6. according to the method described in claim 1,
Wherein the articulamentum is made of binding material.
7. according to the method described in claim 1,
Wherein use semiconductive or conductive material as carrier (10).
8. according to the method described in claim 1,
It wherein uses in the semiconductive or conductive material of form of film as carrier (10).
9. according to the method described in claim 1,
Wherein the growth substrates are removed from the surface of first semiconductor layer, wherein being roughened described the first the half of exposing
The surface of the exposing of conductor layer.
10. according to the method described in claim 1,
Wherein use chip as carrier.
11. according to the method described in claim 1,
Wherein use the thinned chip with thicker fringe region as carrier.
12. a kind of opto-electronic device (21,34,35), the opto-electronic device has carrier (10) and layer structure, the layer knot
Structure has the first semiconductor layer (2) and the second semiconductor layer (3) and active area and mirror layer (4) for generating light,
Wherein the layer structure (2,3) connect via articulamentum (8) with the first side of the carrier (10), and
The first contact portion (32) and second for being in electrical contact the layer structure (2,3) is wherein equipped in the carrier (10)
Contact portion (33), wherein
First and second contact portion (32,33) is oriented to opposite second side from first side of the carrier (10),
And
Wherein the articulamentum (8) is made of electrically insulating material,
First contact portion (32) for being in electrical contact first semiconductor layer (2) is constituted in the first recess portion, wherein
The mirror layer (4), the articulamentum (8), second semiconductor layer (3) and the carrier (10) have described first
Recess portion (14), and
Wherein between the carrier (10) and first semiconductor layer (2) of pending contact, including the carrier
With first semiconductor layer, first contact portion continuously, seamlessly and is integrally formed.
13. one kind has the opto-electronic device (21,34,35) of carrier (10) and layer structure, the layer structure is led with the first half
Body layer (2), the second semiconductor layer (3) and the active area (16) for generating light, wherein
The layer structure is connect via articulamentum (8) with the first side of the carrier (10),
The articulamentum (8) is made of electrically insulating material,
The device has the first contact portion (32) and the second contact portion (33) for being in electrical contact the layer structure,
For being in electrical contact first contact portion (32) of first semiconductor layer (2) locally from the carrier (10)
Back side passes through recess portion (14) and extends to first semiconductor layer (2),
The recess portion in the carrier (10), in the articulamentum (8) and in second semiconductor layer (3) structure
At, and
First contact portion (32) the inside of the recess portion continuously, seamlessly and be integrally formed, so that described
One contact portion passes through the carrier (10), the articulamentum (8) and second semiconductor layer (3) extend to described the first half and lead
In body layer (2).
14. device according to claim 13,
Wherein the mirror layer (4) of the device, the articulamentum (8), second semiconductor layer (3) and the carrier (10) have
The recess portion (14), wherein adjacent first semiconductor layer (2) of the recess portion (14), wherein second semiconductor layer (3)
It is arranged between first semiconductor layer (2) and the carrier (10), wherein the side of the recess portion (14) is by insulating layer
(17) it covers, wherein first contact portion (32) is arranged in the recess portion (14), wherein introducing in the carrier (10)
Another recess portion (15), wherein the adjacent mirror layer (4) of another recess portion (15) or the adjacent conductive layer for covering the mirror layer
(6), wherein the side of another recess portion (15) is covered by insulating layer (17), wherein second contact portion (33) is arranged in institute
It states in another recess portion (15).
15. device according to claim 12 or 13,
It is wherein applied on the carrier (10) insulating layer (17), wherein conductive the first contact disc (18) is applied to described
On insulating layer (17), first contact disc is connect with first contact portion (32), and wherein by the second conductive contact
Disk (19) is applied on the insulating layer (17), and second contact disc is connect with second contact portion (33), and wherein
First and second contact discs (18,19) are electrically separated from each other, wherein another insulating layer (23) is applied on first contact disc,
Wherein second contact disc (19) is also partly applied on another insulating layer (23).
16. device according to claim 12 or 13,
Wherein the carrier (10) is made of semiconductive or conductive material.
17. device according to claim 12 or 13,
Wherein the carrier (10) consists of metal.
18. device according to claim 12 or 13,
Wherein the carrier (10) is constituted in the form of the film being made of metal or semiconductor material.
19. device according to claim 12 or 13,
Wherein the articulamentum (8) has the thickness degree less than 10 μm, and wherein the carrier (10) has less than 100 μm
Thickness degree.
20. device according to claim 19,
Wherein the articulamentum (8) has the thickness degree less than 1 μm.
21. device according to claim 19,
Wherein the carrier (10) has the thickness degree less than 10 μm.
22. device according to claim 12 or 13,
It is provided with substantially transparent connecting material for the light emitted by the active area, and is wherein used
The carrier constituted in a manner of mirror surface on towards the side of the articulamentum is as carrier.
23. device according to claim 12 or 13,
Wherein the carrier (10) along any direction extend transversely be more than be applied to it is on the articulamentum (8), by the first and
The layer structure that second semiconductor layer (2,3) is constituted.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102012217533.4A DE102012217533A1 (en) | 2012-09-27 | 2012-09-27 | Method for producing an optoelectronic component |
| DE102012217533.4 | 2012-09-27 | ||
| PCT/EP2013/069966 WO2014048988A1 (en) | 2012-09-27 | 2013-09-25 | Method for producing an optoelectronic component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104704642A CN104704642A (en) | 2015-06-10 |
| CN104704642B true CN104704642B (en) | 2019-07-16 |
Family
ID=
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101601144A (en) * | 2007-01-31 | 2009-12-09 | 奥斯兰姆奥普托半导体有限责任公司 | Optoelectronic semiconductor chip and being used to is made the method for the contact structures of this type of chip |
| CN102315352A (en) * | 2010-07-08 | 2012-01-11 | 三星Led株式会社 | Light emitting semiconductor device and manufacturing approach thereof |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101601144A (en) * | 2007-01-31 | 2009-12-09 | 奥斯兰姆奥普托半导体有限责任公司 | Optoelectronic semiconductor chip and being used to is made the method for the contact structures of this type of chip |
| CN102315352A (en) * | 2010-07-08 | 2012-01-11 | 三星Led株式会社 | Light emitting semiconductor device and manufacturing approach thereof |
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