CN104702270B - A kind of delay phase-locked loop and its more new control method - Google Patents
A kind of delay phase-locked loop and its more new control method Download PDFInfo
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- CN104702270B CN104702270B CN201510134262.1A CN201510134262A CN104702270B CN 104702270 B CN104702270 B CN 104702270B CN 201510134262 A CN201510134262 A CN 201510134262A CN 104702270 B CN104702270 B CN 104702270B
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Abstract
The present invention discloses a kind of delay phase-locked loop and its more new control method, and the delay phase-locked loop includes delay chain, phase discriminator, feedback circuit, logic control circuit and counter；Input clock signal line connection delay chain and phase discriminator；The output end connection output clock cable of delay chain；The output end of the input connection delay chain of feedback circuit, the output end connection phase discriminator of feedback circuit；The output end connection logic control circuit of phase discriminator, the output end connection delay chain of logic control circuit；The input connection memory control system of counter, the output end connection logic control circuit of counter.The present invention when power-down mode exits, accelerates the renewal speed of delay chain, to ensure that VCLK and DQS rising edge align as early as possible, system operatio is not in mistake by setting counter；After power-supply fluctuation is stable, control delay chain recovers renewal speed, to suppress some less noises on input clock and power supply.
Description
【Technical field】
The invention belongs to PHASE-LOCKED LOOP PLL TECHNIQUE field, more particularly to a kind of delay phase-locked loop and its more new control method.
【Background technology】
Refer to shown in Fig. 1, existing delay phase-locked loop DLL operation principle is：Input clock VCLK postpones into DLL
Chain, output clock is produced after delay, output clock produces feedback clock after feedback circuit, when input clock is with feedback
Clock exports UP or DN signal to DLL logic control circuits, DLL logic control circuits after DLL phase discriminators carry out phase bit comparison
Increasing or decreasing for DLL delay chains is controlled by add drop circuit, the renewal speed of DLL delay chains is controlled by renewal speed circuit
Degree, until input clock and the phase alignment of feedback clock.
When input clock samples the high level of feedback clock, UP=1, DN=0；Input clock samples feedback clock
During low level, DN=1, UP=0.
DLL renewal speed：The initial phase relationship of input clock and feedback clock is as shown in Figure 2.Due to input clock
It is larger with the initial phase difference td0 of feedback clock, so DLL is with a faster speed 1step/ (n*tck) (when representing n
Clock cycle renewal time lag of first order chain) go to update the phase difference of input clock and feedback clock；Tck is the clock cycle.
When the phase difference of input clock and feedback clock is almost 0, as shown in Figure 3.In order to filter input clock and electricity
The noise of some very littles on source, DLL renewal speed can be slack-off, is changed into 1step/ (m*n*tck) from 1step/ (n*tck)
(representing n*m clock cycle renewal time lag of first order chain), i.e., renewal speed is slack-off m times.
The problem of following be present in prior art：
Under normal circumstances, it is rational to change renewal speed after DLL lockings, can effectively filter input clock and power supply
On some very littles noise, keep DLL delay chains stabilization.But after DLL lockings, chip can enter power supply
Close pattern, when power-down mode exits, a larger fluctuation is had on power supply, this fluctuation amplitude and it is lasting when
Between considerably beyond some on input clock and power supply are normal, noise fluctuations of very little, as shown in Figure 4.
It is unstable due to power supply, cause the time delay of DLL delay chains very big change occur, during so as to cause input
Clock VCLK and data aligned signal DQS phase difference are not almost 0, but have a phase difference δ, as shown in Figure 5.
After power-down mode exits, system needs input clock VCLK and data aligned signal DQS rising edge immediately
In aligned condition, if power-supply fluctuation is larger, DLL needs to update the length of DLL delay chains to allow input clock VCLK sums
Alignd as early as possible according to aligned signal DQS rising edge.Now DLL renewal speed is 1step/ (m*n*tck), it is meant that DLL exists
Remove to allow input clock VCLK and data aligned signal DQS rising edge alignment with a very slow speed, if power supply is unstable
Time it is longer, then phase between input clock VCLK and data aligned signal DQS is not all alignd in for a long time,
Mistake just occurs in system operatio.
【The content of the invention】
It is an object of the invention to provide a kind of delay phase-locked loop and its more new control method, is asked with solving above-mentioned technology
Topic.
To achieve these goals, the present invention adopts the following technical scheme that：
A kind of delay phase-locked loop, including delay chain, phase discriminator, feedback circuit, logic control circuit and counter；During input
Clock signal wire connection delay chain and phase discriminator；The output end connection output clock cable of delay chain；The input of feedback circuit
The output end of connection delay chain, the output end connection phase discriminator of feedback circuit；The output end connection logic control circuit of phase discriminator,
The output end connection delay chain of logic control circuit；The input connection memory control system of counter, the output of counter
End connection logic control circuit.
Preferably, the output end of logic control circuit passes through add drop circuit and renewal speed circuit connection delay chain；It is described
Add drop circuit is used for the increase and decrease for controlling delay chain；The renewal speed circuit is used for the renewal speed for changing delay chain.
Preferably, the counter exits signal for receiving the power-down mode that memory control system is sent, and
Export the first signal and the renewal speed of delay chain is controlled by the control of renewal speed circuit to logic control circuit, logic control circuit
It is changed into 1step/ (n*tck) from 1step/ (m*n*tck), accelerates input clock VCLK and data aligned signal DQS rising edge
Alignment；Meanwhile counter is exited to the stable time span of power-supply fluctuation according to power-down mode set in advance and counted
Number, microsyn output secondary signal passes through renewal speed circuit to logic control circuit, logic control circuit to after setting duration
The renewal speed of control control delay chain reverts to 1step/ (m*n*tck)；N and m is positive integer, and m >=2.
Preferably, n=2, m=8.
A kind of more new control method of delay phase-locked loop, specifically includes following steps：After power-down mode exits, deposit
Reservoir control system sends power-down mode and exits signal to counter, and counter exports the first signal and gives logic control electricity
Road, the quickening renewal speed of delay chain is controlled, accelerate input clock VCLK and data aligned signal DQS rising edge alignment, with
It is not in mistake to ensure system operatio；Meanwhile counter is exited to power-supply fluctuation according to power-down mode set in advance
Stable time span is counted, and microsyn output secondary signal is to logic control circuit, control delay to after setting duration
Chain recovers renewal speed.
Relative to prior art, the invention has the advantages that：
The present invention, when power-down mode exits, controls the quickening renewal speed of delay chain by setting counter, with
Ensure that VCLK and DQS rising edge aligns as early as possible, system operatio is not in mistake；After power-supply fluctuation is stable, delay chain is controlled
Recover renewal speed, to suppress some less noises on input clock and power supply.
【Brief description of the drawings】
Fig. 1 is the structural representation of existing delay phase-locked loop；
Fig. 2 is the initial phase schematic diagram of input clock and feedback clock；
Fig. 3 is the phase schematic diagram of input clock and feedback clock after DLL lockings；
Fluctuation schematic diagram when Fig. 4 exits for power-down mode on power supply；
Fig. 5 is because power-supply fluctuation causes the schematic diagram that has phase difference δ between VCLK and DQS；
Fig. 6 is that the renewal speed of more new control method of the invention changes schematic diagram when power-down mode exits；
Fig. 7 is the structural representation of delay phase-locked loop of the present invention.
【Embodiment】
Refer to shown in Fig. 7, a kind of delay phase-locked loop of the present invention, including delay chain, phase discriminator, feedback circuit, add drop electricity
Road, renewal speed circuit, logic control circuit and counter.
Input clock signal line connection delay chain and phase discriminator；The output end connection output clock cable of delay chain；Instead
The output end of the input connection delay chain of current feed circuit, the output end connection phase discriminator of feedback circuit；The output end of phase discriminator connects
Logic control circuit is connect, the output end of logic control circuit passes through add drop circuit and renewal speed circuit connection delay chain；Count
The input connection memory control system of device, receives the power-down mode that memory control system is sent and exits signal, count
The output end connection logic control circuit of number device.
A kind of more new control method of delay phase-locked loop of the present invention, including：After power-down mode exits, memory control
System processed sends power-down mode and exits signal to counter, and counter exports the first signal to logic control circuit, logic
Control circuit is changed into 1step/ (n* by the renewal speed of renewal speed current controlled delay chain from 1step/ (m*n*tck)
tck)；DLL renewal speed is accelerated, and input clock VCLK and data aligned signal DQS rising edge can be allowed to align as early as possible, to protect
It is not in mistake to demonstrate,prove system operatio.Meanwhile counter exited according to power-down mode set in advance it is steady to power-supply fluctuation
Fixed time span is counted, and microsyn output secondary signal is to logic control circuit, logic control electricity to after setting duration
Road is changed into 1step/ (m*n*tck) by the renewal speed of renewal speed current controlled delay chain from 1step/ (n*tck), with suppression
Some less noises on input clock and power supply processed, as shown in Figure 6.
In the present invention, n and m are positive integer, and m >=2.Preferably, n=2, m=8.
Claims (3)
1. a kind of delay phase-locked loop, it is characterised in that including delay chain, phase discriminator, feedback circuit, logic control circuit and counting
Device；Input clock signal line connection delay chain and phase discriminator；The output end connection output clock cable of delay chain；Feedback circuit
Input connection delay chain output end, feedback circuit output end connection phase discriminator；The output end connection logic of phase discriminator
Control circuit, the output end connection delay chain of logic control circuit；The input connection memory control system of counter, is counted
The output end connection logic control circuit of device；
The output end of logic control circuit passes through add drop circuit and renewal speed circuit connection delay chain；The add drop circuit is used
In the increase and decrease of control delay chain；The renewal speed circuit is used for the renewal speed for changing delay chain；
The counter exits signal for receiving the power-down mode that memory control system is sent, and exports the first signal
To logic control circuit, logic control circuit is by the renewal speed of renewal speed current controlled delay chain from 1step/ (m*n*
Tck) it is changed into 1step/ (n*tck), accelerates input clock VCLK and data aligned signal DQS rising edge alignment；Meanwhile count
Device is exited to the stable time span of power-supply fluctuation according to power-down mode set in advance and counted, to after setting duration
The renewal that microsyn output secondary signal passes through renewal speed current controlled delay chain to logic control circuit, logic control circuit
Speed reverts to 1step/ (m*n*tck)；N and m is positive integer, and m >=2.
2. a kind of delay phase-locked loop according to claim 1, it is characterised in that n=2, m=8.
3. the more new control method of a kind of delay phase-locked loop, it is characterised in that based on any one of claim 1 to 2
Delay phase-locked loop, specifically include following steps：After power-down mode exits, memory control system sends power-off mould
Formula exits signal to counter, and counter exports the first signal to logic control circuit, controls the quickening renewal speed of delay chain,
Accelerate input clock VCLK and data aligned signal DQS rising edge alignment, to ensure that system operatio is not in mistake；Together
When, counter is exited to the stable time span of power-supply fluctuation according to power-down mode set in advance and counted, to setting
Microsyn output secondary signal recovers renewal speed to logic control circuit, control delay chain after timing is long.
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| CN201510134262.1A CN104702270B (en) | 2015-03-25 | 2015-03-25 | A kind of delay phase-locked loop and its more new control method |
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| CN201510134262.1A CN104702270B (en) | 2015-03-25 | 2015-03-25 | A kind of delay phase-locked loop and its more new control method |
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| CN104702270B true CN104702270B (en) | 2017-11-10 |
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| CN105281755B (en) * | 2015-11-17 | 2018-05-08 | 西安紫光国芯半导体有限公司 | A kind of delay phase-locked loop and its filtering more new control method |
| CN113541679B (en) * | 2021-09-15 | 2022-01-18 | 浙江力积存储科技有限公司 | Delay locked loop |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102957422A (en) * | 2011-08-30 | 2013-03-06 | 中国科学院电子学研究所 | Digital time delay lock loop circuit |
| CN104283550A (en) * | 2014-09-29 | 2015-01-14 | 山东华芯半导体有限公司 | Delay-locked loop and duty ratio correcting circuit |
| CN204481792U (en) * | 2015-03-25 | 2015-07-15 | 西安华芯半导体有限公司 | A kind of delay phase-locked loop |
-
2015
- 2015-03-25 CN CN201510134262.1A patent/CN104702270B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102957422A (en) * | 2011-08-30 | 2013-03-06 | 中国科学院电子学研究所 | Digital time delay lock loop circuit |
| CN104283550A (en) * | 2014-09-29 | 2015-01-14 | 山东华芯半导体有限公司 | Delay-locked loop and duty ratio correcting circuit |
| CN204481792U (en) * | 2015-03-25 | 2015-07-15 | 西安华芯半导体有限公司 | A kind of delay phase-locked loop |
Non-Patent Citations (1)
| Title |
|---|
| 高精度自动变模控制全数字锁相环研究与设计;刘文;《中国优秀硕士学位论文全文数据库 信息科技辑 》;20130315(第3期);I136-205 * |
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