CN204481792U - A kind of delay phase-locked loop - Google Patents
A kind of delay phase-locked loop Download PDFInfo
- Publication number
- CN204481792U CN204481792U CN201520172956.XU CN201520172956U CN204481792U CN 204481792 U CN204481792 U CN 204481792U CN 201520172956 U CN201520172956 U CN 201520172956U CN 204481792 U CN204481792 U CN 204481792U
- Authority
- CN
- China
- Prior art keywords
- output
- delay chain
- logic control
- control circuit
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model discloses a kind of delay phase-locked loop, and described delay phase-locked loop comprises delay chain, phase discriminator, feedback circuit, logic control circuit sum counter; Input clock signal line connection delay chain and phase discriminator; The output of delay chain connects clock signal line; The output of the input connection delay chain of feedback circuit, the output of feedback circuit connects phase discriminator; The output of phase discriminator connects logic control circuit, the output connection delay chain of logic control circuit; The input connected storage control system of counter, the output of counter connects logic control circuit.The utility model is by arranging counter, and when power-down mode exits, accelerate the renewal speed of delay chain, to ensure that the rising edge of VCLK and DQS aligns as early as possible, Dynamic System there will not be mistake; After power-supply fluctuation is stable, control lag chain recovers renewal speed, to suppress some the less noises on input clock and power supply.
Description
[technical field]
The utility model belongs to PHASE-LOCKED LOOP PLL TECHNIQUE field, particularly a kind of delay phase-locked loop.
[background technology]
Refer to shown in Fig. 1, the operation principle of existing delay phase-locked loop DLL is: input clock VCLK enters DLL delay chain, output clock is produced after postponing, output clock produces feedback clock after feedback circuit, the signal that input clock and feedback clock export UP or DN after DLL phase discriminator carries out phase compare goes increase or the minimizing of control DLL delay chain to DLL logic control circuit, until the phase alignment of input clock and feedback clock.
When input clock samples the high level of feedback clock, UP=1, DN=0; When input clock samples the low level of feedback clock, DN=1, UP=0.
The renewal speed of DLL: the initial phase relationship of input clock and feedback clock as shown in Figure 2.Because the initial phase difference td0 of input clock and feedback clock is comparatively large, thus DLL with one faster speed 1step/ (n*tck) (representing n clock cycle renewal time lag of first order chain) remove the phase difference of renewal input clock and feedback clock; Tck is the clock cycle.
When the phase difference of input clock and feedback clock is almost 0, as shown in Figure 3.In order to filter some the very little noises on input clock and power supply, the renewal speed of DLL can be slack-off, become 1step/ (m*n*tck) (representing that n*m clock cycle upgrades time lag of first order chain) from 1step/ (n*tck), namely renewal speed is slack-off m doubly.
There is following problem in prior art:
Under normal circumstances, it is rational for changing renewal speed after DLL locking, effectively can filter some the very little noises on input clock and power supply, keeps the stable of DLL delay chain.But, after DLL locking, chip can enter into power-down mode, when power-down mode exits, power supply has a larger fluctuation, the amplitude of this fluctuation and duration considerably beyond some on input clock and power supply normally, very little noise fluctuations, as shown in Figure 4.
Due to the instability of power supply, cause occur very large change the time of delay of DLL delay chain, thus cause the phase difference of input clock VCLK and alignment of data signal DQS not to be be almost 0, but have a phase difference δ, as shown in Figure 5.
After power-down mode exits, system needs the rising edge of input clock VCLK and alignment of data signal DQS to be in aligned condition immediately, if power-supply fluctuation is comparatively large, DLL needs the length upgrading DLL delay chain align as early as possible to allow the rising edge of input clock VCLK and alignment of data signal DQS.Now the renewal speed of DLL is 1step/ (m*n*tck), mean that DLL is removing to allow the rising edge alignment of input clock VCLK and alignment of data signal DQS by a very slow speed, if the time of power supply instability is longer, phase place so between input clock VCLK and alignment of data signal DQS is not all alignd in for a long time, and Dynamic System just there will be mistake.
[utility model content]
The purpose of this utility model is to provide a kind of delay phase-locked loop, to solve the problems of the technologies described above.
To achieve these goals, the utility model adopts following technical scheme:
A kind of delay phase-locked loop, comprises delay chain, phase discriminator, feedback circuit, logic control circuit sum counter; Input clock signal line connection delay chain and phase discriminator; The output of delay chain connects clock signal line; The output of the input connection delay chain of feedback circuit, the output of feedback circuit connects phase discriminator; The output of phase discriminator connects logic control circuit, the output connection delay chain of logic control circuit; The input connected storage control system of counter, the output of counter connects logic control circuit.
Preferably, the output of logic control circuit is by increasing/subtracting circuit and renewal speed circuit connection delay chain; Described increasing/subtract the increase and decrease of circuit for control lag chain; Described renewal speed circuit is for changing the renewal speed of delay chain.
Preferably, the power-down mode that described counter sends for reception memorizer control system exits signal, and export the first signal to logic control circuit, logic control circuit becomes 1step/ (n*tck) by the renewal speed of renewal speed current controlled delay chain from 1step/ (m*n*tck), accelerates the rising edge alignment of input clock VCLK and alignment of data signal DQS; Simultaneously, counter exits to the time span that power-supply fluctuation is stable according to the power-down mode preset and counts, after setting duration, microsyn output secondary signal is to logic control circuit, and logic control circuit reverts to 1step/ (m*n*tck) by the renewal speed of renewal speed current controlled delay chain; N and m is positive integer, and m >=2.
Preferably, n=2, m=8.
Relative to prior art, the utility model has following beneficial effect:
The utility model is by arranging counter, and when power-down mode exits, accelerate the renewal speed of delay chain, to ensure that the rising edge of VCLK and DQS aligns as early as possible, Dynamic System there will not be mistake; After power-supply fluctuation is stable, control lag chain recovers to upgrade speed, to suppress some the less noises on input clock and power supply.
[accompanying drawing explanation]
Fig. 1 is the structural representation of existing delay phase-locked loop;
Fig. 2 is the initial phase schematic diagram of input clock and feedback clock;
Fig. 3 is the phase place schematic diagram of input clock and feedback clock after DLL locking;
Fig. 4 is the fluctuation schematic diagram of power-down mode when exiting on power supply;
Fig. 5 is because power-supply fluctuation causes having between VCLK and DQS the schematic diagram of phase difference δ;
Fig. 6 is that the renewal speed of the utility model more new control method changes when power-down mode exits schematic diagram;
Fig. 7 is the structural representation of the utility model delay phase-locked loop.
[embodiment]
Refer to shown in Fig. 7, a kind of delay phase-locked loop of the utility model, comprises delay chain, phase discriminator, feedback circuit, increasing/subtract circuit, renewal speed circuit, logic control circuit sum counter.
Input clock signal line connection delay chain and phase discriminator; The output of delay chain connects clock signal line; The output of the input connection delay chain of feedback circuit, the output of feedback circuit connects phase discriminator; The output of phase discriminator connects logic control circuit, and the output of logic control circuit is by increasing/subtracting circuit and renewal speed circuit connection delay chain; The input connected storage control system of counter, the power-down mode that reception memorizer control system sends exits signal, and the output of counter connects logic control circuit.
The more new control method of this delay phase-locked loop comprises: after power-down mode exits, memory control system sends power-down mode and exits signal to counter, counter exports the first signal to logic control circuit, and logic control circuit becomes 1step/ (n*tck) by the renewal speed of renewal speed current controlled delay chain from 1step/ (m*n*tck); The renewal speed of DLL accelerates, and the rising edge of input clock VCLK and alignment of data signal DQS can be allowed to align as early as possible, to ensure that Dynamic System there will not be mistake.Simultaneously, counter exits to the time span that power-supply fluctuation is stable according to the power-down mode preset and counts, after setting duration, microsyn output secondary signal is to logic control circuit, logic control circuit becomes 1step/ (m*n*tck) by the renewal speed of renewal speed current controlled delay chain from 1step/ (n*tck), to suppress some the less noises on input clock and power supply, as shown in Figure 6.
In the utility model, n and m is positive integer, and m >=2.Preferably, n=2, m=8.
Claims (2)
1. a delay phase-locked loop, is characterized in that, comprises delay chain, phase discriminator, feedback circuit, logic control circuit sum counter; Input clock signal line connection delay chain and phase discriminator; The output of delay chain connects clock signal line; The output of the input connection delay chain of feedback circuit, the output of feedback circuit connects phase discriminator; The output of phase discriminator connects logic control circuit, the output connection delay chain of logic control circuit; The input connected storage control system of counter, the output of counter connects logic control circuit.
2. a kind of delay phase-locked loop according to claim 1, is characterized in that, the output of logic control circuit is by increasing/subtracting circuit and renewal speed circuit connection delay chain; Described increasing/subtract the increase and decrease of circuit for control lag chain; Described renewal speed circuit is for changing the renewal speed of delay chain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520172956.XU CN204481792U (en) | 2015-03-25 | 2015-03-25 | A kind of delay phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520172956.XU CN204481792U (en) | 2015-03-25 | 2015-03-25 | A kind of delay phase-locked loop |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204481792U true CN204481792U (en) | 2015-07-15 |
Family
ID=53637563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520172956.XU Active CN204481792U (en) | 2015-03-25 | 2015-03-25 | A kind of delay phase-locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204481792U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702270A (en) * | 2015-03-25 | 2015-06-10 | 西安华芯半导体有限公司 | Delay phase-locked ring and update control method thereof |
-
2015
- 2015-03-25 CN CN201520172956.XU patent/CN204481792U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702270A (en) * | 2015-03-25 | 2015-06-10 | 西安华芯半导体有限公司 | Delay phase-locked ring and update control method thereof |
| CN104702270B (en) * | 2015-03-25 | 2017-11-10 | 西安紫光国芯半导体有限公司 | A kind of delay phase-locked loop and its more new control method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110336545A (en) | A kind of bidirectional self-adaptive clock circuit for supporting wide frequency ranges | |
| CN100376006C (en) | Semiconductor memory device having advanced data strobe circuit | |
| CN102289246B (en) | Methods and apparatuses for delay-locked loops and phase-locked loops | |
| US20200409444A1 (en) | Power consumption management in protocol-based redrivers | |
| CN101958144A (en) | Method for generating reading enabling signals and storage system adopting same | |
| TWI257066B (en) | Instantaneous frequency-based microprocessor power management | |
| CN103546151A (en) | High-speed DLL (Delay-locked loop) | |
| CN204481792U (en) | A kind of delay phase-locked loop | |
| CN104702270A (en) | Delay phase-locked ring and update control method thereof | |
| CN105280220A (en) | DLL locking process circuit and method for improving DRAM self-refreshing and exiting | |
| CN103440032A (en) | Power-saving system and power-saving method by adjusting CPU (central processing unit) frequency of mobile terminal | |
| CN102347759B (en) | Delay phase-locked loop system and method with self-calibration | |
| CN100417024C (en) | Lock phase loop of low stable error and its correcting circuif | |
| CN205490485U (en) | Detect final clock output's delay phase -locked loop and duty cycle correction circuit | |
| CN102751982B (en) | Clock selection circuit suitable for backboard spending treatment of communication equipment | |
| CN105577173B (en) | A kind of delay phase-locked loop and duty cycle circuit for rectifying for detecting final clock output | |
| CN107733402A (en) | Towards the sequential monitoring unit and monitoring system of nearly threshold value low-voltage | |
| CN101197650B (en) | Clock synchronization device and method | |
| CN105281755A (en) | Delay phase-locked loop and filtering updating and control method of the same | |
| CN205179016U (en) | DLL output circuit | |
| CN203563053U (en) | High-speed DLL (Delay-locked loop) | |
| CN104702273A (en) | Delay phase locked loop for preventing error locking and phase locking method thereof | |
| CN202424687U (en) | Self-adjustable delay locking loop circuit | |
| CN204481793U (en) | A kind of delay phase-locked loop preventing wrong lock | |
| CN204578498U (en) | The phase interpolator improved |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710075 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |