CN104701261A - Transistor forming method - Google Patents

Transistor forming method Download PDF

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Publication number
CN104701261A
CN104701261A CN201310647735.9A CN201310647735A CN104701261A CN 104701261 A CN104701261 A CN 104701261A CN 201310647735 A CN201310647735 A CN 201310647735A CN 104701261 A CN104701261 A CN 104701261A
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substrate
etching
dry etching
shaped groove
hydrogen
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CN104701261B (en
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韩秋华
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2229/00—Indexing scheme for semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, for details of semiconductor bodies or of electrodes thereof, or for multistep manufacturing processes therefor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a transistor forming method comprising the steps of providing a substrate, forming an NMOS gate structure and a PMOS gate structure, dry-etching the substrate to form a U-shaped groove, wet-etching the U-shaped groove to form a sigma-shaped groove, and growing a germanium silicon layer in an epitaxial way in the sigma-shaped groove to form a source region or a drain region. During formation of the U-shaped groove through dry etching, dry etching is completed in two steps, first, first dry etching is carried out on the substrate, and then second dry etching is carried out on the substrate. The second dry etching adopts a reducing gas as an etching gas, and can remove etching additional products generated by the first dry etching. Moreover, very few etching additional products are produced during the second dry etching, so that a clean surface is provided for subsequent wet etching, the formed sigma-shaped groove has a standard shape and a flat surface, and the subsequently formed source region or drain region has a better shape.

Description

The formation method of transistor
Technical field
The present invention relates to semiconductor applications, be specifically related to a kind of formation method of transistor.
Background technology
In existing semiconductor device, adopt the method for stress technique can promote groove carrier mobility in semiconductor device, this method is stretched by physical method or compact silicon lattice reaches raising cmos device carrier mobility to improve transistor performance.
Such as: in substrate corresponding to PMOS transistor source region and drain region, form Σ connected in star, epitaxial growth Ge silicon layer in described Σ connected in star again, carry out ion implantation to described germanium silicon layer and form source region and drain region, the raceway groove of described germanium silicon layer energy pair pmos transistor applies compression.For nmos pass transistor, then form U-shaped groove in substrate corresponding to source region and drain region, epitaxial growth carborundum in described U-shaped groove again, carries out ion implantation to described carborundum and forms source region and drain region, and the raceway groove of described carborundum energy pair nmos transistor applies tensile stress.
With reference to figure 1 and Fig. 2, show the schematic diagram of a kind of Transistor forming method of prior art.Described transistor comprises: substrate 10, isolation structure 11 is set in substrate 10, substrate 10 is divided into PMOS district and nmos area by described isolation structure 11, PMOS district is provided with first grid 12A, the side wall 19A of first grid 12A sidewall, the first hard mask layer 13A at first grid 12A top, nmos area is provided with the second hard mask layer 13B at second grid 12B, second grid 12B top.Described transistor also comprises the dielectric layer 14B being covered in second grid 12B top and sidewall and surface, nmos area, be covered in the photoresist layer 15 on dielectric layer 14B surface, carry out dry etching with photoresist layer 15 and first grid 12A, side wall 14A for the substrate 10 of mask to PMOS district, form U-shaped groove 16.
With reference to figure 2, remove photoresist layer 15, wet etching is carried out to U-shaped groove 16, to form Σ connected in star 17.
Exist afterwards, be used as stressor layers at described Σ connected in star 17 epitaxial growth germanium-silicon layer.
But germanium-silicon layer surface smoothness is poor in prior art, thus have impact on the quality of stressor layers, and then have impact on the performance of transistor.
Summary of the invention
The problem that the present invention solves is being formed in the process for the Σ connected in star of epitaxial growth Ge silicon layer, making Σ connected in star pattern more standard, can optimize the final performance with the transistor in stressor layers source region and drain region formed.
For solving the problem, the invention provides a kind of formation method of transistor, comprising:
Substrate is provided, comprises PMOS district substrate and nmos area substrate;
The nmos area substrate of described substrate forms NMOS grid structure, described PMOS district substrate forms PMOS grid structure;
Σ connected in star is formed in the described PMOS district substrate that described PMOS grid structure exposes;
The step forming Σ connected in star comprises:
Carry out dry etching formation U-shaped groove to the described PMOS district substrate that described PMOS grid structure exposes, described dry etching comprises the first dry etching carried out successively and the second dry etching adopting reducibility gas;
Wet etching is carried out to described U-shaped groove, to form Σ connected in star;
Stressor layers is formed, to form source region or drain region in described Σ connected in star.
Optionally, described substrate adopts silicon substrate, and the step of described first dry etching comprises: adopt the mist comprising hydrogen bromide and chlorine to carry out plasma etching to described PMOS district substrate.
Optionally, the mist comprising hydrogen bromide and chlorine is adopted to comprise the step that described PMOS district substrate carries out plasma etching: the power of etching machine is 100 watts to 1000 watts, air pressure in etching cavity is at 2 millitorr to 20 millitorrs, the flow of hydrogen bromide marks condition milliliter per minute at 10 mark condition milliliter per minutes to 500, and the flow of chlorine marks condition milliliter per minute at 10 mark condition milliliter per minutes to 500.
Optionally, described substrate adopts silicon substrate, described second dry etching step comprise: adopt hydrogen to carry out plasma etching to described PMOS district substrate.
Optionally, hydrogen is adopted to comprise the step that described PMOS district substrate carries out plasma etching: the power of etching machine is 100 watts to 1000 watts, air pressure in etching cavity is at 2 millitorr to 40 millitorrs, and the flow of hydrogen marks condition milliliter per minute at 20 mark condition milliliter per minutes to 500.
Optionally, described substrate adopts silicon substrate, and the step of described second dry etching comprises: adopt the mist of hydrogen and argon gas to carry out plasma etching to described.
Optionally, the mist of hydrogen and argon gas is adopted to comprise the step that described PMOS district substrate carries out plasma etching: the power of plasma etching is 100 watts to 1000 watts, air pressure in etching cavity is at 2 millitorr to 40 millitorrs, the flow of hydrogen marks condition milliliter per minute at 20 mark condition milliliter per minutes to 500, and the flow of argon gas is within 500 mark condition milliliter per minutes.
Optionally, the step that described substrate carries out the first dry etching is comprised: the etch amount of described first dry etching to substrate accounts for dry etching to 70% to 90% of total etch amount of substrate etching.
Optionally, the step that described substrate carries out the second dry etching is comprised: the etch amount of described second dry etching to substrate accounts for dry etching to 10% to 30% of total etch amount of substrate etching.
Optionally, the step of wet etching comprises: adopt Tetramethylammonium hydroxide or potassium hydroxide solution to carry out wet etching to described U-shaped groove.
Compared with prior art, technical scheme of the present invention has the following advantages:
When dry etching forms U-shaped groove, dry etching is divided into two steps, first the first dry etching is carried out to described substrate, carry out the second dry etching again, in the second dry etching, adopt reducibility gas as etching gas, the etching addition product that the first dry etching can be produced is removed, and the etching addition product that the second dry etching produces is considerably less, for follow-up wet etching provides clean surface, make formed Σ connected in star pattern standard and surfacing, stressor layers is formed to form source region or drain region in described Σ connected in star, the performance of transistor can be optimized.
Further, described substrate is silicon substrate, hydrogen is adopted to carry out the second dry etching to described, the etch rate of reducing gas hydrogen to silicon substrate is very fast, main etching reaction product is silane, silane can not be attached to the substrate surface of reaction, so the U-shaped groove cleannes of acquisition are high after making etching complete.
Accompanying drawing explanation
Fig. 1 ~ Fig. 2 is the schematic diagram of prior art Transistor forming method;
Fig. 3 is the flow chart of Transistor forming method of the present invention;
Fig. 4 ~ Fig. 9 is the schematic diagram of the forming process of Transistor forming method of the present invention.
Embodiment
In order to obtain the not high reason of stressor layers growth quality, technique prior art being formed to stressor layers is analyzed.
Prior art is formed in the process of Σ connected in star, first carries out dry etching to substrate and forms U-shaped groove, then carries out wet etching formation Σ connected in star to described U-shaped groove.U-shaped groove (as shown in Figure 1) surface is attached to because dry etching can produce etching addition product, described addition product act as the effect of mask and stops that subsequent wet etches, make the Σ connected in star pattern nonstandard (as shown in Figure 2) formed, thus have impact on the quality of the stressor layers be filled in Σ connected in star, and then result in the not good enough problem of transistor performance.
In order to solve the problems of the technologies described above, the invention provides a kind of formation method of transistor.The step adopting dry etching to form U-shaped groove comprises the first dry etching carried out successively and the second dry etching adopting reducibility gas.So first the first dry etching is carried out to described substrate, carry out the second dry etching again, in the second dry etching, adopt reducibility gas as etching gas, the etching addition product that the first dry etching can be produced is removed, and the etching addition product that the second dry etching produces is considerably less, for follow-up wet etching provides clean surface, the U-shaped groove of such formation and Σ connected in star pattern standard, be of value to the quality improving the stressor layers be filled in Σ connected in star, and then improve the performance of transistor.
With reference to figure 3, show the flow chart of the formation method of Σ shape epitaxial Germanium silicon layer of the present invention, the formation method of Σ connected in star of the present invention comprises following roughly step:
Step S1, provides substrate, substrate is divided into PMOS district substrate, nmos area substrate;
Step S2, the nmos area substrate of described substrate forms NMOS grid structure, and described PMOS district substrate forms PMOS grid structure;
Step S3, carry out dry etching formation U-shaped groove to the described PMOS district substrate that described PMOS grid structure exposes, described dry etching comprises the first dry etching carried out successively and the second dry etching adopting reducibility gas;
Step S4, carries out wet etching to described U-shaped groove, to form Σ connected in star;
Step S5, epitaxial growth stressor layers in described Σ connected in star, to form source region or drain region.
By above-mentioned steps, U-shaped groove and the Σ connected in star of pattern standard can be formed, be of value to the quality improving the stressor layers be filled in Σ connected in star, and then improve the performance of transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to figure 4, perform step S1, substrate 100 is provided, substrate is divided into PMOS district substrate, nmos area substrate, in the present embodiment, described substrate 100 is silicon substrate, in other embodiments, described substrate 100 can also be other substrate such as germanium silicon layer substrate or silicon-on-insulator substrate, does not do any restriction to this present invention.
In described substrate 100, form isolation structure 101, substrate is divided into PMOS district substrate, nmos area substrate by described isolation structure 101, and described PMOS district substrate is for the formation of PMOS, and described nmos area substrate is for the formation of NMOS.
In conjunction with reference to figure 5 to Fig. 7, perform step S2, form NMOS grid structure (not marking) at nmos area substrate, form PMOS grid structure (not marking) at PMOS district substrate.
In the present embodiment, described NMOS grid structure comprises NMOS grid 102B, the first hard mask layer 103B, retains dielectric layer 104B, and described PMOS grid structure comprises PMOS grid 102A, the second hard mask layer 103A, side wall 104A.
Particularly, first form 102B at nmos area substrate, form PMOS grid 102A at PMOS district substrate.
In order to ensure in subsequent epitaxial growth process, described NMOS grid 102B and PMOS grid 102A top can not epitaxial growth Ge silicon layers, after formation NMOS grid 102B and PMOS grid 102A, the first hard mask layer 103B, the second hard mask layer 103A is formed respectively, using the extension barrier layer as NMOS grid 102B and PMOS grid 102A subsequent technique at NMOS grid 102B and PMOS grid 102A top.
In the present embodiment, the material of described first hard mask layer 103B, the second hard mask layer 103A is silicon nitride.In other embodiments, the material of described first hard mask layer 103B, the second hard mask layer 103A can also be the other materials such as silica, silicon oxynitride, and the present invention is not restricted this.
It should be noted that, in other embodiments, also can not form described first hard mask layer 103B, the second hard mask layer 103A, but using the dielectric layer for the formation of side wall as extension barrier layer.
Substrate 100 surface of exposing on NMOS grid 102B, PMOS grid 102A surface and NMOS grid 102B, PMOS grid 102A forms dielectric layer 104.Described dielectric layer 104 is for the formation of the side wall of NMOS grid 102B and PMOS grid 102A.
In the present embodiment, the material of described dielectric layer 104 is silicon nitride.In other embodiments, the material of described dielectric layer 104 can also be the other materials such as silica, silicon oxynitride, and the present invention is not restricted this.
Need because follow-up to carry out dry etching to form U-shaped groove to PMOS district substrate, so block nmos area substrate in advance, sustain damage in dry etching to prevent nmos area substrate.Particularly, dielectric layer surface on described NMOS grid 102B, PMOS grid 102A forms photoresist layer, graphical described photoresist layer is to form patterned photoresist layer 105, described patterned photoresist layer 105 is covered in dielectric layer 104 surface on described nmos area substrate and NMOS grid 102B, and exposes the dielectric layer 104 on the PMOS district of described substrate 100 and PMOS grid 102A.
With described patterned photoresist layer 105 for mask, described dielectric layer 104 is etched, form the side wall 104A being positioned at described PMOS grid 102A sidewall, described dielectric layer 104 blocks at the graphical photoresist layer 105 of the part of nmos area and retains, and is formed and retains dielectric layer 104B.
In conjunction with reference to figure 7, Fig. 8, perform step S3, with described patterned photoresist layer 105, PMOS grid structure for mask, dry etching is carried out to described PMOS district substrate, to form U-shaped groove, described dry etching comprises the first dry etching carried out successively and the second dry etching adopting reducibility gas.
First carry out grade first dry etching to described substrate 100, form the first groove 106, described first groove 106 forms U-shaped groove in the second dry etching afterwards.In the present embodiment, as etching agent, plasma etching is carried out to substrate 100 with the mist of hydrogen bromide and chlorine.
Because the anisotropy adopting the mist of hydrogen bromide and chlorine to carry out etching is better, less to the etching of substrate 100 side direction while etching below substrate 100, so the etch amount of the first dry etching to substrate 100 accounts for dry etching to 70% to 90% of total etch amount of substrate 100, to make the final U-shaped recess sidewall pattern formed better.
It should be noted that, in the step of the first dry etching, also may pass into assist gas except the mist of hydrogen bromide and chlorine as inert gas etc.
In other embodiments, also other gases can be adopted to carry out plasma etching to substrate 100, according to the anisotropic difference of other gas etchings, the etch amount of the first dry etching to substrate 100 accounts for dry etching also can not in 70% to 90% scope to the ratio of total etch amount of substrate 100, and the present invention is not restricted this.
Carry out in first etching cavity being dry-etched in etching machine, in the present embodiment, the power of the etching machine of the first dry etching is 100 watts to 1000 watts, air pressure in etching cavity is at 2 millitorr to 20 millitorrs, the flow of hydrogen bromide marks condition milliliter per minute at 10 mark condition milliliter per minutes to 500, and the flow of chlorine marks condition milliliter per minute at 10 mark condition milliliter per minutes to 500.
After the first dry etching, can adhere to a certain amount of etching addition product 107 on the first groove 106 surface, described addition product 107 comprises: the mist of hydrogen bromide and chlorine and silicon substrate 100 react that formed, easy attachment reaction surface oxide-film, polymer etc.
After the first dry etching, in the same etching cavity of the first dry etching, the second dry etching is carried out to described substrate 100.Particularly, hydrogen is adopted to carry out plasma etching as etching agent to described first groove 106, the etch rate of hydrogen to described substrate 100 is very fast, because hydrogen is reducibility gas, the etching addition products 107 such as the such as oxide-film being attached to the first groove 106 surface can be removed, and etching is continued to described first groove 106, form U-shaped groove 108.
The etch amount of the second dry etching to substrate 100 accounts for dry etching to 10% to 30% of total etch amount of substrate 100 in the present embodiment.
In the present embodiment, the power of the etching machine of the second dry etching is 100 watts to 1000 watts, and the air pressure in etching cavity is at 2 millitorr to 40 millitorrs, and the flow of hydrogen marks condition milliliter per minute at 20 mark condition milliliter per minutes to 500.
In other embodiments, the mist of hydrogen and argon gas also can be adopted to carry out plasma etching to the first groove 106 that described step S6 is formed, wherein the effect of argon gas is the etch rate of adjustment second dry etching to the first groove 106.Because argon gas is inert gas, can not react with silicon substrate 100, improve the ratio that argon gas is shared in mist, the etch rate of the second dry etching can be reduced.
Particularly, during second dry etching such as adopt the mist of hydrogen and argon gas to carry out, the power of etching machine is 100 watts to 1000 watts, air pressure in etching cavity is in the scope of 2 millitorr to 40 millitorrs, the flow of hydrogen is marked in the scope of condition milliliter per minute at 20 mark condition milliliter per minutes to 500, and the flow of argon gas is within 500 mark condition milliliter per minutes.
In other embodiments, other reducibility gas beyond hydrogen also can be adopted to carry out plasma etching to substrate 100.Different owing to etching the mist adopted, the etch amount of the second dry etching to substrate 100 accounts for dry etching also can not in 10% to 30% scope to the ratio of total etch amount of substrate 100, and the present invention is not restricted this.
In the second dry etching, hydrogen and described silicon substrate 100 react, and the reactant of generation is silane, and silane is not easy to be attached to reaction surface.
That is, be also not easy to produce accessory substance while etching addition product 107 can being removed by hydrogen.Thus by the second dry etching, the surface cleanness of the described U-shaped groove 108 of formation is high, for follow-up wet etching provides clean surface.
This sentences hydrogen is that example is described, and can also adopt corresponding reducibility gas for different etachable material.
It should be noted that, after formation U-shaped groove, also need to remove described patterned photoresist layer 105, and the reservation dielectric layer 104B exposed after the described patterned photoresist layer 105 of removal and U-shaped groove 108 are cleaned.Particularly, adopt podzolic gas to carry out cineration technics to described patterned photoresist layer 105, to remove described patterned photoresist layer 105, and adopt the mode of wet-cleaned to clean the reservation dielectric layer 104B exposed and U-shaped groove 108.
With reference to figure 9, perform step S4, wet etching is carried out, to form Σ connected in star 109 to described U-shaped groove 108.
Particularly, Tetramethylammonium hydroxide (TMAH) solution is adopted to carry out wet etching as etchant to described U-shaped groove 108, tetramethyl ammonium hydroxide solution is adopted to be as the benefit of etchant, tetramethyl ammonium hydroxide solution has strong basicity, and etching process is comparatively stable, the Σ connected in star 109 pattern standard of formation.
In other embodiments, the etchant of wet etching can also adopt potassium hydroxide (KOH) solution or other solution, and the present invention is not restricted this.
Carrying out in the process of wet etching to described U-shaped groove 108, described reservation dielectric layer 104B can protect nmos area substrate.
Due to after the second dry etching before, the surface cleanness of described U-shaped groove 108 is high, described U-shaped groove 106 does not have etching addition product when carrying out wet etching stops and carves wet etching, the pattern more standard of the Σ connected in star that the pattern of Σ connected in star 108 of formation is like this formed compared with prior art.
Continue with reference to figure 9, perform step S5, epitaxial growth stressor layers in described Σ connected in star, to form source region or drain region.Particularly, epitaxial growth stressor layers (not shown) in described Σ connected in star, carries out to described stressor layers source region or the drain region that doping forms PMOS.
In the present embodiment, the material of described stressor layers is germanium silicon, for providing compression stress to the raceway groove of PMOS.Form epitaxial growth Ge silicon layer in the Σ connected in star 109 of pattern that method formed more standard in the present invention, can obtain the stressor layers that quality is higher, the stressor layers higher to quality carries out that ion implantation forms source region or drain region and the transistor performance that obtains is better.
Behind the source region forming PMOS and drain region, can also form source region and the drain region of NMOS, the formation source region of NMOS and the method in drain region are this area conventional techniques, and the present invention does not repeat them here.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (10)

1. a formation method for transistor, is characterized in that, comprising:
Substrate is provided, comprises PMOS district substrate and nmos area substrate;
The nmos area substrate of described substrate forms NMOS grid structure, described PMOS district substrate forms PMOS grid structure;
Σ connected in star is formed in the described PMOS district substrate that described PMOS grid structure exposes;
The step forming Σ connected in star comprises:
Carry out dry etching formation U-shaped groove to the described PMOS district substrate that described PMOS grid structure exposes, described dry etching comprises the first dry etching carried out successively and the second dry etching adopting reducibility gas;
Wet etching is carried out to described U-shaped groove, to form Σ connected in star;
Stressor layers is formed, to form source region or drain region in described Σ connected in star.
2. form method as claimed in claim 1, it is characterized in that, described substrate adopts silicon substrate, and the step of described first dry etching comprises: adopt the mist comprising hydrogen bromide and chlorine to carry out plasma etching to described PMOS district substrate.
3. form method as claimed in claim 2, it is characterized in that, the mist comprising hydrogen bromide and chlorine is adopted to comprise the step that described PMOS district substrate carries out plasma etching: the power of etching machine is 100 watts to 1000 watts, air pressure in etching cavity is at 2 millitorr to 20 millitorrs, the flow of hydrogen bromide marks condition milliliter per minute at 10 mark condition milliliter per minutes to 500, and the flow of chlorine marks condition milliliter per minute at 10 mark condition milliliter per minutes to 500.
4. form method as claimed in claim 1, it is characterized in that, described substrate adopts silicon substrate, and the step of described second dry etching comprises: adopt hydrogen to carry out plasma etching to described PMOS district substrate.
5. form method as claimed in claim 4, it is characterized in that, hydrogen is adopted to comprise the step that described PMOS district substrate carries out plasma etching: the power of etching machine is 100 watts to 1000 watts, air pressure in etching cavity is at 2 millitorr to 40 millitorrs, and the flow of hydrogen marks condition milliliter per minute at 20 mark condition milliliter per minutes to 500.
6. form method as claimed in claim 1, it is characterized in that, described substrate adopts silicon substrate, and the step of described second dry etching comprises: adopt the mist of hydrogen and argon gas to carry out plasma etching to described.
7. form method as claimed in claim 6, it is characterized in that, the mist of hydrogen and argon gas is adopted to comprise the step that described PMOS district substrate carries out plasma etching: the power of etching machine is 100 watts to 1000 watts, air pressure in etching cavity is at 2 millitorr to 40 millitorrs, the flow of hydrogen marks condition milliliter per minute at 20 mark condition milliliter per minutes to 500, and the flow of argon gas is within 500 mark condition milliliter per minutes.
8. form method as claimed in claim 1, it is characterized in that, the step of described first dry etching comprises: the etch amount of the first dry etching to substrate accounts for dry etching to 70% to 90% of total etch amount of substrate etching.
9. form method as claimed in claim 1, it is characterized in that, the step of described second dry etching comprises: the etch amount of the second dry etching to substrate accounts for dry etching to 10% to 30% of total etch amount of substrate etching.
10. form method as claimed in claim 1, it is characterized in that, the step of wet etching comprises: adopt Tetramethylammonium hydroxide or potassium hydroxide solution to carry out wet etching to described U-shaped groove.
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