CN104900528B - A kind of method using stress memory technique manufacture FinFET structure - Google Patents
A kind of method using stress memory technique manufacture FinFET structure Download PDFInfo
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- CN104900528B CN104900528B CN201510173993.7A CN201510173993A CN104900528B CN 104900528 B CN104900528 B CN 104900528B CN 201510173993 A CN201510173993 A CN 201510173993A CN 104900528 B CN104900528 B CN 104900528B
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
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- 230000008569 process Effects 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 230000000717 retained effect Effects 0.000 claims abstract description 5
- 238000012545 processing Methods 0.000 claims description 10
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000009471 action Effects 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
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- 239000007788 liquid Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
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- 230000003628 erosive effect Effects 0.000 description 3
- 229960002050 hydrofluoric acid Drugs 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a kind of methods using stress memory technique manufacture FinFET structure, including forming Fin structures and grid and gate lateral wall on substrate, Fin parts other than grid lower channels position are removed, an etching stopping layer and a stressor layers are sequentially formed on the substrate of NMOS area, gate structure is covered, perform a high-temperature annealing process, then, remove stressor layers and etching stopping layer, retained the tensile stress that stressor layers directly act on Fin raceway grooves both sides, and restore to form the part Fin other than grid lower channels position, to form new Fin structures.The present invention makes stressor layers that tensile stress is directly acted on Fin raceway grooves both sides, and causes the stress contact area increase of Fin raceway grooves, and stronger stress effect can be formed to NMOS raceway grooves, so as to obtain higher electron mobility, improves the performance of semiconductor.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology fields, and stress memory skill is utilized more particularly, to a kind of
The method that art manufactures FinFET structure.
Background technology
With the micro sustainable development of super large-scale integration characteristic size, the size of field-effect transistor is also therewith
It is less and less, and the speed operated is also getting faster.Electron transport performance how is effectively improved, improves the driving electricity of circuit element
Stream, which just seems, to become more and more important.
By improving the carrier mobility of channel region, the driving current of cmos device can be increased, improve the property of device
Energy.And a kind of effective mechanism for improving carrier mobility is that stress is generated in channel region.
In general, the mobility of electronics increases with the increase of the tensile stress along electron transfer direction in silicon, and with
It the increase of compression and reduces；On the contrary, the mobility in hole positively charged in silicon is with the compression of hole moving direction
Increase and increase, and reduced with the increase of tensile stress.It therefore, can be by introducing appropriate compression and drawing in channels
Stress, the electron mobility of the hole mobility of PMOS and NMOS is respectively increased.For example, in the manufacturing process of PMOS device
Using the material with compression, and the material with tensile stress is used in NMOS device, to apply suitably to channel region
Stress, so as to improve the mobility of carrier.
It as a result, can be by introducing stress memory technique (Stress Memorization in semiconductor fabrication
Technique, SMT), to change the lattice structure in raceway groove, so as to improve the mobility of carrier in raceway groove.
A kind of existing stress memory technique applied to planar semiconductor device is heavy by side on the semiconductor device
One ply stress material layer of product (for example, silicon nitride etc.) utilizes the stress above photoetching, etch process removal semiconductor devices PMOS
Material layer, and high-temperature annealing process is carried out, so that stress is remembered on the grid of NMOS or gate bottom raceway groove, then remove
Stress material enables stress to retain and improves mobility of the electronics in NMOS, so as to improve the performance of device NMOS area.
From the point of view of existing research, application tensile stress can improve the mobility of electronics on raceway groove, and apply compression then
The mobility in hole can be improved.
However, with the reduction of device size, in the device of the FinFET (fin formula field effect transistor) of such as three-dimensional structure
In part manufacture, due to the complexity of device, above application can not be suitable in the stress memory technique of planar semiconductor device
FinFET structure.It is therefore desirable to a kind of stress memory technique for being suitable for manufacture FinFET structure is developed, and for improving
The electron mobility of NMOS in FinFET structure.
Invention content
It is an object of the invention to overcome drawbacks described above of the existing technology, a kind of utilization stress memory technique system is provided
The method for making FinFET structure can improve the electron mobility of NMOS in FinFET structure.
To achieve the above object, technical scheme is as follows：
A kind of method using stress memory technique manufacture FinFET structure includes the following steps：
Step S01：There is provided semi-conductive substrate, over the substrate formed strip Fin structures and across and three faces
Surround the grid and gate lateral wall of Fin；
Step S02：Fin parts other than the grid lower channels position are removed；
Step S03：An etching stopping layer and a stressor layers are sequentially formed on the substrate of NMOS area, by the grid
Pole structure covering, enables etching stopping layer and stressor layers to abut the both sides of raceway groove, directly to apply tensile stress to raceway groove both sides,
Also, contact action area of the stress in raceway groove both sides is also significantly increased；
Step S04：A high-temperature annealing process is performed, then, the stressor layers and etching stopping layer is removed, makes the stress
The tensile stress that layer directly acts on Fin raceway grooves both sides is retained；
Step S05：Restore to form the part Fin other than the grid lower channels position, to form new Fin structures.
Preferably, the Fin structures are made of monocrystalline silicon.
Preferably, the grid is made of polysilicon, metal or metal silicide.
Preferably, the etching stopping layer is silica or silicon oxynitride.
Preferably, the stressor layers are silicon nitride or silicon carbide with tensile stress.
Preferably, in step S05, restore to be formed using epitaxial growth technology other than the grid lower channels position
Part Fin.
Preferably, the thickness of the etching stopping layer is 5~100A.
Preferably, the high annealing is carried out using rapid thermal anneal process or flash anneal technique.
Preferably, in step S04, the stressor layers and etching stopping layer are removed using wet processing.
Preferably, when carrying out the wet processing, the stressor layers are removed using phosphoric acid, the erosion is removed using hydrofluoric acid
Carve stop-layer.
Beneficial effects of the present invention are：Stress memory technique is applied to the NMOS of FinFET structure, by removing grid
The part Fin of both sides makes stressor layers that tensile stress is directly acted on Fin raceway grooves both sides, and causes the stress contact surface of Fin raceway grooves
Product increase, can form NMOS raceway grooves stronger stress effect, so as to obtain higher electron mobility, therefore improve NMOS
And the performance of FinFET.
Description of the drawings
Fig. 1 is a kind of flow chart of method using stress memory technique manufacture FinFET structure of the present invention；
Fig. 2~Fig. 7 is the process structure signal that a preferred embodiment of the present invention manufactures FinFET structure according to the method for Fig. 1
Figure.
Specific embodiment
Below in conjunction with the accompanying drawings, the specific embodiment of the present invention is described in further detail.
It should be noted that in following specific embodiments, when embodiments of the present invention are described in detail, in order to clear
Ground represents the structure of the present invention in order to illustrate, special not draw to the structure in attached drawing according to general proportion, and carried out part
Amplification, deformation and simplified processing, therefore, should avoid in this, as limitation of the invention to understand.
In specific embodiment of the invention below, referring to Fig. 1, Fig. 1, which is that the present invention is a kind of, utilizes stress memory skill
The flow chart of the method for art manufacture FinFET structure；Meanwhile Fig. 2~Fig. 7 is please referred to, Fig. 2~Fig. 7 is that the present invention one is preferable
Embodiment manufactures the process structure schematic diagram of FinFET structure according to the method for Fig. 1.As shown in Figure 1, a kind of utilization of the present invention
The method that stress memory technique manufactures FinFET structure, includes the following steps：
As shown in frame 01, step S01：Semi-conductive substrate is provided, formed over the substrate Fin structures and grid and
Gate lateral wall.
Please refer to Fig. 2.The substrate 1 of the present invention is chosen as the silicon chip of monocrystalline or SOI (silicon-on-insulator) substrate.With SOI works
For skill, but SOI technology is not limited to, first, the existing known technology of industry can be used, such as extension is used in SOI substrate 1
Growth technique forms Fin structure sheafs.Optionally, the Fin structure sheafs in the present embodiment can be made of monocrystalline silicon.Then,
Being coated with, being exposed and developed for photoresist is carried out, the Fin structure sheafs are patterned, and etches the monocrystalline silicon for forming strip
Fin structures 2 (fin-shaped semiconductor structure).Next, the existing known technology of industry can be equally used, in Fin structures 2 successively
It forms grid oxygen (not shown in figure, refer to 5 locations of structures of grid oxygen in Fig. 5), grid 4 and forms grid in 4 both sides of grid
Side wall 3, and be developed across and three bread enclose the gate structure 6 of Fin2.As an optional embodiment, the material of the grid 4
It can be made of polysilicon, metal or metal silicide.For example, LPCVD techniques can be used to form polycrystalline silicon gate layer, so
Afterwards, using photoetching process, being coated with, being exposed and developed for photoresist is carried out, the polysilicon layer is patterned, and passes through erosion
Carving technology removes extra polysilicon segment, is developed across and surrounds the grid 4 of the Fin structures 2.
As shown in frame 02, step S02：Fin parts other than the grid lower channels position are removed.
Please refer to Fig. 3.Next, for effect of the strengthening subsequent stressor layers to raceway groove, need first to 4 lower channels of grid
Fin (i.e. exposing the Fin structure divisions except 3 bottom of grid 4 and side wall shown in Fig. 2) other than position makees part removal processing,
So that the both sides for enabling raceway groove are stressed the direct effect of layer tensile stress.Fin knots in this part can be covered using photoresist
Other than structure do not need to removal region, then, then using dry method etch technology carve fall needed for remove part Fin.Fin structures
2 after etching, is left the Fin portions other than the Fin parts 2-1 at raceway groove (diagram vertical portion) and raceway groove Fin part 2-1
Divide 2-2 (diagram horizontal component).
As shown in frame 03, step S03：An etching stopping layer and a stress are sequentially formed on the substrate of NMOS area
Layer, the gate structure is covered.
Please refer to Fig. 4 and Fig. 5.Fig. 5 is the device profile structure diagram formed in the step S03 corresponding with Fig. 4.It connects down
Come, it, can first one etching stopping layer 7 of deposited overall and a stressor layers 8, and the gate structure 6 is covered successively on the substrate 1
Lid.Optionally, cvd silicon oxide may be used in the etching stopping layer 7 or silicon oxy-nitride material is formed；The stressor layers 8 can be with
It is formed using silicon nitride of the deposition with tensile stress or carbofrax material.As a preferred embodiment, the etching can be stopped
Only the deposition thickness control of layer 7 is in the range of 5~100A.Then, the stressor layers of PMOS area covering are removed by etch process
And etching stopping layer, retain stressor layers 8 and etching stopping layer 7 that diagram NMOS area covers.As an optional embodiment,
The stressor layers and etching stopping layer of wet processing removal PMOS area covering can be used.Further, it is described wet in progress
During method technique, can be used phosphoric acid as etching liquid come remove PMOS area covering the stressor layers and using hydrofluoric acid
The etching stopping layer is removed as etching liquid.
From fig. 5, it can be seen that since the Fin other than 6 lower channels position of gate structure has been partially removed (remaining diagram
The Fin part 2-2 other than Fin parts 2-1 and raceway groove Fin part 2-1 at raceway groove), make what is subsequently deposited on substrate 1
Etching stopping layer 7 and stressor layers 8 can abut the both sides of raceway groove, and stressor layers 8 directly can apply tensile stress to raceway groove both sides；And
And contact action area of the stress in raceway groove both sides also obtains significantly increase (this is because the Fin other than raceway groove is partly gone
Remove and expose the reason of the vertical plane of Fin parts 2-1), so as to form stronger stress effect to raceway groove, therefore, can obtain
Higher electron mobility.There is conventional 5 structure of grid oxygen between grid and Fin structures.
As shown in frame 04, step S04：A high-temperature annealing process is performed, then, removes the stressor layers and etch stop
Layer, is retained the tensile stress that the stressor layers directly act on Fin raceway grooves both sides.
Please refer to Fig. 6 (Fig. 6 is consistent with the graphic structure of Fig. 3).Next, by performing a high-temperature annealing process, make
8 material of stressor layers, such as silicon nitride or silicon carbide are in high annealing with the tensile stress formed to raceway groove both sides.So
Afterwards, the stressor layers 8 and etching stopping layer 7 are removed.Since the stressor layers and etching stopping layer of PMOS area covering are before
It is removed, so, the stressor layers and etching stopping layer that this step need to only cover remaining NMOS area are removed.Make
For an optional embodiment, the stressor layers and etching stopping layer of wet processing removal NMOS area covering can be used.Into
When carrying out the wet processing, phosphoric acid can be used as etching liquid to remove the stressor layers and using hydrogen in one step
Fluoric acid removes the etching stopping layer as etching liquid.After Fig. 6 displays remove the stressor layers 8 and etching stopping layer 7
Device architecture has reverted to the state consistent with Fig. 3.
It is acted on by high annealing, even if after the stressor layers are removed from raceway groove both sides, can also make the stressor layers
The tensile stress for directly acting on Fin raceway grooves both sides is retained, you can raceway groove is made to still remain in by tensile stress useful effect
State.As an optional embodiment, rapid thermal annealing (rapid thermal can be used in the high annealing
Anneal, RTA) technique or flash anneal (Flash Anneal) technique carries out, and extremely short processing time can effectively avoid height
Temperature is to the adverse effect of device other structures.
As shown in frame 05, step S05：Restore to form the part Fin other than the grid lower channels position, it is new to be formed
Fin structures.
Please refer to Fig. 7.After raceway groove being made to obtain higher electron mobility by action of pulling stress, next, needing
Original Fin structures being partially removed are restored, to form the inherent function of FinFET.It is optional real as one
Apply mode, using epitaxial growth technology, on the position of the remaining Fin parts 2-2 of two lateral erosion of raceway groove (gate structure 6) after
The new Fin2-3 of continuous growth, until restoring original Fin structures 2 in Fig. 2 completely.Next, it can proceed with FinFET devices
The manufacture of part subsequent technique.
In this way, the above method using the present invention, you can by stress memory technique from the application to planar semiconductor device,
On the NMOS for further applying three-dimensional FinFET structure.By first removing the part Fin of grid both sides, and by raceway groove two
Side deposition stress layer makes stressor layers that tensile stress is directly acted on Fin raceway grooves both sides, and causes the stress contact surface of Fin raceway grooves
Product increase, can form NMOS raceway grooves stronger stress effect, so as to obtain higher electron mobility；Later, by again
Restore to generate original Fin structures, to form complete FinFET structure, make NMOS in FinFET performance obtained it is bright
It is aobvious to improve.
Above-described to be merely a preferred embodiment of the present invention, the embodiment is not to be protected to limit the patent of the present invention
Range, therefore the equivalent structure variation that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
- A kind of 1. method using stress memory technique manufacture FinFET structure, which is characterized in that include the following steps：Step S01：There is provided semi-conductive substrate, over the substrate formed strip Fin structures and across and three bread enclose The grid and gate lateral wall of Fin；Step S02：Fin parts other than the grid lower channels position are removed；Step S03：An etching stopping layer and a stressor layers are sequentially formed on the substrate of NMOS area, by the grid knot Structure covers, and etching stopping layer and stressor layers is enable to abut the both sides of raceway groove, directly to apply tensile stress to raceway groove both sides, and And contact action area of the stress in raceway groove both sides is also significantly increased；Step S04：A high-temperature annealing process is performed, then, removes the stressor layers and etching stopping layer, makes the stressor layers straight It connects and acts on the tensile stresses of Fin raceway grooves both sides and retained；Step S05：Restore to form the part Fin other than the grid lower channels position, to form new Fin structures.
- 2. the method according to claim 1 using stress memory technique manufacture FinFET structure, which is characterized in that described Fin structures are made of monocrystalline silicon.
- 3. the method according to claim 1 using stress memory technique manufacture FinFET structure, which is characterized in that described Grid is made of polysilicon, metal or metal silicide.
- 4. the method according to claim 1 using stress memory technique manufacture FinFET structure, which is characterized in that described Etching stopping layer is silica or silicon oxynitride.
- 5. the method according to claim 1 using stress memory technique manufacture FinFET structure, which is characterized in that described Stressor layers are silicon nitride or silicon carbide with tensile stress.
- 6. the method according to claim 1 using stress memory technique manufacture FinFET structure, which is characterized in that step In S05, the part Fin other than the grid lower channels position is formed to restore using epitaxial growth technology.
- 7. the method using stress memory technique manufacture FinFET structure according to claim 1 or 4, which is characterized in that The thickness of the etching stopping layer is 5~100A.
- 8. the method according to claim 1 using stress memory technique manufacture FinFET structure, which is characterized in that described High annealing is carried out using rapid thermal anneal process or flash anneal technique.
- 9. the method according to claim 1 using stress memory technique manufacture FinFET structure, which is characterized in that step In S04, the stressor layers and etching stopping layer are removed using wet processing.
- 10. the method according to claim 9 using stress memory technique manufacture FinFET structure, which is characterized in that into During the row wet processing, the stressor layers are removed using phosphoric acid, the etching stopping layer is removed using hydrofluoric acid.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100505188C (en) * | 2006-04-21 | 2009-06-24 | 国际商业机器公司 | Method for forming FET |
| US8445334B1 (en) * | 2011-12-20 | 2013-05-21 | International Business Machines Corporation | SOI FinFET with recessed merged Fins and liner for enhanced stress coupling |
| CN103247535A (en) * | 2012-02-08 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Dislocation SMT for FinFET device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100505188C (en) * | 2006-04-21 | 2009-06-24 | 国际商业机器公司 | Method for forming FET |
| US8445334B1 (en) * | 2011-12-20 | 2013-05-21 | International Business Machines Corporation | SOI FinFET with recessed merged Fins and liner for enhanced stress coupling |
| CN103247535A (en) * | 2012-02-08 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Dislocation SMT for FinFET device |
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