CN104900528A - Method for manufacturing FinFET structure by stress memorization technique - Google Patents
Method for manufacturing FinFET structure by stress memorization technique Download PDFInfo
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- CN104900528A CN104900528A CN201510173993.7A CN201510173993A CN104900528A CN 104900528 A CN104900528 A CN 104900528A CN 201510173993 A CN201510173993 A CN 201510173993A CN 104900528 A CN104900528 A CN 104900528A
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 238000012545 processing Methods 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000000717 retained effect Effects 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 239000000463 material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000006835 compression Effects 0.000 description 5
- 238000007906 compression Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 235000008429 bread Nutrition 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a method for manufacturing a FinFET structure by a stress memorization technique. The method comprises the following steps: forming a Fin structure, gates and gate side walls on a substrate, removing the Fin parts outside the channels in the lower parts of the gates, sequentially forming an etching stop layer and a stress layer on the substrate in an NMOS area to cover the gate structures, and performing a high-temperature annealing process; and then, removing the stress layer and the etching stop layer, retaining the tensile stress directly applied by the stress layer to the two sides of the Fin channels, and restoring part of the Fins outside the channels in the lower parts of the gates to form a new Fin structure. According to the invention, the stress layer directly applies tensile stress to the two sides of the Fin channels, the stress contact area of the Fin channels is increased, a stronger stress effect can be achieved on an NMOS channel, higher electron mobility is gained, and the performance of semiconductors is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, more specifically, relate to a kind of method utilizing stress memory technique to manufacture FinFET structure.
Background technology
Along with the micro sustainable development of very lagre scale integrated circuit (VLSIC) characteristic size, the size of field-effect transistor is also thereupon more and more less, and the speed of operation is also more and more faster.How effectively improving electron transport performance, the drive current improving circuit element is just seeming and is becoming more and more important.
By improving the carrier mobility of channel region, the drive current of cmos device can be increased, improving the performance of device.And a kind of effective mechanism improving carrier mobility produces stress in channel region.
Generally speaking, in silicon, the mobility of electronics increases along with the increase of the tension stress along electron transfer direction, and reduces along with the increase of compression; On the contrary, in silicon, the mobility in the hole of positively charged increases along with the increase of the compression of hole moving direction, and reduces along with the increase of tension stress.Therefore, by introducing suitable compression and tension stress in channels, the hole mobility of PMOS and the electron mobility of NMOS can be improved respectively.Such as, in the manufacturing process of PMOS device, adopt the material with compression, and in nmos device, adopt the material with tensile stress, to apply suitable stress to channel region, thus improve the mobility of charge carrier.
Thus, by introducing stress memory technique (Stress Memorization Technique, SMT) in semiconductor fabrication, change the lattice structure in raceway groove, thus improve the mobility of charge carrier in raceway groove.
Existing a kind of stress memory technique being applied to planar semiconductor device, deposit one deck stress material layer (such as by square on the semiconductor device, silicon nitride etc.), utilize the stress material layer above photoetching, etch process removal semiconductor device PMOS, and carry out high-temperature annealing process, remembered on the grid or gate bottom raceway groove of NMOS to make stress, then stress material is removed, stress retained and improves the mobility of electronics at NMOS, thus improve the performance of device NMOS area.
From existing research, raceway groove applies the mobility that tension stress can improve electronics, apply the mobility that compression then can improve hole.
But, along with the reduction of device size, in the device of the FinFET (fin formula field effect transistor) of such as three-dimensional structure manufactures, due to the complexity of device, the above-mentioned stress memory technique being applied to planar semiconductor device, can not be applicable to FinFET structure.So, need to develop a kind of stress memory technique being applicable to manufacture FinFET structure, and for improving the electron mobility of NMOS in FinFET structure.
Summary of the invention
The object of the invention is to the above-mentioned defect overcoming prior art existence, a kind of method utilizing stress memory technique to manufacture FinFET structure is provided, the electron mobility of NMOS in FinFET structure can be improved.
For achieving the above object, technical scheme of the present invention is as follows:
Utilize stress memory technique to manufacture a method for FinFET structure, comprise the following steps:
Step S01: provide semi-conductive substrate, forms Fin structure and grid and gate lateral wall over the substrate;
Step S02: the Fin part beyond described grid lower channels position is removed;
Step S03: form an etching stopping layer and a stressor layers successively on the described substrate of NMOS area, described grid structure is covered;
Step S04: perform a high-temperature annealing process, then, removes described stressor layers and etching stopping layer, and the tension stress making described stressor layers directly act on Fin raceway groove both sides is retained;
Step S05: recover to form the part Fin beyond described grid lower channels position, to form new Fin structure.
Preferably, described Fin structure is made up of monocrystalline silicon.
Preferably, described grid is made up of polysilicon, metal or metal silicide.
Preferably, described etching stopping layer is silica or silicon oxynitride.
Preferably, described stressor layers is silicon nitride or the carborundum with tension stress.
Preferably, in step S05, utilize epitaxial growth technology to recover the part Fin formed beyond described grid lower channels position.
Preferably, the thickness of described etching stopping layer is 5 ~ 100A.
Preferably, described high annealing adopts rapid thermal anneal process or flash anneal technique to carry out.
Preferably, in step S04, wet processing is adopted to remove described stressor layers and etching stopping layer.
Preferably, when carrying out described wet processing, adopt phosphoric acid to remove described stressor layers, adopt hydrofluoric acid to remove described etching stopping layer.
Beneficial effect of the present invention is: NMOS stress memory technique being applied to FinFET structure, by removing the part Fin of grid both sides, stressor layers is made tension stress to be directly acted on Fin raceway groove both sides, and the stress contact area of Fin raceway groove is increased, stronger stress effect can be formed to NMOS raceway groove, thus obtain higher electron mobility, therefore improve the performance of NMOS and FinFET.
Accompanying drawing explanation
Fig. 1 is a kind of flow chart utilizing stress memory technique to manufacture the method for FinFET structure of the present invention;
Fig. 2 ~ Fig. 7 is that a preferred embodiment of the present invention manufactures the process structure schematic diagram of FinFET structure according to the method for Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
It should be noted that, in following embodiment, when describing embodiments of the present invention in detail, in order to clearly represent structure of the present invention so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, distortion and simplify processes, therefore, should avoid being understood in this, as limitation of the invention.
In following the specific embodiment of the present invention, refer to Fig. 1, Fig. 1 is a kind of flow chart utilizing stress memory technique to manufacture the method for FinFET structure of the present invention; Meanwhile, incorporated by reference to consulting Fig. 2 ~ Fig. 7, Fig. 2 ~ Fig. 7 is that a preferred embodiment of the present invention manufactures the process structure schematic diagram of FinFET structure according to the method for Fig. 1.As shown in Figure 1, a kind of method utilizing stress memory technique to manufacture FinFET structure of the present invention, comprises the following steps:
As shown in frame 01, step S01: provide semi-conductive substrate, forms Fin structure and grid and gate lateral wall over the substrate.
Refer to Fig. 2.Substrate 1 of the present invention is chosen as silicon chip or SOI (silicon-on-insulator) substrate of monocrystalline.For SOI technology, but be not limited to SOI technology, first, the existing known technology of industry can be adopted, SOI substrate 1 adopts such as epitaxial growth technology to form Fin structure sheaf.Alternatively, the described Fin structure sheaf in the present embodiment can be made up of monocrystalline silicon.Then, carry out the coating of photoresist, exposure and development, described Fin structure sheaf is carried out graphically, and etching forms the monocrystalline silicon Fin structure 2 (fin-shaped semiconductor structure) of strip.Next, the existing known technology of industry can be adopted equally, Fin structure 2 is formed grid oxygen successively (do not show in figure, refer to grid oxygen 5 locations of structures in Fig. 5), grid 4 and form gate lateral wall 3 in grid 4 both sides, and formed across and three bread enclose the grid structure 6 of Fin2.As an optional embodiment, the material of described grid 4 can be made up of polysilicon, metal or metal silicide.Such as, LPCVD technique can be adopted to form polycrystalline silicon gate layer, then, adopt photoetching process, carry out the coating of photoresist, exposure and development, described polysilicon layer is carried out graphically, and removes unnecessary polysilicon segment by etch process, form across and surround the grid 4 of described Fin structure 2.
As shown in frame 02, step S02: the Fin part beyond described grid lower channels position is removed.
Refer to Fig. 3.Next, in order to strengthening subsequent stressor layers is to the effect of raceway groove, need first to make part Transformatin, to enable the both sides of raceway groove be subject to the direct effect of stressor layers tension stress to the Fin (namely exposing the Fin structure division outside bottom grid 4 and sidewall 3 shown in Fig. 2) beyond grid 4 lower channels position.Photoresist can be utilized to cover the region not needing to remove beyond this part Fin structure, then, then adopt dry method etch technology to carve the required part Fin removed.Fin structure 2 after etching, remaining be positioned at raceway groove place Fin part 2-1 (diagram vertical portion) and raceway groove Fin part 2-1 beyond Fin part 2-2 (diagram horizontal component).
As shown in frame 03, step S03: form an etching stopping layer and a stressor layers successively on the described substrate of NMOS area, described grid structure is covered.
Refer to Fig. 4 and Fig. 5.Fig. 5 is the device profile structural representation formed in the step S03 corresponding with Fig. 4.Next, on described substrate 1, can first deposited overall one etching stopping layer 7 and a stressor layers 8 successively, and described grid structure 6 is covered.Alternatively, described etching stopping layer 7 can adopt cvd silicon oxide or silicon oxy-nitride material to be formed; Described stressor layers 8 can adopt deposition to have silicon nitride or the carbofrax material formation of tension stress.As a preferred embodiment, the deposit thickness of described etching stopping layer 7 can be controlled the scope at 5 ~ 100A.Then, removed stressor layers and the etching stopping layer of PMOS area covering by etch process, retain stressor layers 8 and the etching stopping layer 7 of the covering of diagram NMOS area.As an optional execution mode, wet processing can be adopted to remove described stressor layers and the etching stopping layer of PMOS area covering.Further, when carrying out described wet processing, phosphoric acid can be adopted to remove the described stressor layers of PMOS area covering as etching liquid, and adopt hydrofluoric acid to remove described etching stopping layer as etching liquid.
As can be seen from Figure 5, because the Fin beyond grid structure 6 lower channels position is partially removed (remaining diagram is positioned at the Fin part 2-2 beyond the Fin part 2-1 at raceway groove place and raceway groove Fin part 2-1), make the follow-up etching stopping layer 7 that deposits on substrate 1 and stressor layers 8 can near the both sides of raceway groove, stressor layers 8 directly can apply tension stress to raceway groove both sides; And, stress the contact action area of raceway groove both sides also significantly increased (this be due to raceway groove beyond Fin be partially removed and expose the cause of the vertical plane of Fin part 2-1), thus stronger stress effect is formed to raceway groove, therefore, higher electron mobility can be obtained.There is conventional grid oxygen 5 structure between grid and Fin structure.
As shown in frame 04, step S04: perform a high-temperature annealing process, then, removes described stressor layers and etching stopping layer, and the tension stress making described stressor layers directly act on Fin raceway groove both sides is retained.
Refer to Fig. 6 (graphic structure of Fig. 6 and Fig. 3 is consistent).Next, by performing a high-temperature annealing process, make described stressor layers 8 material, such as silicon nitride or carborundum have the tension stress formed raceway groove both sides when high annealing.Then, described stressor layers 8 and etching stopping layer 7 is removed.The stressor layers covered due to PMOS area and etching stopping layer are being removed, before so the stressor layers that this step only need cover remaining NMOS area and etching stopping layer are removed.As an optional execution mode, wet processing can be adopted to remove described stressor layers and the etching stopping layer of NMOS area covering.Further, when carrying out described wet processing, phosphoric acid can be adopted to remove described stressor layers as etching liquid, and adopt hydrofluoric acid to remove described etching stopping layer as etching liquid.Fig. 6 shows the device architecture after removing described stressor layers 8 and etching stopping layer 7 and has reverted to the state consistent with Fig. 3.
By high annealing effect, even if after described stressor layers being removed from raceway groove both sides, the tension stress that described stressor layers also can be made to directly act on Fin raceway groove both sides is retained, and raceway groove can be made still to remain on the state being subject to tension stress useful effect.As an optional execution mode, described high annealing can adopt rapid thermal annealing (rapid thermal anneal, RTA) technique or flash anneal (Flash Anneal) technique are carried out, and its extremely short processing time can effectively avoid high temperature to the adverse effect of other structures of device.
As shown in frame 05, step S05: recover to form the part Fin beyond described grid lower channels position, to form new Fin structure.
Refer to Fig. 7.After made raceway groove obtain higher electron mobility by action of pulling stress, next, need to recover original Fin structure be partially removed, to form the inherent function of FinFET.As an optional execution mode, can utilize epitaxial growth technology, the Fin2-3 that continued growth is new on the position of the remaining Fin part 2-2 of raceway groove (grid structure 6) both sides etching, until recover original Fin structure 2 in Fig. 2 completely.Next, the manufacture of FinFET subsequent technique can be proceeded.
Like this, adopt said method of the present invention, by stress memory technique from the application to planar semiconductor device, can be applied to further on the NMOS of three-dimensional FinFET structure.By first removing the part Fin of grid both sides, and by depositing stressor layers in raceway groove both sides, stressor layers is made tension stress to be directly acted on Fin raceway groove both sides, and the stress contact area of Fin raceway groove is increased, stronger stress effect can be formed to NMOS raceway groove, thus obtain higher electron mobility; Afterwards, by again recovering to generate original Fin structure, form complete FinFET structure, the performance of NMOS in FinFET is significantly improved.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. utilize stress memory technique to manufacture a method for FinFET structure, it is characterized in that, comprise the following steps:
Step S01: provide semi-conductive substrate, forms Fin structure and grid and gate lateral wall over the substrate;
Step S02: the Fin part beyond described grid lower channels position is removed;
Step S03: form an etching stopping layer and a stressor layers successively on the described substrate of NMOS area, described grid structure is covered;
Step S04: perform a high-temperature annealing process, then, removes described stressor layers and etching stopping layer, and the tension stress making described stressor layers directly act on Fin raceway groove both sides is retained;
Step S05: recover to form the part Fin beyond described grid lower channels position, to form new Fin structure.
2. the method utilizing stress memory technique to manufacture FinFET structure according to claim 1, it is characterized in that, described Fin structure is made up of monocrystalline silicon.
3. the method utilizing stress memory technique to manufacture FinFET structure according to claim 1, it is characterized in that, described grid is made up of polysilicon, metal or metal silicide.
4. the method utilizing stress memory technique to manufacture FinFET structure according to claim 1, it is characterized in that, described etching stopping layer is silica or silicon oxynitride.
5. the method utilizing stress memory technique to manufacture FinFET structure according to claim 1, it is characterized in that, described stressor layers is silicon nitride or the carborundum with tension stress.
6. the method utilizing stress memory technique to manufacture FinFET structure according to claim 1, is characterized in that, in step S05, utilize epitaxial growth technology to recover the part Fin formed beyond described grid lower channels position.
7. the stress memory technique that utilizes according to claim 1 or 4 manufactures the method for FinFET structure, and it is characterized in that, the thickness of described etching stopping layer is 5 ~ 100A.
8. the method utilizing stress memory technique to manufacture FinFET structure according to claim 1, is characterized in that, described high annealing adopts rapid thermal anneal process or flash anneal technique to carry out.
9. the method utilizing stress memory technique to manufacture FinFET structure according to claim 1, is characterized in that, in step S04, adopts wet processing to remove described stressor layers and etching stopping layer.
10. the method utilizing stress memory technique to manufacture FinFET structure according to claim 9, is characterized in that, when carrying out described wet processing, adopts phosphoric acid to remove described stressor layers, adopts hydrofluoric acid to remove described etching stopping layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653623A (en) * | 2020-06-19 | 2020-09-11 | 上海华力集成电路制造有限公司 | Fin type transistor structure |
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|---|---|---|---|---|
| CN100505188C (en) * | 2006-04-21 | 2009-06-24 | 国际商业机器公司 | Method for forming FET |
| US8445334B1 (en) * | 2011-12-20 | 2013-05-21 | International Business Machines Corporation | SOI FinFET with recessed merged Fins and liner for enhanced stress coupling |
| CN103247535A (en) * | 2012-02-08 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Dislocation SMT for FinFET device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100505188C (en) * | 2006-04-21 | 2009-06-24 | 国际商业机器公司 | Method for forming FET |
| US8445334B1 (en) * | 2011-12-20 | 2013-05-21 | International Business Machines Corporation | SOI FinFET with recessed merged Fins and liner for enhanced stress coupling |
| CN103247535A (en) * | 2012-02-08 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Dislocation SMT for FinFET device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653623A (en) * | 2020-06-19 | 2020-09-11 | 上海华力集成电路制造有限公司 | Fin type transistor structure |
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