CN104700901A - Detection method for memory cell in SRAM - Google Patents
Detection method for memory cell in SRAM Download PDFInfo
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- CN104700901A CN104700901A CN201310655188.9A CN201310655188A CN104700901A CN 104700901 A CN104700901 A CN 104700901A CN 201310655188 A CN201310655188 A CN 201310655188A CN 104700901 A CN104700901 A CN 104700901A
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Abstract
The invention provides a detection method for a memory cell in SRAM. According to the invention, the input terminal of a first inverter in the memory cell is connected with the output terminal of the first inverter and with the input terminal of a second inverter; since the input and the output of the first inverter are equal and the input and the output of the second inverter accord with the characteristic curve of the inverter, if the first inverter matches with the second inverter, the output of the first inverter is equal to the output of the second inverter under the condition that the input of the first inverter is equal to the input of the second inverter; thus, under the condition that the input of the first inverter is equal to the input of the second inverter, if the output of the first inverter is not equal to the output of the second inverter, the first inverter does not match with the second inverter and it is certain that the threshold-voltage of at least one transistor drifts. As the memory cell is used as a detection unit, individual detection of every MOS transistor in the memory cell is avoided; detection quantity of the whole SRAM is reduced; efficiency is improved; cost is low; and results are accurate.
Description
Technical field
The present invention relates to technical field of integrated circuits, the detection method of the storage unit particularly in a kind of SRAM.
Background technology
Along with the raising of integrated circuit integrated level and the reduction of supply voltage, the physical dimension forming the semiconductor devices of integrated circuit is constantly reduced, and this just requires the manufacturing process updating chip.The improvement of manufacturing process is very large to the performance impact of single semiconductor devices, for assessing the performance of semiconductor devices, usually needs to test the reliability of semiconductor devices.
Static RAM (SRAM, Static Random Access Memory) a large amount of storage unit be made up of two phase inverters of middle existence, each phase inverter comprises a pair pull-up PMOS and pull-down NMOS pipe, if two phase inverters do not mate, then can cause the memory node data upset by mistake of two phase inverters.Above-mentioned unmatched a kind of key factor is caused to be that metal-oxide-semiconductor threshold voltage in two phase inverters does not mate.Thus, whether metal-oxide-semiconductor threshold voltage mates is the important indicator affecting memory reliability.Be that wafer acceptability test (WAT, WaferAcceptance Test) is carried out to each metal-oxide-semiconductor in storage unit in prior art, whether mated by the metal-oxide-semiconductor threshold voltage obtaining each metal-oxide-semiconductor threshold voltage and then obtain storage unit.
The ultimate principle of wafer acceptability test is the performance parameter that the test feeler switch (test key) be positioned on wafer Cutting Road (Scribe line) obtains single semiconductor devices.With reference to the crystal circle structure schematic diagram shown in figure 1, wafer 11 is cut 12 and is divided into multiple wafer (chip) 13.When making described wafer 13, can make single semiconductor element on described Cutting Road 12, namely the element be positioned at above described Cutting Road 12 is called as feeler switch.With reference to figure 2, described Cutting Road 12 having feeler switch M20 and feeler switch M21, by testing described feeler switch M20 and feeler switch M21, the metal-oxide-semiconductor characteristic in the wafer around described Cutting Road 12 can be obtained.
When detecting the PMOS threshold voltage in SRAM memory cell, corresponding DC voltage is applied to the pad that the drain electrode of described feeler switch M20, source electrode are connected with substrate, scanning voltage is applied to the pad that the grid of described feeler switch M20 connects, and during applying described scanning voltage, measure the drain current of described feeler switch M20, the family curve that the drain current obtaining described feeler switch M20 changes with the gate source voltage (voltage difference namely between grid and source electrode) of described feeler switch M20, calculates the threshold voltage of described feeler switch M20 again according to described family curve.
Namely the threshold voltage of described feeler switch M20 represents the PMOS threshold voltage in SRAM memory cell.The method of the NMOS tube threshold voltage in test SRAM memory cell is similar with the method for test PMOS, and namely test the threshold voltage of described feeler switch M21, concrete operations do not repeat them here.
Afterwards, compare each the metal-oxide-semiconductor threshold voltage in two phase inverters, to determine whether two phase inverters mate.
The method of above-mentioned detection SRAM memory cell scans each metal-oxide-semiconductor, and in storer, there is a large amount of metal-oxide-semiconductors, when obtaining the metal-oxide-semiconductor threshold voltage in storer by wafer acceptability test, each feeler switch needs connection four pads, namely the grid of feeler switch, drain electrode, source electrode are respectively connected a pad with substrate, this causes, and whether to mate cost by two phase inverters utilizing wafer acceptability test to obtain a large amount of metal-oxide-semiconductor threshold voltage in storer and then to obtain storage unit higher, and consuming time, result is also not accurate sometimes.
In view of this, the detection method of the storage unit that the invention provides in a kind of SRAM is solved the problems referred to above.
Summary of the invention
Higher, the consuming time and not problem accurately of the storage unit cost that what the present invention solved is is detected in SRAM by wafer acceptability test.
For solving the problem, the invention provides the detection method of the storage unit in a kind of SRAM, described SRAM comprises multiple storage unit be arranged in array, described storage unit at least comprises the first phase inverter and the second phase inverter, described first phase inverter comprises the first pull-up PMOS and the first pull-down NMOS pipe, described second phase inverter comprises the second pull-up PMOS and the second pull-down NMOS pipe, the input end of described first phase inverter is connected with output terminal and is connected with the input end of described second phase inverter, and described detection method comprises:
Power-on voltage, test the difference of the output terminal of the first phase inverter and the output terminal of the second phase inverter, if described difference is 0, then the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe mate with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe, if described difference is not 0, then the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe do not mate with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe.
Alternatively, described storage unit also comprises: the first transmission NMOS tube, the second transmission NMOS tube, described detection method comprises: open the first transmission NMOS tube and second and transmit NMOS tube, transmit by the first transmission NMOS tube and second difference that NMOS tube tests the output terminal of the first phase inverter and the output terminal of the second phase inverter.
Alternatively, described detection method also comprises: power-on voltage, tests the output valve of the output terminal of the first phase inverter and the output terminal of the second phase inverter respectively.
Alternatively, if the output valve of the first phase inverter is not standard value, then there is drift in the first pull-up PMOS of the first phase inverter or the threshold voltage of the first pull-down NMOS pipe, described standard value is the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe when mating with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe, the output valve that the output terminal of the first phase inverter and the output terminal of the second phase inverter all export.
Alternatively, described detection method also comprises: the threshold voltage measuring the first pull-up PMOS and the first pull-down NMOS pipe respectively.
Alternatively, if the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is just, then the threshold voltage of the first pull-up PMOS or the first pull-down NMOS pipe is bigger than normal; If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is negative, then the threshold voltage of the first pull-up PMOS or the first pull-down NMOS pipe is less than normal.
Alternatively, if the output valve of the second phase inverter is not standard value, then there is drift in the second pull-up PMOS of the second phase inverter or the threshold voltage of the second pull-down NMOS pipe, described standard value is the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe when mating with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe, the output valve that the output terminal of the first phase inverter and the output terminal of the second phase inverter all export.
Alternatively, described detection method also comprises: the threshold voltage measuring the second pull-up PMOS and the second pull-down NMOS pipe respectively.
Alternatively, if the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is just, then the threshold voltage of the second pull-up PMOS or the second pull-down NMOS pipe is less than normal; If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is negative, then the threshold voltage of the second pull-up PMOS or the second pull-down NMOS pipe is bigger than normal.
Alternatively, the input end of described first phase inverter is connected with output terminal and the implementation method be connected with the input end of described second phase inverter is: the conductive plunger place between the grid being connected described first pull-up PMOS and the source electrode of the second pull-up PMOS forms the through hole covering this conductive plunger; Formed and connect the described grid of the first pull-up PMOS and the conductive plunger of source electrode.
Alternatively, after having detected: insert conductive material in described through hole; Conductive plunger place between the grid connecting described first pull-up PMOS and source electrode forms the through hole covering this conductive plunger, and inserts isolation material in described through hole.
Compared with prior art, technical scheme of the present invention has the following advantages: 1) by being connected with output terminal by the input end of the first phase inverter in storage unit and being connected with the input end of described second phase inverter, utilize the constrained input of this first phase inverter equal, the constrained input of the second phase inverter meets the family curve of phase inverter, if two phase inverter couplings, when the input of the first phase inverter is equal with the input of the second phase inverter, the output of the first phase inverter is also necessarily equal with the output of the second phase inverter; And then can show that, when the input of the first phase inverter is equal with the input of the second phase inverter, if the output of the output of the first phase inverter and the second phase inverter is unequal, then two phase inverters do not mate, necessarily there is the threshold voltage of at least one transistor to occur drift.Above by the mode taking storage unit as detecting unit, avoid and detect separately each metal-oxide-semiconductor in this storage unit, decrease the detection limit of whole SRAM, improve efficiency, cost is lower and result is accurate.
2) in possibility, for the storage unit be made up of 4TMOS pipe (the first pull-up PMOS, the first pull-down NMOS pipe, the second pull-up PMOS and the second pull-down NMOS pipe), the source electrode of the first pull-up PMOS and the drain electrode link of the first pull-down NMOS pipe are as the output terminal of the first phase inverter, the source electrode of the second pull-up PMOS and the drain electrode link of the second pull-down NMOS pipe, as the output terminal of the second phase inverter, directly can obtain the difference of the output of the first phase inverter and the output of the second phase inverter from this two output terminal;
For the storage unit be made up of 6TMOS pipe (except above-mentioned four metal-oxide-semiconductors, also comprise the first transmission NMOS tube, the second transmission NMOS tube), the first transmission NMOS tube and second can also be opened and transmit NMOS tube, transmit indirectly by the first transmission NMOS tube and second difference that NMOS tube tests the output terminal of the first phase inverter and the output terminal of the second phase inverter; Certainly, for the storage unit of 6TMOS pipe composition, the difference of the source electrode of the first pull-up PMOS and drain electrode link two link of the drain electrode link of the first pull-down NMOS pipe, the source electrode of the second pull-up PMOS and the second pull-down NMOS pipe can also directly be measured.
3) in possibility, except above-mentioned test difference, described detection method also comprises: the output valve of testing the output terminal of the first phase inverter and the output terminal of the second phase inverter respectively.During by the output valve of respective phase inverter to judge that the first phase inverter does not mate with the second phase inverter, it is the metal-oxide-semiconductor threshold of appearance value drift in which phase inverter.
4) in possibility, for 3) possibility, if the output valve of the first phase inverter is not standard value, then there is drift in the first pull-up PMOS of the first phase inverter or the threshold voltage of the first pull-down NMOS pipe, described standard value is the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe when mating with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe, the output valve that the output terminal of the first phase inverter and the output terminal of the second phase inverter all export.Now can get rid of the metal-oxide-semiconductor threshold of appearance value drift of the second phase inverter.
5) in possibility, for 4) possibility, if there is drift in the threshold voltage of the first pull-up PMOS of the first phase inverter or the first pull-down NMOS pipe, then measure the threshold voltage of the first pull-up PMOS and the first pull-down NMOS pipe respectively, with specific to the threshold voltage shift judging certain metal-oxide-semiconductor.
6) in possibility, for 4) possibility, if the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is just, then the threshold voltage of the first pull-up PMOS or the first pull-down NMOS pipe is bigger than normal; If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is negative, then the threshold voltage of the first pull-up PMOS or the first pull-down NMOS pipe is less than normal.The difference that said method can export according to two phase inverters roughly judges the drift situation of a certain metal-oxide-semiconductor.
7) in possibility, for 3) possibility, if the output valve of the second phase inverter is not standard value, then there is drift in the second pull-up PMOS of the second phase inverter or the threshold voltage of the second pull-down NMOS pipe, described standard value is the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe when mating with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe, the output valve that the output terminal of the first phase inverter and the output terminal of the second phase inverter all export.Now can get rid of the metal-oxide-semiconductor threshold of appearance value drift of the first phase inverter.
8) in possibility, for 7) possibility, if there is drift in the threshold voltage of the second pull-up PMOS of the second phase inverter or the second pull-down NMOS pipe, then measure the threshold voltage of the second pull-up PMOS and the second pull-down NMOS pipe respectively, with specific to the threshold voltage shift judging certain metal-oxide-semiconductor.
9) in possibility, for 7) possibility, if the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is just, then the threshold voltage of the second pull-up PMOS or the second pull-down NMOS pipe is less than normal; If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is negative, then the threshold voltage of the second pull-up PMOS or the second pull-down NMOS pipe is bigger than normal.The difference that said method can export according to two phase inverters roughly judges the drift situation of a certain metal-oxide-semiconductor.
10) in possibility, about the semiconductor structure realizing above-mentioned detection method, the present invention is by carrying out corresponding change to the 4TMOS of the storage unit in the SRAM in wafer pipe or 6TMOS pipe, particularly, the conductive plunger place between the grid connecting described first pull-up PMOS and the source electrode of the second pull-up PMOS forms the through hole covering this conductive plunger; Formed and connect the described grid of the first pull-up PMOS and the conductive plunger of source electrode and to be connected with output terminal with the input end realizing the first phase inverter and to be connected with the input end of described second phase inverter.
11) in possibility, for 10) change in possibility after semiconductor structure, upon completion of the assays, in described through hole, insert conductive material; Conductive plunger place between the grid connecting described first pull-up PMOS and source electrode forms the through hole covering this conductive plunger, and inserts isolation material in described through hole, to recover 4TMOS pipe or the 6TMOS pipe of the storage unit in SRAM.
Accompanying drawing explanation
Fig. 1 is the structural representation of wafer;
Fig. 2 is the structural representation of the Cutting Road shown in Fig. 1;
Fig. 3 is the circuit diagram of the detection method use that one embodiment of the invention provides;
Fig. 4 is the first phase inverter in Fig. 3 and the second phase inverter input-output curve;
When Fig. 5 is the first pull-up PMOS threshold voltage shift in Fig. 3, the first corresponding respectively phase inverter and the output relation curve of the second phase inverter;
When Fig. 6 is the first pull-up PMOS threshold voltage shift in Fig. 3, the first corresponding phase inverter and the output difference relation curve of the second phase inverter;
When Fig. 7 is the second pull-up PMOS threshold voltage shift in Fig. 3, the first corresponding respectively phase inverter and the output relation curve of the second phase inverter;
When Fig. 8 is the second pull-up PMOS threshold voltage shift in Fig. 3, the first corresponding phase inverter and the output difference relation curve of the second phase inverter;
When Fig. 9 is the first pull-down NMOS pipe threshold voltage shift in Fig. 3, the first corresponding respectively phase inverter and the output relation curve of the second phase inverter;
When Figure 10 is the first pull-down NMOS pipe threshold voltage shift in Fig. 3, the first corresponding phase inverter and the output difference relation curve of the second phase inverter;
When Figure 11 is the second pull-down NMOS pipe threshold voltage shift in Fig. 3, the first corresponding respectively phase inverter and the output relation curve of the second phase inverter;
When Figure 12 is the second pull-down NMOS pipe threshold voltage shift in Fig. 3, the first corresponding phase inverter and the output difference relation curve of the second phase inverter;
Figure 13 is the circuit diagram of the detection method use that another embodiment of the present invention provides.
Embodiment
As described in the background art, the method of existing detection SRAM memory cell scans each metal-oxide-semiconductor in storage unit, to obtain each metal-oxide-semiconductor threshold voltage, and SRAM has multiple storage unit, it is higher that this causes two phase inverters obtaining storage unit whether to mate cost, and consuming time, result is also not accurate sometimes.For the problems referred to above, the present invention proposes to detect in units of storage unit, and reduce test volume, improve efficiency, result is comparatively accurate.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 3 is the circuit diagram of the detection method use that one embodiment of the invention provides, and with reference to figure 3, storage unit is 4TMOS pipe, the first pull-down NMOS pipe PD1, the second pull-down NMOS pipe PD2, the first pull-up PMOS PU1 and the second pull-up PMOS PU2.
The drain electrode of described first pull-up PMOS PU1 connects power vd D, the source electrode of the first pull-up PMOS PU1 is connected with the drain electrode of the first pull-down NMOS pipe PD1, the source ground VSS of the first pull-down NMOS pipe PD1, and the grid of described first pull-up PMOS PU1 is connected with the grid of the first pull-down NMOS pipe PD1;
The drain electrode of described second pull-up PMOS PU2 connects power vd D, the source electrode of the second pull-up PMOS PU2 is connected with the drain electrode of the second pull-down NMOS pipe PD2, the source ground VSS of the second pull-down NMOS pipe PD2, and the grid of described second pull-up PMOS PU2 is connected with the grid of the second pull-down NMOS pipe PD2;
In addition, the grid of the source electrode of the first pull-up PMOS PU1 and the drain electrode link of the first pull-down NMOS pipe PD1, the first pull-up PMOS PU1 and the grid link of the first pull-down NMOS pipe PD1, the grid of the second pull-up PMOS PU2 and the grid link of the second pull-down NMOS pipe PD2, above-mentioned three links are connected.
Can find out, above-mentioned first pull-down NMOS pipe PD1 and the first pull-up PMOS PU1 forms the first phase inverter, second pull-up PMOS PU2 and the second pull-down NMOS pipe PD2 forms the second phase inverter, and namely the input end of the first phase inverter is connected with output terminal and is connected with the input end of described second phase inverter.In addition, the second phase inverter has output terminal.The output terminal of the first phase inverter is for exporting the output V1out of the first phase inverter, and the output terminal of the second phase inverter is for exporting the output V2out of the second phase inverter.
For foregoing circuit, as shown in Figure 4, the input Vin of the first phase inverter is equal with output Vout, input Vin and the output Vout of the second phase inverter meet the family curve of phase inverter, if two phase inverter couplings, when the input of the first phase inverter is equal with the input of the second phase inverter, the output V1out of the first phase inverter is also necessarily equal with the output V2out of the second phase inverter.Accordingly, can draw when the input of the first phase inverter is equal with the input of the second phase inverter, if the output V2out of the output V1out of the first phase inverter and the second phase inverter is unequal, then two phase inverters do not mate, and necessarily have the threshold voltage of at least one transistor to occur drift.The present invention utilizes These characteristics, is detecting unit with storage unit, avoids and detects separately each metal-oxide-semiconductor in this storage unit, to reduce the detection limit of whole SRAM, improve efficiency.
Particularly, except above-mentioned test difference V1out-V2out, described detection method also comprises: the output valve V1out testing the output terminal of the first phase inverter and the output terminal of the second phase inverter respectively, V2out.During by the output valve of respective phase inverter to judge that the first phase inverter does not mate with the second phase inverter, it is the metal-oxide-semiconductor threshold of appearance value drift in which phase inverter.
Particularly, if the output valve V1out of the first phase inverter is not standard value, then there is drift in the first pull-up PMOS PU1 of the first phase inverter or the threshold voltage of the first pull-down NMOS pipe PD1, described standard value is that the first pull-up PMOS PU1 of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe PD1 are when mating with the second pull-up PMOS PU2 of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe PD2, the output valve that the output terminal of the first phase inverter and the output terminal of the second phase inverter all export, i.e. V1out=V2out.Now can get rid of the metal-oxide-semiconductor threshold of appearance value drift of the second phase inverter.
Further, if there is drift in the threshold voltage of the first pull-up PMOS PU1 of the first phase inverter or the first pull-down NMOS pipe PD1, then measure the threshold voltage of the first pull-up PMOS PU1 and the first pull-down NMOS pipe PD1 respectively, with specific to the threshold voltage shift judging certain metal-oxide-semiconductor.The measuring method of the threshold voltage of above-mentioned single metal-oxide-semiconductor can with reference to existing measuring method, and such as wafer acceptability test obtains the metal-oxide-semiconductor threshold voltage in storer.
If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is just, then the threshold voltage of the first pull-up PMOS PU1 or the first pull-down NMOS pipe PD1 is bigger than normal; If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is negative, then the threshold voltage of the first pull-up PMOS PU1 or the first pull-down NMOS pipe PD1 is less than normal.The difference that said method can export according to two phase inverters roughly judges the drift situation of a certain metal-oxide-semiconductor.
If the output valve of the second phase inverter is not standard value, then there is drift in the second pull-up PMOS PU2 of the second phase inverter or the threshold voltage of the second pull-down NMOS pipe PD2, described standard value is that the first pull-up PMOS PU1 of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe PD1 are when mating with the second pull-up PMOS PU2 of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe PD2, the output valve that the output terminal of the first phase inverter and the output terminal of the second phase inverter all export, i.e. V1out=V2out.Now can get rid of the metal-oxide-semiconductor threshold of appearance value drift of the first phase inverter.
If there is drift in the threshold voltage of the second pull-up PMOS PU2 of the second phase inverter or the second pull-down NMOS pipe PD2, then measure the threshold voltage of the second pull-up PMOS PU2 and the second pull-down NMOS pipe PD2 respectively, with specific to the threshold voltage shift judging certain metal-oxide-semiconductor.The measuring method of the threshold voltage of above-mentioned single metal-oxide-semiconductor can with reference to existing measuring method, and such as wafer acceptability test obtains the metal-oxide-semiconductor threshold voltage in storer.
If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is just, then the threshold voltage of the second pull-up PMOS PU2 or the second pull-down NMOS pipe PD2 is less than normal; If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is negative, then the threshold voltage of the second pull-up PMOS PU2 or the second pull-down NMOS pipe PD2 is bigger than normal.The difference that said method can export according to two phase inverters roughly judges the drift situation of a certain metal-oxide-semiconductor.
The method of the test SRAM memory cell that technical solution of the present invention provides is tested in units of storage unit, for the accuracy of two phase inverter matching degrees of the storage unit of checking the present embodiment acquisition, inventor, for single metal-oxide-semiconductor threshold voltage shift, has carried out emulation testing.
First with reference to shown in Fig. 5, first the threshold voltage of the first pull-up PMOS PU1 is set, exporting V1out and the second phase inverter to the first phase inverter, to export V2out equal, now the threshold voltage of the first pull-up PMOS PU1 is the threshold voltage that 4TMOS transistor memory unit two phase inverter is mated, and is called the threshold voltage matching value of the first pull-up PMOS PU1.Then with above-mentioned threshold voltage matching value for basic point, regulate the threshold voltage of the first pull-up PMOS PU1 by step-length 0.05V to the drift of change general orientation, record the first phase inverter respectively to export V1out and the second phase inverter and export V2out, till drift value deltaVth is 0.5V to the maximum.Afterwards still with above-mentioned threshold voltage matching value for basic point, regulate the threshold voltage of the first pull-up PMOS PU1 by step-length 0.05V to the direction drift that diminishes, record the first phase inverter respectively to export V1out and the second phase inverter and export V2out, till drift value deltaVth is 0.5V to the maximum.
Export do not mate for intuitively showing two phase inverters in the storage unit that causes due to the first pull-up PMOS PU1 threshold drift, export V1out and the second phase inverter to the first phase inverter in Fig. 5 and export V2out and do difference, result as shown in Figure 6.
Composition graphs 5 is with shown in Fig. 6, because the first phase inverter curve of output is comparatively smooth, and the second phase inverter curve of output has acute variation near the threshold voltage matching value of the first pull-up PMOS PU1, thus, the difference that first phase inverter output V1out and the second phase inverter export V2out also has acute variation near the threshold voltage matching value of the first pull-up PMOS PU1, be embodied in slope larger, generally be greater than 1, thus the slightly little threshold voltage shift of the first pull-up PMOS PU1, be reflected in the first phase inverter to export in difference that V1out and the second phase inverter export V2out and just have larger change, in other words, there is amplification effect.Thus relatively directly measure the threshold voltage scheme of each metal-oxide-semiconductor, this programme detects accurately.
Similarly, first with reference to shown in Fig. 7, first the threshold voltage of the second pull-up PMOS PU2 is set, exporting V1out and the second phase inverter to the first phase inverter, to export V2out equal, now the threshold voltage of the second pull-up PMOS PU2 is the threshold voltage that 4TMOS transistor memory unit two phase inverter is mated, and is called the threshold voltage matching value of the second pull-up PMOS PU2.Then with above-mentioned threshold voltage matching value for basic point, regulate the threshold voltage of the second pull-up PMOS PU2 by step-length 0.05V to the drift of change general orientation, record the first phase inverter respectively to export V1out and the second phase inverter and export V2out, till drift value deltaVth is 0.5V to the maximum.Afterwards still with above-mentioned threshold voltage matching value for basic point, regulate the threshold voltage of the second pull-up PMOS PU2 by step-length 0.05V to the direction drift that diminishes, record the first phase inverter respectively to export V1out and the second phase inverter and export V2out, till drift value deltaVth is 0.5V to the maximum.
Export do not mate for intuitively showing two phase inverters in the storage unit that causes due to the second pull-up PMOS PU2 threshold drift, export V1out and the second phase inverter to the first phase inverter in Fig. 7 and export V2out and do difference, result as shown in Figure 8.
Composition graphs 7 is with shown in Fig. 8, because the first phase inverter curve of output is comparatively smooth, and the second phase inverter curve of output has acute variation near the threshold voltage matching value of the second pull-up PMOS PU2, thus, the difference that first phase inverter output V1out and the second phase inverter export V2out also has acute variation near the threshold voltage matching value of the first pull-up PMOS PU1, be embodied in slope larger, generally be greater than 1, thus the slightly little threshold voltage shift of the second pull-up PMOS PU2, be reflected in the first phase inverter to export in difference that V1out and the second phase inverter export V2out and just have larger change, in other words, there is amplification effect.Thus relatively directly measure the threshold voltage scheme of each metal-oxide-semiconductor, this programme is measured accurately.
With above-mentioned detection type seemingly, positive and negative 0.5V drift can be carried out with the threshold voltage matching value of this NMOS tube PD1 for basic point to the threshold voltage of the first pull-down NMOS pipe PD1, record the first phase inverter respectively and export V1out and the second phase inverter and export V2out, as shown in Figure 9.Export V2out to the first phase inverter output V1out and the second phase inverter and do difference, the relation between the threshold voltage shift amount deltaVth of this difference and the first pull-down NMOS pipe PD1 as shown in Figure 10.For basic point, positive and negative 0.5V drift is carried out with the threshold voltage matching value of this NMOS tube PD2 to the threshold voltage of the second pull-down NMOS pipe PD2, records the first phase inverter respectively and export V1out and the second phase inverter and export V2out, as shown in figure 11.Export V2out to the first phase inverter output V1out and the second phase inverter and do difference, the relation between the threshold voltage shift amount deltaVth of this difference and the second pull-down NMOS pipe PD2 as shown in figure 12.Above-mentioned concrete detection method is concrete with reference to the first pull-up PMOS PU1 and the second pull-up PMOS PU2.Do not repeat them here.
Except above-mentioned detection method, present invention also offers the method obtained for the semiconductor structure of above-mentioned detection method, particularly, the present invention is by carrying out corresponding change to the 4TMOS pipe of the storage unit in the SRAM in wafer, in other words, the grid of the first pull-up PMOS PU1 in storage unit and the grid link of the first pull-down NMOS pipe PD1, the source electrode of the second pull-up PMOS PU2 and the drain electrode link of the second pull-down NMOS pipe PD2, two links are connected, in the present embodiment, the grid of above-mentioned first pull-up PMOS PU1 is connected by conductive plunger with between the source electrode of the second pull-up PMOS PU2, the source electrode of the first pull-up PMOS PU1 and the drain electrode link of the first pull-down NMOS pipe PD1, the grid of the second pull-up PMOS PU2 and the grid link of the second pull-down NMOS pipe PD2, two links are connected.Particularly, the conductive plunger place between the grid connecting described first pull-up PMOS PU1 and the source electrode of the second pull-up PMOS PU2 forms the through hole covering this conductive plunger, and above-mentioned through hole preferably inserts isolation material; Formed and connect the described grid of the first pull-up PMOS PU1 and the conductive plunger of source electrode and to be connected with output terminal with the input end realizing the first phase inverter and to be connected with the input end of described second phase inverter.
Alternatively, for the semiconductor structure after change, upon completion of the assays, remove the isolation material in through hole, in described through hole, insert conductive material; Conductive plunger place between the grid connecting described first pull-up PMOS PU1 and source electrode forms the through hole covering this conductive plunger, and inserts isolation material in described through hole, to recover the 4TMOS pipe of the storage unit in SRAM.
In another embodiment, as shown in figure 13, storage unit is formed (except above-mentioned 4TMOS pipe by 6TMOS pipe, also comprise the first transmission NMOS tube PG1, the second transmission NMOS tube PG2), the first transmission NMOS tube PG1 and second can also be opened and transmit NMOS tube PG2, transmit indirectly by the first transmission NMOS tube PG1 and second the difference V1out-V2out that NMOS tube PG2 tests the output terminal of the first phase inverter and the output terminal of the second phase inverter.Can also be measured the output valve V1out of the output terminal of the first phase inverter by the first transmission NMOS tube PG1, the second transmission NMOS tube PG2 measures the output valve V2out of the output terminal of the second phase inverter.Certainly, for the storage unit of 6TMOS pipe composition, also can directly test the drain electrode link of source electrode with the first pull-down NMOS pipe PD1 of the first pull-up PMOS PU1, the source electrode of the second pull-up PMOS PU2 and drain electrode link two link of the second pull-down NMOS pipe PD2 difference V1out-V2out or test this respectively and two connect hold and export V1out with corresponding first phase inverter that obtains, the second phase inverter output V2out.
In specific implementation process, for avoiding the first transmission NMOS tube PG1, the second test of transmission NMOS tube PG2 to the difference V1out-V2out of the output terminal of the output terminal of the first phase inverter and the second phase inverter impact, the voltage of 1.5VDD-2VDD, preferred 2VDD can be applied at the grid of the first transmission NMOS tube PG1, the second transmission NMOS tube PG2.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (11)
1. the detection method of the storage unit in a SRAM, described SRAM comprises multiple storage unit be arranged in array, described storage unit at least comprises the first phase inverter and the second phase inverter, described first phase inverter comprises the first pull-up PMOS and the first pull-down NMOS pipe, described second phase inverter comprises the second pull-up PMOS and the second pull-down NMOS pipe, it is characterized in that, the input end of described first phase inverter is connected with output terminal and is connected with the input end of described second phase inverter, and described detection method comprises:
Power-on voltage, test the difference of the output terminal of the first phase inverter and the output terminal of the second phase inverter, if described difference is 0, then the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe mate with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe, if described difference is not 0, then the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe do not mate with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe.
2. detection method according to claim 1, it is characterized in that, described storage unit also comprises: the first transmission NMOS tube, the second transmission NMOS tube, described detection method comprises: open the first transmission NMOS tube and second and transmit NMOS tube, transmit by the first transmission NMOS tube and second difference that NMOS tube tests the output terminal of the first phase inverter and the output terminal of the second phase inverter.
3. detection method according to claim 1 and 2, is characterized in that, described detection method also comprises: power-on voltage, tests the output valve of the output terminal of the first phase inverter and the output terminal of the second phase inverter respectively.
4. detection method according to claim 3, it is characterized in that, if the output valve of the first phase inverter is not standard value, then there is drift in the first pull-up PMOS of the first phase inverter or the threshold voltage of the first pull-down NMOS pipe, described standard value is the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe when mating with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe, the output valve that the output terminal of the first phase inverter and the output terminal of the second phase inverter all export.
5. detection method according to claim 4, is characterized in that, described detection method also comprises: the threshold voltage measuring the first pull-up PMOS and the first pull-down NMOS pipe respectively.
6. detection method according to claim 4, is characterized in that, if the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is just, then the threshold voltage of the first pull-up PMOS or the first pull-down NMOS pipe is bigger than normal; If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is negative, then the threshold voltage of the first pull-up PMOS or the first pull-down NMOS pipe is less than normal.
7. detection method according to claim 3, it is characterized in that, if the output valve of the second phase inverter is not standard value, then there is drift in the second pull-up PMOS of the second phase inverter or the threshold voltage of the second pull-down NMOS pipe, described standard value is the first pull-up PMOS of the first phase inverter and the threshold voltage of the first pull-down NMOS pipe when mating with the second pull-up PMOS of the second phase inverter and the threshold voltage of the second pull-down NMOS pipe, the output valve that the output terminal of the first phase inverter and the output terminal of the second phase inverter all export.
8. detection method according to claim 7, is characterized in that, described detection method also comprises: the threshold voltage measuring the second pull-up PMOS and the second pull-down NMOS pipe respectively.
9. detection method according to claim 7, is characterized in that, if the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is just, then the threshold voltage of the second pull-up PMOS or the second pull-down NMOS pipe is less than normal; If the difference of the output terminal of the output terminal of the first phase inverter and the second phase inverter is negative, then the threshold voltage of the second pull-up PMOS or the second pull-down NMOS pipe is bigger than normal.
10. detection method according to claim 1, it is characterized in that, the input end of described first phase inverter is connected with output terminal and the implementation method be connected with the input end of described second phase inverter is: the conductive plunger place between the grid being connected described first pull-up PMOS and the source electrode of the second pull-up PMOS forms the through hole covering this conductive plunger; Formed and connect the described grid of the first pull-up PMOS and the conductive plunger of source electrode.
11. detection methods according to claim 10, is characterized in that, after having detected: in described through hole, insert conductive material; Conductive plunger place between the grid connecting described first pull-up PMOS and source electrode forms the through hole covering this conductive plunger, and inserts isolation material in described through hole.
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