CN108320775B

CN108320775B - SRAM unit and detection method thereof, detection system of SRAM unit and SRAM device

Info

Publication number: CN108320775B
Application number: CN201710037835.8A
Authority: CN
Inventors: 甘正浩
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-01-18
Filing date: 2017-01-18
Publication date: 2022-03-22
Anticipated expiration: 2037-01-18
Also published as: CN108320775A

Abstract

An SRAM unit and a detection method thereof, a detection system of the SRAM unit and an SRAM device are provided, the SRAM unit comprises: a memory cell including a first inverter and a second inverter; a transfer unit including a first transfer gate transistor and a second transfer gate transistor, drains of the first transfer gate transistor and the second transfer gate transistor being electrically connected to the first node and the third node, respectively; a word line electrically connected to the first pass gate transistor gate and the second pass gate transistor gate; bit lines including a first bit line and a second bit line electrically connected to sources of the first and second pass gate transistors, respectively; a driving unit electrically connected to the bit line for simultaneously loading a low level to the second node and the fourth node; and a reading unit electrically connected to the bit line for reading a sum of output currents of the first pull-up transistor and the second pull-up transistor. A failed SRAM cell can be detected by the SRAM cell.

Description

SRAM unit and detection method thereof, detection system of SRAM unit and SRAM device

Technical Field

The present invention relates to the field of semiconductors, and in particular, to an SRAM cell, a detection method thereof, a detection system of the SRAM cell, and an SRAM device.

Background

In the current semiconductor industry, integrated circuit products can be divided into three major categories: logic, memory, and analog circuits, where memory devices represent a significant proportion of the products of integrated circuits. As semiconductor technology advances and memory devices are used more widely, it is necessary to form the memory devices on one chip simultaneously with other device regions to form embedded semiconductor memory devices. For example, if the memory device is embedded in a central processing unit, the memory device needs to be compatible with the embedded central processing unit platform and maintain the specification and corresponding electrical performance of the original memory device.

Generally, the memory device needs to be compatible with the embedded standard logic device. For embedded semiconductor devices, they are typically divided into logic areas, which typically include logic devices, and memory areas, which include memory devices. With the development of Memory technology, various types of semiconductor memories have appeared, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory (Flash). Because the static random access memory has the advantages of low power consumption, high working speed and the like, the static random access memory and the forming method thereof are paid more and more attention.

It is therefore desirable to provide a new SRAM cell structure and method of testing the same, and to detect failed SRAM cells in the meantime.

Disclosure of Invention

The invention provides an SRAM unit and a detection method thereof, a detection system of the SRAM unit and an SRAM device, which are convenient for detecting a failed SRAM unit.

To solve the above problems, the present invention provides an SRAM cell, comprising: a memory cell including a first inverter and a second inverter; the first inverter comprises a first pull-up transistor and a first pull-down transistor, the drain of the first pull-up transistor is electrically connected with the source of the first pull-down transistor, the connection point of the drain of the first pull-up transistor and the source of the first pull-down transistor is a first node, the gate of the first pull-up transistor is electrically connected with the gate of the first pull-down transistor, and the connection point of the gate of the first pull-up transistor and the gate of the first pull-down transistor is a second node; the second inverter comprises a second pull-up transistor and a second pull-down transistor, the drain of the second pull-up transistor is electrically connected with the source of the second pull-down transistor, the connection point of the drain of the second pull-up transistor and the source of the second pull-down transistor is a third node, the gate of the second pull-up transistor is electrically connected with the gate of the second pull-down transistor, and the connection point of the gate of the second pull-up transistor and the gate of the second pull-down transistor is a fourth node; wherein the second node is electrically connected to the third node, and the first node is electrically connected to the fourth node; a transfer unit including a first transfer gate transistor and a second transfer gate transistor, a drain of the first transfer gate transistor being electrically connected to the first node, and a drain of the second transfer gate transistor being electrically connected to the third node; a word line electrically connected to the gate of the first pass gate transistor and the gate of the second pass gate transistor; a bit line comprising a first bit line electrically connected to the source of the first pass gate transistor and a second bit line electrically connected to the source of the second pass gate transistor; a driving unit electrically connected to the bit line, the driving unit for simultaneously loading a low level to the second node and the fourth node through the bit line and the transfer unit; a reading unit electrically connected to the bit line, the reading unit for reading a sum of a first output current of the first pull-up transistor and a second output current of the second pull-up transistor through the bit line and the transfer unit.

Correspondingly, the invention also provides a detection method of the SRAM unit, which comprises the following steps: providing the SRAM cell; providing a threshold voltage reference value for the pull-up transistor; providing a relation between a threshold voltage and an output current of the pull-up transistor; turning on the first and second pass-gate transistors; the driving unit loads a low level to the fourth node through the first bit line and the first transmission gate transistor, so that the second pull-up transistor is turned on, the second pull-down transistor is turned off, and the second pull-up transistor outputs a second output current; the driving unit loads a low level to the second node through the second bit line and a second transfer gate transistor at the same time, so that the first pull-up transistor is started, the first pull-down transistor is closed, and the first pull-up transistor outputs a first output current; the reading unit reads the sum of the first output current and the second output current through the first transmission gate transistor, the first bit line, the second transmission gate transistor and the second bit line; dividing the sum of the first output current and the second output current by two to obtain an output current detection value; obtaining threshold voltage detection values of the first pull-up transistor and the second pull-up transistor according to the relation and the output current detection value; and comparing the threshold voltage detection value with a threshold voltage reference value, and judging that the first pull-up transistor and the second pull-up transistor are invalid when the absolute value of the difference between the threshold voltage detection value and the threshold voltage reference value is larger than a preset difference.

Correspondingly, the invention also provides a detection system of the SRAM unit, which comprises: the aforementioned SRAM cell; the calculation unit is connected with the SRAM unit and is used for dividing the sum of the first output current and the second output current of the SRAM unit by two to obtain an output current detection value and obtaining threshold voltage detection values of the first pull-up transistor and the second pull-up transistor according to a relational expression between the threshold voltage and the output current of the pull-up transistor; and the judging unit is connected with the calculating unit and used for providing a threshold voltage reference value of the pull-up transistor, comparing the threshold voltage detection value with the threshold voltage reference value, and judging that the first pull-up transistor and the second pull-up transistor are invalid when the absolute value of the difference value between the threshold voltage detection value and the threshold voltage reference value is greater than a preset difference value.

Correspondingly, the invention also provides an SRAM device, comprising: a plurality of memory modules arranged in a matrix, the memory modules including memory cells and transfer units; the memory cell comprises a first inverter and a second inverter; the first inverter comprises a first pull-up transistor and a first pull-down transistor, the drain of the first pull-up transistor is electrically connected with the source of the first pull-down transistor, the connection point of the drain of the first pull-up transistor and the source of the first pull-down transistor is a first node, the gate of the first pull-up transistor is electrically connected with the gate of the first pull-down transistor, and the connection point of the gate of the first pull-up transistor and the gate of the first pull-down transistor is a second node; the second inverter comprises a second pull-up transistor and a second pull-down transistor, the drain of the second pull-up transistor is electrically connected with the source of the second pull-down transistor, the connection point of the drain of the second pull-up transistor and the source of the second pull-down transistor is a third node, the gate of the second pull-up transistor is electrically connected with the gate of the second pull-down transistor, and the connection point of the gate of the second pull-up transistor and the gate of the second pull-down transistor is a fourth node; the second node is electrically connected with the third node, and the first node is electrically connected with the fourth node; the transfer unit comprises a first transfer gate transistor and a second transfer gate transistor, wherein the drain electrode of the first transfer gate transistor is electrically connected with the first node, and the drain electrode of the second transfer gate transistor is electrically connected with the third node; a plurality of word lines, each word line being electrically connected to the gates of the first pass gate transistor and the second pass gate transistor in the same row of the matrix; a plurality of bit lines including a plurality of first bit lines and a plurality of second bit lines alternately arranged, each first bit line being electrically connected to the sources of the first pass-gate transistors in the same column of the matrix, and each second bit line being electrically connected to the sources of the second pass-gate transistors in the same column of the matrix; a driving unit electrically connected to the plurality of bit lines, the driving unit for simultaneously loading a low level to the second node and the fourth node through the bit lines and the transfer unit; a reading unit electrically connected to the plurality of bit lines, the reading unit for reading a sum of a first output current of the first pull-up transistor and a second output current of the second pull-up transistor through the bit lines and the transfer unit.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the SRAM cell of the present invention includes a driving unit electrically connected to a bit line, wherein the driving unit is configured to load a low level to the second node and the fourth node through the bit line and the transfer unit, so that when the SRAM cell is operated, both the first pull-down transistor in the first inverter and the second pull-down transistor in the second inverter are turned off, and both the first pull-up transistor in the first inverter and the second pull-up transistor in the second inverter are turned on, so that the first pull-up transistor outputs a first output current, i.e., a current of the first node is a first output current, and the second pull-up transistor outputs a second output current, i.e., a current of the third node is a second output current; the SRAM cell further comprises a reading unit electrically connected with the bit line, and the reading unit is used for reading the sum of a first output current of the first pull-up transistor and a second output current of the second pull-up transistor through the bit line and the transfer unit; obtaining an output current detection value by dividing the sum of the first output current and the second output current read by the reading unit by two, so that a threshold voltage detection value can be obtained by the output current detection value; the first inverter and the second inverter are symmetrical structures, so that the first output current and the second output current are considered to be equal, and correspondingly, the threshold voltage of the first pull-up transistor corresponding to the first output current is the threshold voltage detection value, and the threshold voltage of the second pull-up transistor corresponding to the second output current is the threshold voltage detection value; by comparing the threshold voltage detection value with a threshold voltage reference value, when the absolute value of the difference between the threshold voltage detection value and the threshold voltage reference value is greater than a preset difference, it can be determined that the first pull-up transistor and the second pull-up transistor are failed; therefore, the SRAM unit can detect the failed SRAM unit in time, so that corresponding improvement measures can be made in time to improve the performance of the SRAM device.

Drawings

FIG. 1 is a diagram of the cumulative distribution function of the minimum operating voltage for SRAM reading and writing;

FIG. 2 is a circuit diagram of an embodiment of an SRAM cell of the present invention;

FIG. 3 is a graph of threshold voltage of a first pull-up transistor versus a first output current in an embodiment of a method for testing an SRAM cell of the present invention;

FIG. 4 is a functional block diagram of one embodiment of a detection system for an SRAM cell of the present invention;

FIG. 5 is a circuit diagram of an embodiment of an SRAM device of the present invention.

Detailed Description

In view of the background, it is desirable to provide a new SRAM cell structure and method for testing the same, and to detect failed SRAM cells in the meantime. The reason for this analysis is:

currently, Negative Bias Temperature Instability (NBTI) becomes a main cause of SRAM performance degradation, and PMOS correspondingly has a problem of threshold voltage (Vt) increase under the influence of NBTI. Referring to fig. 1 in combination, a cumulative distribution function (CDF plot) of the minimum operating voltage for reading and writing of the SRAM is shown, where the abscissa represents the operating voltage value and the ordinate represents the ratio at a certain operating voltage value.

Curves

201 and 301 represent a first SRAM device, and

curves

202 and 302 represent a second SRAM device, the first SRAM device being a normal SRAM device, the second SRAM device having a pull-up transistor threshold voltage greater than the pull-up transistor threshold voltage of the first SRAM device, the effect of NBTI on the SRAM device being characterized by

curves

202 and 302.

Specifically, a curve 201 represents a cumulative distribution function diagram of the Read function minimum operating voltage (Vccmin _ Read) of the first SRAM device, a curve 202 represents a cumulative distribution function diagram of the Read function minimum operating voltage of the second SRAM device, a curve 301 represents a cumulative distribution function diagram of the Write function minimum operating voltage (Vccmin _ Write) of the second SRAM device, and a curve 302 represents a cumulative distribution function diagram of the Write function minimum operating voltage (Vccmin _ Write) of the first SRAM device.

As can be seen from fig. 1, when the threshold voltage of the pull-up transistor is increased, the minimum operating voltage of the read function of the SRAM device is increased and the minimum operating voltage of the write function of the SRAM device is decreased, that is, NBIT causes the minimum operating voltage of the read function and the minimum operating voltage of the write function of the SRAM device to shift, thereby causing the performance of the SRAM device to be degraded.

Therefore, it is desirable to provide a new SRAM cell structure and a testing method thereof, and an SRAM cell corresponding to a pull-up transistor whose threshold voltage is shifted is detected, so that corresponding improvement measures can be made according to actual situations, SRAM devices can be optimized in time, and loss degree can be reduced.

In order to solve the technical problem, the present invention provides an SRAM cell, including a driving unit electrically connected to a bit line, the driving unit being configured to load a low level to the second node and the fourth node through the bit line and the transfer unit at the same time, so that when the SRAM cell is operated, a first pull-down transistor in a first inverter and a second pull-down transistor in a second inverter are both turned off, and a first pull-up transistor in the first inverter and a second pull-up transistor in the second inverter are both turned on, so that the first pull-up transistor outputs a first output current, that is, a current of the first node is a first output current, and the second pull-up transistor outputs a second output current, that is, a current of the third node is a second output current; the SRAM cell further comprises a reading unit electrically connected with the bit line, and the reading unit is used for reading the sum of a first output current of the first pull-up transistor and a second output current of the second pull-up transistor through the bit line and the transfer unit; obtaining an output current detection value by dividing the sum of the first output current and the second output current read by the reading unit by two, so that a threshold voltage detection value can be obtained by the output current detection value; the first inverter and the second inverter are symmetrical structures, so that the first output current and the second output current are considered to be equal, and correspondingly, the threshold voltage of the first pull-up transistor corresponding to the first output current is the threshold voltage detection value, and the threshold voltage of the second pull-up transistor corresponding to the second output current is the threshold voltage detection value; by comparing the threshold voltage detection value with a threshold voltage reference value, when the absolute value of the difference between the threshold voltage detection value and the threshold voltage reference value is greater than a preset difference, it can be determined that the first pull-up transistor and the second pull-up transistor are failed; therefore, the SRAM unit can detect the failed SRAM unit in time, so that corresponding improvement measures can be made in time to improve the performance of the SRAM device.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to FIG. 2, a circuit diagram of one embodiment of an SRAM cell of the present invention is shown.

The SRAM cell includes:

a memory cell (not labeled) comprising a first inverter (not labeled) and a second inverter (not labeled); wherein the first inverter comprises a first pull-up transistor PUL and a first pull-down transistor PDL, a drain of the first pull-up transistor PUL is electrically connected with a source of the first pull-down transistor PDL, a connection point of the drain of the first pull-up transistor PUL and the source of the first pull-down transistor PDL is a first node A, a gate of the first pull-up transistor PUL is electrically connected with a gate of the first pull-down transistor PDL, and a connection point of the gate of the first pull-up transistor PUL and the gate of the first pull-down transistor PDL is a second node C; the second inverter comprises a second pull-up transistor PUR and a second pull-down transistor PDR, the drain of the second pull-up transistor PUR is electrically connected with the source of the second pull-down transistor PDR, the connection point of the drain of the second pull-up transistor PUR and the source of the second pull-down transistor PDR is a third node B, the gate of the second pull-up transistor PUR is electrically connected with the gate of the second pull-down transistor PDR, and the connection point of the gate of the second pull-up transistor PUR and the gate of the second pull-down transistor PDR is a fourth node D; wherein the second node C is electrically connected to the third node B, and the first node A is electrically connected to the fourth node D;

a transmission unit (not shown) including a first transmission gate transistor PGL and a second transmission gate transistor PGR, a drain of the first transmission gate transistor PGL being electrically connected to the first node a, and a drain of the second transmission gate transistor PGR being electrically connected to the third node B;

a word line WL electrically connected to the gates of the first and second pass gate transistors PGL and PGR;

bit lines (not labeled) including a first bit line BL electrically connected to the source of the first pass gate transistor PGL and a second bit line BLb electrically connected to the source of the second pass gate transistor PGR;

a driving unit 300 electrically connected to the bit line, the driving unit 300 for simultaneously loading a low level to the second node C and the fourth node D through the bit line and the transfer unit;

a reading unit 200 electrically connected to the bit line, the reading unit 200 being configured to read a first output current I of the first pull-up transistor PUL through the bit line and the transfer unit_LAnd a second output current I of the second pull-up transistor PUR_RAnd (4) summing.

The SRAM cell will be described in detail below with reference to the drawings.

In this embodiment, the memory unit and the transfer unit may constitute one memory module, and a plurality of repetitive memory modules arranged in a matrix may be used to constitute an SRAM device.

The storage unit is used for storing data. In this embodiment, taking the SRAM cell as a 6T structure as an example, the memory cell includes a first inverter (not shown) and a second inverter (not shown), and the first inverter and the second inverter are symmetrical structures.

The first inverter comprises a first pull-up transistor PUL and a first pull-down transistor PDL, a drain of the first pull-up transistor PUL is electrically connected with a source of the first pull-down transistor PDL, and a connection point of the drain of the first pull-up transistor PUL and the source of the first pull-down transistor PDL is a first node A; the gate of the first pull-up transistor PUL is electrically connected to the gate of the first pull-down transistor PDL, and a connection point between the gate of the first pull-up transistor PUL and the gate of the first pull-down transistor PDL is a second node C.

The second inverter comprises a second pull-up transistor PUR and a second pull-down transistor PDR, the drain of the second pull-up transistor PUR is electrically connected with the source of the second pull-down transistor PDR, and the connection point of the drain of the second pull-up transistor PUR and the source of the second pull-down transistor PDR is a third node B; a gate of the second pull-up transistor PUR is electrically connected to a gate of the second pull-down transistor PDR, and a connection point of the gate of the second pull-up transistor PUR and the gate of the second pull-down transistor PDR is a fourth node D.

In this embodiment, the SRAM cell further comprises a working voltage power supply V_ddAnd a common voltage source V_ss(ii) a The source electrodes of the first pull-up transistor PUL and the second pull-up transistor PUR are connected with the working voltage power supply V_ddElectrically connected to the drains of the first PDL and second PDR pull-down transistors and the common voltage supply V_ssAnd (6) electrically connecting. The working voltage power supply V_ddIs greater than the common voltage source V_ssThe value of the voltage of the common voltage source V_ssBut may also be Ground (GND).

With continued reference to FIG. 2, the SRAM cell further comprises: a transfer unit (not shown), including a first transfer gate transistor PGL and a second transfer gate transistor PGR, wherein a drain of the first transfer gate transistor PGL is electrically connected to the first node a, and a drain of the second transfer gate transistor PGR is electrically connected to the third node B; a word line WL electrically connected to a gate of the first pass gate transistor PGL and a gate of the second pass gate transistor PGR; and a bit line (not shown) including a first bit line BL electrically connected to the source of the first pass gate transistor PGL and a second bit line BLb electrically connected to the source of the second pass gate transistor PGR.

Correspondingly, the first pull-up transistor PUL and the second pull-up transistor PUR are of a symmetrical structure, the first pull-down transistor PDL and the second pull-down transistor PDR are of a symmetrical structure, and the first pass-gate transistor PGL and the second pass-gate transistor PGR are of a symmetrical structure.

In this embodiment, the first pull-up transistor PUL and the second pull-up transistor PUR are PMOS, and the first pull-down transistor PDL, the second pull-down transistor PDR, the first pass-gate transistor PGL, and the second pass-gate transistor PGR are NMOS.

In this embodiment, the SRAM cell is used to detect a failed first pull-up transistor PUL or second pull-up transistor PUR.

It should be noted that, since the first pull-up transistor PUL and the second pull-up transistor PUR have symmetrical structures, the first pull-up transistor PUL and the second pull-up transistor PUR can be regarded as having the same structure and performance. Similarly, it can be considered that the structures and the performances of the first pull-down transistor PDL and the second pull-down transistor PDR are the same, and the structures and the performances of the first pass gate transistor PGL and the second pass gate transistor PGR are the same.

When the SRAM cell is used for detection, the word line WL is configured to load a high potential, so that the first pass gate transistor PGL and the second pass gate transistor PGR are turned on, and thus the first bit line BL is electrically connected to the first node a and the fourth node D through the first pass gate transistor PGL, and the second bit line BLb is electrically connected to the third node B and the second node C through the second pass gate transistor PGR.

With continued reference to FIG. 2, the SRAM cell further comprises: a driving unit 300 electrically connected to the bit line (not labeled), the driving unit 300 being configured to simultaneously load a low level to the second node C and the fourth node D through the bit line and the transfer unit (not labeled).

As can be seen from the foregoing analysis, when the first pass gate transistor PGL and the second pass gate transistor PGR are turned on, the first bit line BL is electrically connected to the first node a and the fourth node D through the first pass gate transistor PGL, and the second bit line BLb is electrically connected to the third node B and the second node C through the second pass gate transistor PGR, so that the driving unit 300 can simultaneously load a low level to the first bit line BL and the second bit line BLb, and thus load a low level to the fourth node D through the first bit line BL and the first pass gate transistor PGL, and load a low level to the second node C through the second bit line BLb and the second pass gate transistor PGR.

It should be noted that, since the second node C is electrically connected to the third node B, and the first node a is electrically connected to the fourth node D, the driving unit 300 is further configured to simultaneously load a low potential to the first node a and the third node B.

With continued reference to FIG. 2, the SRAM cell further comprises: a reading unit 200 electrically connected to the bit line (not labeled), the reading unit 200 being used for reading the first output current I of the first pull-up transistor PUL through the bit line and the transmitting unit (not labeled)_LAnd a second output current I of the second pull-up transistor PUR_RAnd (4) summing.

When a high potential is applied to the gate of the NMOS, the NMOS is turned on, and when a low potential is applied to the gate of the PMOS, the PMOS is turned on. In this embodiment, the driving unit 300 is configured to load a low level to the second node C and the fourth node D at the same time, so that the driving unit 300 can turn on both the first pull-up transistor PUL and the second pull-up transistor PUR and turn off both the first pull-down transistor PDL and the second pull-down transistor PDR; accordingly, the current of the first node A is the first output current I of the first pull-up transistor PUL_LThe current of the third node B is the second output current I of the second pull-up transistor PUR_R。

In addition, when the first pass gate transistor PGL and the second pass gate transistor PGR are turned on, the first bit line BL may be electrically connected to the first node a through the first pass gate transistor PGL, and the second bit line BLb may be electrically connected to the third node B through the second pass gate transistor PGR; the read unit 200 is electrically connected to the bit line (not labeled), so that the read unit 200 can read the first output current I at the first node a through the first bit line BL and the first pass gate transistor PGL_LThe second output current I at the third node B may also be read through the second bit line BLb and the second pass gate transistor PGR_R. Correspondingly, the reading unit 200 is used for reading the first output current I_LAnd the second output current I_RAnd (4) summing.

It should be noted that the SRAM cell is not only used for detection, but also used for normal operation. Therefore, in order to avoid adversely affecting the normal operation of the SRAM cell, the SRAM cell further comprises: a first enable unit (not shown) for electrically connecting the driving unit 300 and a bit line (not shown), a second enable unit (not shown) for electrically connecting the reading unit 200 and the bit line, and a selection unit 100 electrically connected to both the first enable unit and the second enable unit.

The storage unit and the transfer unit in the SRAM cell may form a storage module, and the plurality of repetitive storage modules arranged in a matrix may be used to form an SRAM device, that is, the SRAM device includes a plurality of storage units and transfer units with repetitive structures, so the first enabling unit and the selecting unit 100 are used to select a storage module to be detected from the matrix, so as to prevent the storage module from being affected by the driving unit 300 for a long time, and also prevent the reading unit 200 from simultaneously obtaining the first output currents I corresponding to the plurality of storage modules_LAnd a second output current I_RSumming; the second enabling unit and the selecting unit 100 are used for reading the first output current I corresponding to the memory module to be detected from the matrix_LAnd a second output current I_RAnd (4) summing.

In this embodiment, the selecting unit 100 is configured to control the first enabling unit and the second enabling unit to be turned on or turned off simultaneously; the first enabling unit is configured to control the driving unit 300 to load a low level to the second node C and the fourth node D at the same time; the second enabling unit is used for controlling the reading unit 200 to read the first output current I_LAnd the second output current I_RAnd (4) summing.

The SRAM device comprises a plurality of memory modules with a repeated structure arranged in a matrix, the selection unit 100 is used for addressing, and the row address and the column address of the memory module to be detected in the matrix can be determined through the selection unit 100, so that the specific address of the memory module to be detected in the matrix can be determined.

In this embodiment, the first enable unit includes a first transistor T1, the second enable unit includes a second transistor T2, and the transistor types of the first transistor T1 and the second transistor T2 are the same. Therefore, the selection unit 100 is used to control the simultaneous turning on or simultaneous turning off of the first transistor T1 and the second transistor T2.

Therefore, the first transistor T1 and the second transistor T2 correspond to the memory modules in the matrix one to one, that is, the number of the first transistors T1 is equal to the number of the memory modules, and the number of the second transistors T2 is equal to the number of the memory modules.

It should be noted that, in this embodiment, the selecting unit 100 is not only used to determine the specific address of the memory module to be detected in the matrix, but also used to turn on the first transistor T1 and the second transistor T2 of the memory module corresponding to the specific address, and turn off the first transistor T1 and the second transistor T2 corresponding to the remaining memory modules, so that the driving unit 300 and the reading unit 200 act on the memory module to be detected.

In this embodiment, the first transistor T1 and the second transistor T2 are both PMOS transistors. In other embodiments, the first transistor and the second transistor are both NMOS. Wherein, when the selection unit 100 is used for providing a high potential, the first transistor T1 and the second transistor T2 are both NMOS, and when the selection unit 100 is used for providing a low potential, the first transistor T1 and the second transistor T2 are both PMOS.

Specifically, the first transistor T1 includes a first gate, a first source and a first drain, and the second transistor T2 includes a second gate, a second source and a second drain; the first gate and the second gate are both electrically connected to the selection unit 100; the first source electrode is electrically connected with the driving unit 300; the first drain is electrically connected with the first bit line BL and the second bit line BLb; the second source is electrically connected with the first bit line BL and the second bit line BLb; the second drain is electrically connected to the read unit 200.

Therefore, when the selection unit 100 determines the specific address of the memory module to be detected in the matrix, and turns on the first transistor T1 and the second transistor T2 of the corresponding memory module, the driving unit 300 loads a low level to the fourth node D through the first transistor T1, the first bit line BL, and the first pass-gate transistor PGL to turn on the second pull-up transistor PUR; the driving unit 300 further loads a low level to the second node C through the first transistor T1, the second bit line BLb and the second pass gate transistor PGR to turn on the first pull-up transistor PUL, so that the first pull-up transistor PUL outputs a first output current I_LMaking the second pull-up transistor PUR output a second output current I_RAnd reading the first output current I by the reading unit 200_LAnd a second output current I_RAnd (4) summing.

With reference to fig. 2, correspondingly, the present invention further provides a method for detecting an SRAM cell, including: providing the SRAM cell of the previous embodiment; providing a threshold voltage reference value for the pull-up transistor; providing a relation between a threshold voltage and an output current of the pull-up transistor; turning on the first pass gate transistor PGL and the second pass gate transistor PGR; the driving unit 300 loads a low level to the fourth node D through the first bit line BL and the first pass gate transistor PGL, so that the second pull-up transistor PUR is turned on, the second pull-down transistor PDR is turned off, and the second pull-up transistor PUR outputs a second output current I_R(ii) a The driving unit 300 loads a low level to the second node C through the second bit line BLb and the second pass gate transistor PGR, so that the first pull-up transistor PUL is turned on, the first pull-down transistor PDL is turned off, and the first pull-up transistor PUL outputs a first output current I_L(ii) a The read unit 200 reads through the first pass gate transistor PGL, the first bit line BL, the second pass gate transistor PGR, and the second bit line BLbTaking the first output current I_LAnd a second output current I_RSumming; the first output current I_LAnd a second output current I_RDividing the sum by two to obtain an output current detection value; obtaining threshold voltage detection values of the first pull-up transistor PUL and the second pull-up transistor PUR according to the relation and the output current detection value; and comparing the threshold voltage detection value with a threshold voltage reference value, and judging that the first pull-up transistor PUL and the second pull-up transistor PUR are invalid when the absolute value of the difference between the threshold voltage detection value and the threshold voltage reference value is larger than a preset difference.

The following describes the detection method provided by the embodiment of the present invention in detail with reference to the accompanying drawings.

The storage unit and the transfer unit in the SRAM unit can form a storage module, a plurality of repeated storage modules arranged in a matrix can be used for forming an SRAM device, namely the SRAM device comprises a plurality of storage units and transfer units with repeated structures, and the detection method is used for detecting the storage module to be detected in the SRAM device.

Specifically, the descriptions of the SRAM cell refer to the corresponding descriptions in the foregoing embodiments of the SRAM cell of the present invention, and are not repeated herein.

In this embodiment, the detection method is used to detect the first output current I of the first pull-up transistor PUL in the SRAM cell_LAnd a second output current I of the second pull-up transistor PUR_RTo sum up, thereby to output the first output current I_LAnd a second output current I_RDividing the sum by two to obtain output current detection values of the first pull-up transistor PUL and the second pull-up transistor PUR, and obtaining threshold voltage detection values of the first pull-up transistor PUL and the second pull-up transistor PUR according to the relational expression and the output current detection values, so as to judge whether the first pull-up transistor PUL or the second pull-up transistor PUR is invalid.

It should be noted that, since the first pull-up transistor PUL and the second pull-up transistor PUR have symmetrical structures, the first pull-up transistor PUL and the second pull-up transistor PUR can be regarded as having the same structure and performance; accordingly, it can be considered that the output current values of the first pull-up transistor PUL and the second pull-up transistor PUR are output current detection values. Therefore, when any one of the first pull-up transistor PUL and the second pull-up transistor PUR fails, the corresponding SRAM cell is determined to be failed.

Specifically, the detection method comprises the following steps: providing a threshold voltage reference value of the pull-up transistor, i.e. providing a threshold voltage reference value of the first pull-up transistor PUL and the second pull-up transistor PUR; subsequently, after threshold voltage detection values of the first pull-up transistor PUL and the second pull-up transistor PUR are obtained, the threshold voltage detection values are compared with the threshold voltage reference value. Wherein the threshold voltage reference value of the pull-up transistor can be determined according to actual process requirements.

In this embodiment, the sources of the first pull-up transistor PUL and the second pull-up transistor PUR are both connected to the working voltage source V_ddElectrically connected to the drains of the first PDL and second PDR pull-down transistors and a common voltage source V_ssAnd (6) electrically connecting. The working voltage power supply V_ddIs greater than the common voltage source V_ssThe value of the voltage of the common voltage source V_ssBut may also be Ground (GND).

In this embodiment, the first pull-up transistor PUL is enabled to output a first output current I_LMake the second pull-up transistor PUR output a second output current I_RComprises the following steps: applying a high potential to the word line WL to turn on the first and second pass gate transistors PGL and PGR, so that the first bit line BL is electrically connected to the first and fourth nodes a and D through the first pass gate transistor PGL, and the second bit line BLb is electrically connected to the third and second nodes B and C through the second pass gate transistor PGR; the driving unit 300 simultaneously loads a low level to the second node C and the fourth node D through the bit line (not denoted) and the transfer unit (not denoted).

Specifically, the driving unit 300 loads a low level to the fourth node D through the first bit line BL and the first transfer gate transistor PGL, and simultaneously loads a low level to the second node C through the second bit line BLb and the second transfer gate transistor PGR.

Since a connection point of the gate of the first pull-up transistor PUL and the gate of the first pull-down transistor PDL is a second node C, a connection point of the gate of the second pull-up transistor PUR and the gate of the second pull-down transistor PDR is a fourth node D, and the NMOS is turned on when a high potential is applied to the gate of the NMOS, and the PMOS is turned on when a low potential is applied to the gate of the PMOS. Accordingly, the driving unit 300 turns on both the first pull-up transistor PUL and the second pull-up transistor PUR, while turning off both the first pull-down transistor PDL and the second pull-down transistor PDR.

In this embodiment, in the step of loading the driving unit 300 to the fourth node D and the second node C with the low level, the driving unit 300 Grounds (GND) the first bit line BL and the second bit line BLb.

Correspondingly, the output current of the first inverter is the first output current I of the first pull-up transistor PUL_LThe output current of the second inverter is the second output current I of the second pull-up transistor PUR_R(ii) a And since the second node C is electrically connected to the third node B and the first node a is electrically connected to the fourth node D, the third node B and the first node a are both at low potential, so the first pull-up transistor PUL outputs current to the first node a and the second pull-up transistor PUR outputs current to the third node B, that is, the current of the first node a is the first output current I of the first pull-up transistor PUL_LThe current of the third node B is the second output current I of the second pull-up transistor PUR_R。

Since the first pass gate transistor PGL and the second pass gate transistor PGR are turned on, the first bit line BL passes through the first pass gate transistor PGL and the second pass gate transistor PGRA node a is electrically connected, and the second bit line BLb is electrically connected to the third node B through the second pass gate transistor PGR; the read unit 200 is electrically connected to the bit line (not labeled), so that the read unit 200 reads a first output current I to the first node A through the first bit line BL_LA second output current I is also read to the third node B through the second bit line BLb_R. Specifically, the current read by the reading unit 200 is the first output current I_LAnd the second output current I_RAnd (4) summing.

It should be noted that the SRAM cell to be tested is also used for normal operation. Therefore, in order to avoid adversely affecting the normal operation of the SRAM cell, the SRAM cell further comprises: a first enable unit (not shown) for electrically connecting the driving unit 300 and a bit line (not shown), a second enable unit (not shown) for electrically connecting the reading unit 200 and the bit line, and a selection unit 100 electrically connected to both the first enable unit and the second enable unit.

In this embodiment, the first enable unit includes a first transistor T1, the second enable unit includes a second transistor T2, and the transistor types of the first transistor T1 and the second transistor T2 are the same.

For the detailed description of the selection unit 100, the first enabling unit, the second enabling unit, the first transistor T1 and the second transistor T2, reference may be made to the corresponding description in the foregoing embodiment of the SRAM cell of the present invention, and no further description is provided herein.

In this embodiment, after the selection unit 100 determines the specific address of the memory module to be detected in the matrix, the selection unit 100 controls the first transistor T1 and the second transistor T2 of the memory module corresponding to the specific address to be simultaneously turned on, and turns off the remaining first transistor T1 and the remaining second transistor T2.

Therefore, in the step of loading the low level to the fourth node D by the driving unit 300 through the first bit line BL and the first pass gate transistor PGL, the first transistor T1, the first bit line BL and the first pass gate transistorA first circuit loop is formed between the PGLs, and the driving unit 300 loads a low level to the fourth node D through the first circuit loop; and due to the source of the second pull-up transistor PUR and the operating voltage supply V_ddElectrically connected, so that the second pull-up transistor PUR is in an on state; in addition, since the fourth node D is at a low voltage level, the second pull-down transistor PDR is in an off state.

Similarly, in the step of loading the low level to the second node C by the driving unit 300 through the second bit line BLb and the second pass gate transistor PGR, a second circuit loop is formed among the first transistor T1, the second bit line BLb and the second pass gate transistor PGR, and the driving unit 300 loads the low level to the second node C through the second circuit loop; and due to the source of the first pull-up transistor PUL and the operating voltage supply V_ddElectrically connected, so that the first pull-up transistor PUL is in an on state; in addition, since the second node C is at a low potential, the first pull-down transistor PDL is in an off state.

Since the second node C is electrically connected to the third node B, the first node a is electrically connected to the fourth node D, the first node a and the third node B are correspondingly low-potential, and the first output current I of the first pull-up transistor PUL_LA second output current I of the second pull-up transistor PUR flowing to the first node A_RFlows to the third node B; accordingly, the read unit 200 reads the first output current I through the first pass gate transistor PGL, the first bit line BL, the second pass gate transistor PGR, and the second bit line BLb_LAnd a second output current I_RIn the sum step, a third circuit loop is formed among the first pull-up transistor PUL, the first pass-gate transistor PGL, the first bit line BL, and the second transistor T2, a fourth circuit loop is formed among the second pull-up transistor PUR, the second pass-gate transistor PGR, the second bit line BLb, and the second transistor T2, and the reading unit 200 reads the first output current I through the third circuit loop and the fourth circuit loop_LAnd the second output current I_RAnd (4) summing.

It should be noted that the reading unit 200 reads the first output current I_LAnd the second output current I_RAfter the step of summing, the detection method further comprises the following steps: the first output current I_LAnd a second output current I_RThe sum is divided by two to obtain an output current detection value.

Since the first pull-up transistor PUL and the second pull-up transistor PUR are symmetrical structures, it can be considered that the structures and the performances of the first pull-up transistor PUL and the second pull-up transistor PUR are the same, and accordingly, it can be considered that the output current values of the first pull-up transistor PUL and the second pull-up transistor PUR are the output current detection values.

It should be noted that, since the first node a and the third node B are grounded, the first pull-up transistor PUL and the second pull-up transistor PUR are both in a Saturation Region (Saturation Region). At this time, there is a relation between the threshold voltage of the pull-up transistor and the output current, which is the transistor saturation current (I)_dsat) And (4) a formula.

At the threshold voltage V of the first pull-up transistor PUL_th，PULFor example, the threshold voltage V of the first pull-up transistor PUL_th，PULAnd the first output current I_LHas a first relation therebetween according to the transistor saturation current (I)_dsat) A formula, wherein the first relation is: i is_L＝1/2*K_p*(V_dd-V_B-V_th，PUL)^2*(1+λ_p(V_dd-V_A)). Wherein, K_p＝μC_oxW/L，λ_pFor channel length modulation effect, V_BIs the potential of the third node B, V_AIs the potential of the first node A, V_ddIs a constant. And since the first bit line BL and the second bit line BLb are grounded, V_BAnd V_ACan be regarded as zero, accordingly, the first relation is: i is_L＝1/2*K_p*(V_dd-V_th，PUL)^2*(1+λ_p*V_dd)。

With reference to fig. 3, the threshold voltage V of the first pull-up transistor PUL is shown, taking the first pull-up transistor PUL as an example_th，PULAnd a first output current I_LGraph of the relationship of (c). Wherein the abscissa represents the threshold voltage V of the first pull-up transistor PUL_th，PULThe ordinate represents the threshold voltage V_th，PULCorresponding first output current I_L. From the graph, the first output current I of the first pull-up transistor PUL is shown_LAnd a threshold voltage V of the first pull-up transistor PUL_th，PULAnd (4) correlating.

Similarly, the threshold voltage V of the second pull-up transistor PUR_th，PURAnd the second output current I_RHas a second relational expression of I_R＝1/2*K_p*(V_dd-V_th，PUR)^2*(1+λ_p*V_dd)。

That is, the relationship between the threshold voltage and the output current of the pull-up transistor is: i is_PU＝1/2*K_p*(V_dd-V_th，PU)^2*(1+λ_p*V_dd)。

In addition, since the first node a and the third node B are low, the first pass gate transistor PGL and the second pass gate transistor PGR are both in a Linear Region (Linear Region). Obtaining the output current I of the first transmission gate transistor PGL according to a linear region current formula_PGLAnd a threshold voltage V of the first pass gate transistor PGL_th，PGLThe relationship between them is: i is_PGL＝K_p*[(V_GS-V_th，PGL)*V_DS-1/2*V_DS^2]＝K_p*[(V_dd-V_th，PGL)V_A](ii) a Thus dI/dV_th,PGL＝-K_p*V_A。

Since the driving unit 300 grounds the first bit line BL, V_ACan be regarded as zero, corresponding, dI/dV_th,PGL0, i.e. the first pass-gate transistor PGL threshold voltage V_th，PGLDoes not result in the first pass gate transistor PGLOutput current I_PGLA change occurs. Similarly, the second pass gate transistor PGR has a threshold voltage V_th，PGRDoes not result in the output current I of the second pass gate transistor PGR_PGRA change occurs.

Therefore, the first pass gate transistor PGL and the second pass gate transistor PGR do not interfere with the current obtained by the reading unit 200, that is, the current obtained by the reading unit 200 is only affected by the first pull-up transistor PUL and the second pull-up transistor PUR, that is, the output current detection value is only affected by the first pull-up transistor PUL and the second pull-up transistor PUR.

Accordingly, in this embodiment, the threshold voltage detection values of the first pull-up transistor PUL and the second pull-up transistor PUR may be obtained according to the relation and the output current detection value.

Specifically, the output current detection value is substituted into the first relational expression to obtain a first threshold voltage detection value V of the first pull-up transistor PUL_{th，PUL_Test}(ii) a Substituting the output current detection value into the second relational expression to obtain a second threshold voltage detection value V of the second pull-up transistor PUR_{th，PUR_Test}。

In this embodiment, the output current detection value is the first output current I_LAnd the second output current I_RHalf of the sum, i.e. the detected output current value (first output current I)_L+ a second output current I_R) /2, therefore said V_{th，PUL_Test}＝V_{th，PUR_Test}。

And after the threshold voltage detection value is obtained, comparing the threshold voltage detection value with a threshold voltage reference value, and when the absolute value of the difference between the threshold voltage detection value and the threshold voltage reference value is greater than a preset difference, judging that the first pull-up transistor PUL and the second pull-up transistor PUR are invalid.

Taking the first pull-up transistor PUL as an example, the first threshold voltage detection value V is obtained_{th，PUL_Test}Then, comparing the first threshold voltageMeasured value V_{th，PUL_Test}And a threshold voltage reference value when the first threshold voltage detection value V_{th，PUL_Test}And when the absolute value of the difference between the reference value of the threshold voltage and the reference value of the threshold voltage is greater than a preset difference, determining that the first pull-up transistor PUL is invalid.

Similarly, the second threshold voltage detection value V is obtained_{th，PUR_Test}Then, the second threshold voltage detection value V is compared_{th，PUR_Test}And a threshold voltage reference value when the second threshold voltage detection value V_{th，PUR_Test}And when the absolute value of the difference between the reference value of the threshold voltage and the reference value of the threshold voltage is larger than a preset difference, judging that the second pull-up transistor PUR is invalid.

In this embodiment, the preset difference is 75mV and 125 mV.

Correspondingly, the invention also provides a detection system of the SRAM unit. Referring to FIG. 4, a functional block diagram of an embodiment of a detection system of an SRAM cell of the present invention is shown.

The detection system of the SRAM unit comprises: the aforementioned SRAM cell 510; a calculation unit 520 connected to the SRAM cell 510 for calculating a first output current I of the SRAM cell 510_LAnd a second output current I_RDividing the sum by two to obtain an output current detection value, and obtaining threshold voltage detection values of the first pull-up transistor PUL and the second pull-up transistor PUR according to a relational expression between the threshold voltage and the output current of the pull-up transistors; and a determining unit 530 connected to the calculating unit 520, configured to provide a threshold voltage reference value of the pull-up transistor, compare the detected threshold voltage value with the threshold voltage reference value, and determine that the first pull-up transistor PUL and the second pull-up transistor PUR are disabled when an absolute value of a difference between the detected threshold voltage value and the threshold voltage reference value is greater than a preset difference.

For the detailed description of the SRAM cell 510, reference may be made to the corresponding description in the foregoing embodiments of the SRAM cell of the present invention, and details are not repeated here.

In this embodiment, the calculating unit 520 is used for calculating the first output current I_LAnd a second output current I_RThe sum is divided by two to obtainAnd obtaining an output current detection value. Since the first pull-up transistor PUL and the second pull-up transistor PUR are symmetrical structures, it can be considered that the structures and the performances of the first pull-up transistor PUL and the second pull-up transistor PUR are the same, and accordingly, it can be considered that the output current values of the first pull-up transistor PUL and the second pull-up transistor PUR are the output current detection values.

It should be noted that, since the first node a and the third node B are grounded, both the first pull-up transistor PUL and the second pull-up transistor PUR are in a Saturation Region (Saturation Region). At this time, there is a relation between the threshold voltage of the pull-up transistor and the output current, which is the transistor saturation current (I)_dsat) And (4) a formula.

In particular, the threshold voltage V of the first pull-up transistor PUL_th，PULAnd the first output current I_LHas a first relation therebetween, the first relation being: i is_L＝1/2*K_p*(V_dd-V_th，PUL)^2*(1+λ_p*V_dd) (ii) a Similarly, the threshold voltage V of the second pull-up transistor PUR_th，PURAnd the second output current I_RHas a second relational expression of I_R＝1/2*K_p*(V_dd-V_th，PUR)^2*(1+λ_p*V_dd)。

Therefore, the calculating unit 520 is further configured to substitute the output current detection value into the first relation to obtain a first threshold voltage detection value V of the first pull-up transistor PUL_{th，PUL_Test}(ii) a Substituting the output current detection value into the second relational expression to obtain a second threshold voltage detection value V of the second pull-up transistor PUR_{th，PUR_Test}。

For a detailed description of the method for obtaining the output current detection value and the threshold voltage detection value of the pull-up transistor, reference may be made to the corresponding description in the foregoing embodiment of the detection method of the SRAM cell of the present invention, and details are not repeated here.

After obtaining the threshold voltage detection value, the determining unit 530 compares the threshold voltage detection value with the threshold voltage reference value, and determines that the first pull-up transistor PUL and the second pull-up transistor PUR are disabled when an absolute value of a difference between the threshold voltage detection value and the threshold voltage reference value is greater than a preset difference. In this embodiment, the preset difference is 75mV and 125 mV.

In this embodiment, for specific description of determining whether the first pull-up transistor PUL and the second pull-up transistor PUR fail, reference may be made to the corresponding description in the foregoing embodiment of the detection method of the SRAM cell of the present invention, and details are not repeated here.

Referring to FIG. 5, a circuit diagram of one embodiment of an SRAM device of the present invention is shown. Correspondingly, the invention also provides an SRAM device.

Referring collectively to fig. 2, the SRAM device comprises: a plurality of memory modules 600 arranged in a matrix, the memory modules including memory cells and transfer cells; the memory cell comprises a first inverter and a second inverter; the first inverter comprises a first pull-up transistor PUL and a first pull-down transistor PDL, a drain of the first pull-up transistor PUL is electrically connected with a source of the first pull-down transistor PDL, a connection point of the drain of the first pull-up transistor PUL and the source of the first pull-down transistor PDL is a first node A, a gate of the first pull-up transistor PUL is electrically connected with the gate of the first pull-down transistor PDL, and a connection point of the gate of the first pull-up transistor PUL and the gate of the first pull-down transistor PDL is a second node C; the second phase inverter comprises a second pull-up transistor PUR and a second pull-down transistor PDR, the drain electrode of the second pull-up transistor PUR is electrically connected with the source electrode of the second pull-down transistor PDR, and the connection point of the drain electrode of the second pull-up transistor PUR and the source electrode of the second pull-down transistor PDRA third node B, a gate of the second pull-up transistor PUR and a gate of the second pull-down transistor PDR are electrically connected, and a connection point of the gate of the second pull-up transistor PUR and the gate of the second pull-down transistor PDR is a fourth node D; the second node C is electrically connected with the third node B, and the first node A is electrically connected with the fourth node D; the transmission unit includes a first transmission gate transistor PGL and a second transmission gate transistor PGR, a drain of the first transmission gate transistor PGL is electrically connected to the first node a, and a drain of the second transmission gate transistor is electrically connected to the third node B; a plurality of word lines WL, each word line WL being electrically connected to the gates of the first pass gate transistor PGL and the second pass gate transistor PGR in the same row in the matrix; a plurality of bit lines (not shown) including a plurality of first bit lines BL and second bit lines BLb alternately arranged, each of the first bit lines BL being electrically connected to the sources of the first pass gate transistors PGL in the same column of the matrix, and each of the second bit lines BLb being electrically connected to the sources of the second pass gate transistors PGR in the same column of the matrix; a driving unit 300 electrically connected to the plurality of bit lines, the driving unit 300 for simultaneously loading a low level to the second node C and the fourth node D through the bit lines and the transfer unit; a reading unit 200 electrically connected to the bit lines, the reading unit 200 being configured to read a first output current I of the first pull-up transistor PUL through the bit lines and the transfer unit_LAnd a second output current I of the second pull-up transistor PUR_RAnd (4) summing.

In this embodiment, the SRAM device includes a plurality of repetitive memory modules 600 arranged in a matrix, and accordingly, the plurality of memory modules 600 have the same structure, and each memory module 600 includes a memory cell and a transfer unit.

The storage unit is used for storing data. In this embodiment, taking the memory module 600 as a 6T SRAM structure as an example, the memory cell includes a first inverter (not shown) and a second inverter (not shown), and the first inverter and the second inverter are symmetrical structures. Wherein the first inverter includes a first pull-up transistor PUL and a first pull-down transistor PDL; the second inverter includes a second pull-up transistor PUR and a second pull-down transistor PDR.

In this embodiment, the transfer unit includes a first transfer gate transistor PGL and a second transfer gate transistor PGR.

Specifically, the first pull-up transistor PUL and the second pull-up transistor PUR have a symmetrical structure, the first pull-down transistor PDL and the second pull-down transistor PDR have a symmetrical structure, and the first pass-gate transistor PGL and the second pass-gate transistor PGR have a symmetrical structure.

It should be noted that the SRAM cell further includes an operating voltage supply V_ddAnd a common voltage source V_ss(ii) a The source electrodes of the first pull-up transistor PUL and the second pull-up transistor PUR are connected with the working voltage power supply V_ddElectrically connected to the drains of the first PDL and second PDR pull-down transistors and the common voltage supply V_ssAnd (6) electrically connecting. The working voltage power supply V_ddIs greater than the common voltage source V_ssThe value of the voltage of the common voltage source V_ssBut may also be Ground (GND).

For the detailed description of the storage unit and the transfer unit, reference may be made to the corresponding description in the foregoing embodiments of the SRAM cell of the present invention, and details are not repeated here.

In this embodiment, each word line WL is electrically connected to the gates of the first pass gate transistor PGL and the second pass gate transistor PGR in the same row of the matrix; each first bit line BL is electrically connected to the source of the first pass gate transistor PGL in the same column of the matrix, and each second bit line BLb is electrically connected to the source of the second pass gate transistor PGR in the same column of the matrix.

That is, the plurality of first pass gate transistors PGL located in the same column of the matrix share one first bit line BL, the plurality of second pass gate transistors PGR located in the same column of the matrix share one second bit line BLb, and the plurality of first pass gate transistors PGL and second pass gate transistors PGR located in the same row of the matrix share one word line WL.

Accordingly, the driving unit 300 is electrically connected to the bit lines, and the reading unit 200 is electrically connected to the bit lines. That is, the plurality of memory modules 600 share one driving unit 300 and one reading unit 200.

The driving unit 300 is configured to simultaneously load a low level to the second node C and the fourth node D through the bit line and the pass unit (not shown), and the reading unit 200 is configured to read a first output current I of the first pull-up transistor PUL through the bit line and the pass unit (not shown)_LAnd a second output current I of the second pull-up transistor PUR_RAnd (4) summing.

For the detailed description of the word line WL, the bit line, the driving unit 300 and the reading unit 200, reference may be made to the corresponding description in the foregoing embodiments of the SRAM cell of the present invention, and further description is omitted here.

It should be noted that the memory module 600 in the SRAM device can be used not only for detection but also for normal operation. In order to avoid adversely affecting the normal operation of the SRAM device, the SRAM device further comprises: a plurality of first enable units (not labeled) for electrically connecting the driving unit 300 and a plurality of bit lines, the plurality of first enable units corresponding to the plurality of memory modules 600 one-to-one and being electrically connected to the bit lines of the corresponding memory modules 600; a plurality of second enable units (not labeled) for electrically connecting the read unit 200 and the plurality of bit lines, the plurality of second enable units corresponding to the plurality of memory modules 600 one-to-one and being electrically connected to the bit lines of the corresponding memory modules 600; and a selection unit 100 electrically connected to the plurality of first enable units and the plurality of second enable units at the same time.

Accordingly, the number of the first enable units is equal to the number of the memory modules 600, and the number of the second enable units is equal to the number of the memory modules 600.

In this embodiment, the SRAM device includes a plurality of memory modules 600 arranged in a matrix and having a repetitive structure, the selection unit 100 is used for addressing, and the selection unit 100 can determine the row address and the column address of the memory module 600 to be detected in the matrix, so as to determine the specific address of the memory module 600 to be detected in the matrix.

The selection unit 100 is further configured to simultaneously control the first enabling unit and the second enabling unit corresponding to the same storage module 600 to be simultaneously turned on or off. Specifically, after determining the specific address of the memory module 600 to be detected in the matrix, the selecting unit 100 is configured to turn on the first enabling unit and the second enabling unit corresponding to the memory module 600 to be detected, and turn off the first enabling unit and the second enabling unit corresponding to the remaining memory modules 600.

The first enabling unit is configured to control the driving unit 300 to load a low level to the second node C and the fourth node D corresponding to the to-be-detected storage module 600 at the same time; the second enabling unit is configured to control the reading unit 200 to read the first output current I of the first pull-up transistor PUL corresponding to the memory module 600 to be detected_LAnd a second output current I of a second pull-up transistor PUR_RAnd (4) summing.

Therefore, the first enabling unit and the selecting unit 100 can prevent the memory module 600 from being affected by the driving unit 300 for a long time, and the reading unit 200 can prevent the first output currents I corresponding to the plurality of memory modules 600 from being obtained by the reading unit 200 at the same time_LAnd a second output current I_RSumming; the second enabling unit and the selecting unit 100 are used for reading the first output current I corresponding to the memory module 600 to be tested_LAnd a second output current I_RAnd (4) summing.

In this embodiment, the first enable unit includes a first transistor T1, the second enable unit includes a second transistor T2, and the transistor types of the first transistor T1 and the second transistor T2 are the same. Therefore, the selection unit 100 is also used to control the simultaneous turning on or simultaneous turning off of the first transistor T1 and the second transistor T2 corresponding to the same memory module 600.

Accordingly, the first transistor T1 and the second transistor T2 correspond to the memory modules 600 in the matrix in a one-to-one manner, that is, the number of the first transistors T1 is equal to the number of the memory modules 600, and the number of the second transistors T2 is equal to the number of the memory modules 600.

Specifically, after the selection unit 100 determines the specific address of the memory module 600 to be tested in the matrix, the selection unit is further configured to turn on the first transistor T1 and the second transistor T2 of the memory module 600 corresponding to the specific address, and turn off the first transistor T1 and the second transistor T2 corresponding to the remaining memory modules 600.

Specifically, the first transistor T1 includes a first gate, a first source and a first drain, and the second transistor T2 includes a second gate, a second source and a second drain; the first gate and the second gate are both electrically connected to the selection unit 100; the first source electrode is electrically connected with the driving unit 300; the first drain is electrically connected to the first bit line BL and the second bit line BLb of the corresponding memory module 600; the second source is electrically connected to the first bit line BL and the second bit line BLb of the corresponding memory module 600; the second drain is electrically connected to the read unit 200.

In this embodiment, after the selection unit 100 determines the specific address of the memory module 600 to be tested in the matrix, the first transistor T1 and the second transistor T2 of the corresponding memory module 600 are turned on, and the driving unit 300 can pass through the first transistor T1, the first bit line BL and the first pass gate transistor of the memory module 600 to be testedThe transistor PGL loads a low level to the fourth node D to turn on the first pull-up transistor PUL; the driving unit 300 may further load a low level to the second node C through the first transistor T1, the second bit line BLb and the second pass gate transistor PGR of the memory module 600 to be tested to turn on the second pull-up transistor PUR, so that the first pull-up transistor PUR outputs the first output current I_LMaking the second pull-up transistor PUR output a second output current I_RAnd reading the first output current I by the reading unit 200_LAnd a second output current I_RAnd (4) summing.

Therefore, the SRAM device of the present embodiment can realize the detection of each memory module 600 in the SRAM device.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for testing an SRAM cell, comprising:

providing an SRAM cell, the SRAM cell comprising: a memory cell including a first inverter and a second inverter; the first inverter comprises a first pull-up transistor and a first pull-down transistor, the drain of the first pull-up transistor is electrically connected with the source of the first pull-down transistor, the connection point of the drain of the first pull-up transistor and the source of the first pull-down transistor is a first node, the gate of the first pull-up transistor is electrically connected with the gate of the first pull-down transistor, and the connection point of the gate of the first pull-up transistor and the gate of the first pull-down transistor is a second node; the second inverter comprises a second pull-up transistor and a second pull-down transistor, the drain of the second pull-up transistor is electrically connected with the source of the second pull-down transistor, the connection point of the drain of the second pull-up transistor and the source of the second pull-down transistor is a third node, the gate of the second pull-up transistor is electrically connected with the gate of the second pull-down transistor, and the connection point of the gate of the second pull-up transistor and the gate of the second pull-down transistor is a fourth node; wherein the second node is electrically connected to the third node, and the first node is electrically connected to the fourth node; a transfer unit including a first transfer gate transistor and a second transfer gate transistor, a drain of the first transfer gate transistor being electrically connected to the first node, and a drain of the second transfer gate transistor being electrically connected to the third node; a word line electrically connected to the gate of the first pass gate transistor and the gate of the second pass gate transistor; a bit line comprising a first bit line electrically connected to the source of the first pass gate transistor and a second bit line electrically connected to the source of the second pass gate transistor; a driving unit electrically connected to the bit line, the driving unit for simultaneously loading a low level to the second node and the fourth node through the bit line and the transfer unit; a read unit electrically connected to the bit line, the read unit for reading a sum of a first output current of the first pull-up transistor and a second output current of the second pull-up transistor through the bit line and the transfer unit; the SRAM cell further includes: a first enable unit for electrically connecting the driving unit and the bit line, a second enable unit for electrically connecting the reading unit and the bit line, and a selection unit simultaneously electrically connected with the first enable unit and the second enable unit; the selection unit is used for controlling the first enabling unit and the second enabling unit to be simultaneously turned on or turned off; the first enabling unit is used for controlling the driving unit to load low level to the second node and the fourth node at the same time; the second enabling unit is used for controlling the reading unit to read the sum of the first output current of the first pull-up transistor and the second output current of the second pull-up transistor;

providing a threshold voltage reference value for the pull-up transistor;

providing a relation between a threshold voltage and an output current of the pull-up transistor;

turning on the first and second pass-gate transistors;

the driving unit loads a low level to the fourth node through the first bit line and the first transmission gate transistor, so that the second pull-up transistor is turned on, the second pull-down transistor is turned off, and the second pull-up transistor outputs a second output current; the driving unit loads a low level to the second node through the second bit line and a second transfer gate transistor at the same time, so that the first pull-up transistor is started, the first pull-down transistor is closed, and the first pull-up transistor outputs a first output current;

the reading unit reads the sum of the first output current and the second output current through the first transmission gate transistor, the first bit line, the second transmission gate transistor and the second bit line;

dividing the sum of the first output current and the second output current by two to obtain an output current detection value;

obtaining threshold voltage detection values of the first pull-up transistor and the second pull-up transistor according to the relation and the output current detection value;

and comparing the threshold voltage detection value with a threshold voltage reference value, and judging that the first pull-up transistor and the second pull-up transistor are invalid when the absolute value of the difference between the threshold voltage detection value and the threshold voltage reference value is larger than a preset difference.

2. The method of testing an SRAM cell of claim 1, wherein the first and second pull-up transistors are PMOS, and the first, second, pull-down, first, and second pass-gate transistors are NMOS.

3. The method of testing an SRAM cell of claim 1, wherein the SRAM cell further comprises an operating voltage supply and a common voltage supply;

the source electrodes of the first pull-up transistor and the second pull-up transistor are electrically connected with a working voltage power supply, and the drain electrodes of the first pull-down transistor and the second pull-down transistor are electrically connected with a common voltage power supply.

4. The method of testing an SRAM cell of claim 1, wherein the first enabling unit comprises a first transistor, the second enabling unit comprises a second transistor, and the first and second transistors are of the same transistor type;

the selection unit is used for controlling the first transistor and the second transistor to be turned on or turned off simultaneously.

5. The method of testing an SRAM cell of claim 4, wherein the first transistor comprises a first gate, a first source, and a first drain, and the second transistor comprises a second gate, a second source, and a second drain;

the first grid and the second grid are both electrically connected with the selection unit;

the first source electrode is electrically connected with the driving unit;

the first drain electrode is electrically connected with the first bit line and the second bit line;

the second source electrode is electrically connected with the first bit line and the second bit line;

the second drain is electrically connected to the read unit.

6. The method for testing the SRAM cell of claim 4, wherein the first transistor and the second transistor are both NMOS; or, the first transistor and the second transistor are both PMOS.

7. The method for testing an SRAM cell as recited in claim 1, wherein the predetermined difference of 75mV is 125 mV.

8. The method for testing an SRAM cell of claim 1, wherein in the step of the driving unit simultaneously loading the fourth node and the second node with a low level, the driving unit simultaneously grounds the first bit line and the second bit line.

9. The method of testing an SRAM cell of claim 1,

the detection method further comprises the following steps: the selection unit controls the first transistor and the second transistor to be turned on simultaneously;

in the steps that the driving unit loads a low level to the fourth node through the first bit line and the first transfer gate transistor, and loads a low level to the second node through the second bit line and the second transfer gate transistor, a first circuit loop is formed among the first transistor, the first bit line and the first transfer gate transistor, and the driving unit loads a low level to the fourth node through the first circuit loop; a second circuit loop is formed among the first transistor, the second bit line and the second transmission gate transistor, and the driving unit loads a low level to the second node through the second circuit loop;

in the step of reading the sum of the first output current and the second output current by the reading unit through the first pass gate transistor, the first bit line, the second pass gate transistor and the second bit line, a third circuit loop is formed among the first pull-up transistor, the first pass gate transistor, the first bit line and the second transistor, a fourth circuit loop is formed among the second pull-up transistor, the second pass gate transistor, the second bit line and the second transistor, and the sum of the first output current and the second output current is read by the reading unit through the third circuit loop and the fourth circuit loop.

10. A system for testing an SRAM cell, comprising:

an SRAM cell, the SRAM cell comprising: a memory cell including a first inverter and a second inverter; the first inverter comprises a first pull-up transistor and a first pull-down transistor, the drain of the first pull-up transistor is electrically connected with the source of the first pull-down transistor, the connection point of the drain of the first pull-up transistor and the source of the first pull-down transistor is a first node, the gate of the first pull-up transistor is electrically connected with the gate of the first pull-down transistor, and the connection point of the gate of the first pull-up transistor and the gate of the first pull-down transistor is a second node; the second inverter comprises a second pull-up transistor and a second pull-down transistor, the drain of the second pull-up transistor is electrically connected with the source of the second pull-down transistor, the connection point of the drain of the second pull-up transistor and the source of the second pull-down transistor is a third node, the gate of the second pull-up transistor is electrically connected with the gate of the second pull-down transistor, and the connection point of the gate of the second pull-up transistor and the gate of the second pull-down transistor is a fourth node; wherein the second node is electrically connected to the third node, and the first node is electrically connected to the fourth node; a transfer unit including a first transfer gate transistor and a second transfer gate transistor, a drain of the first transfer gate transistor being electrically connected to the first node, and a drain of the second transfer gate transistor being electrically connected to the third node; a word line electrically connected to the gate of the first pass gate transistor and the gate of the second pass gate transistor; a bit line comprising a first bit line electrically connected to the source of the first pass gate transistor and a second bit line electrically connected to the source of the second pass gate transistor; a driving unit electrically connected to the bit line, the driving unit for simultaneously loading a low level to the second node and the fourth node through the bit line and the transfer unit; a read unit electrically connected to the bit line, the read unit for reading a sum of a first output current of the first pull-up transistor and a second output current of the second pull-up transistor through the bit line and the transfer unit; the SRAM cell further includes: a first enable unit for electrically connecting the driving unit and the bit line, a second enable unit for electrically connecting the reading unit and the bit line, and a selection unit simultaneously electrically connected with the first enable unit and the second enable unit; the selection unit is used for controlling the first enabling unit and the second enabling unit to be simultaneously turned on or turned off; the first enabling unit is used for controlling the driving unit to load low level to the second node and the fourth node at the same time; the second enabling unit is used for controlling the reading unit to read the sum of the first output current of the first pull-up transistor and the second output current of the second pull-up transistor;

the calculation unit is connected with the SRAM unit and is used for dividing the sum of the first output current and the second output current of the SRAM unit by two to obtain an output current detection value and obtaining threshold voltage detection values of the first pull-up transistor and the second pull-up transistor according to a relational expression between the threshold voltage and the output current of the pull-up transistor;

and the judging unit is connected with the calculating unit and used for providing a threshold voltage reference value of the pull-up transistor, comparing the threshold voltage detection value with the threshold voltage reference value, and judging that the first pull-up transistor and the second pull-up transistor are invalid when the absolute value of the difference value between the threshold voltage detection value and the threshold voltage reference value is greater than a preset difference value.

11. The system for sensing the SRAM cell of claim 10, wherein the predetermined difference of 75mV is 125 mV.

12. An SRAM device, comprising:

a plurality of memory modules arranged in a matrix, the memory modules including memory cells and transfer units; the memory cell comprises a first inverter and a second inverter; the first inverter comprises a first pull-up transistor and a first pull-down transistor, the drain of the first pull-up transistor is electrically connected with the source of the first pull-down transistor, the connection point of the drain of the first pull-up transistor and the source of the first pull-down transistor is a first node, the gate of the first pull-up transistor is electrically connected with the gate of the first pull-down transistor, and the connection point of the gate of the first pull-up transistor and the gate of the first pull-down transistor is a second node; the second inverter comprises a second pull-up transistor and a second pull-down transistor, the drain of the second pull-up transistor is electrically connected with the source of the second pull-down transistor, the connection point of the drain of the second pull-up transistor and the source of the second pull-down transistor is a third node, the gate of the second pull-up transistor is electrically connected with the gate of the second pull-down transistor, and the connection point of the gate of the second pull-up transistor and the gate of the second pull-down transistor is a fourth node; the second node is electrically connected with the third node, and the first node is electrically connected with the fourth node; the transfer unit comprises a first transfer gate transistor and a second transfer gate transistor, wherein the drain electrode of the first transfer gate transistor is electrically connected with the first node, and the drain electrode of the second transfer gate transistor is electrically connected with the third node;

a plurality of word lines, each word line being electrically connected to the gates of the first pass gate transistor and the second pass gate transistor in the same row of the matrix;

a plurality of bit lines including a plurality of first bit lines and a plurality of second bit lines alternately arranged, each first bit line being electrically connected to the sources of the first pass-gate transistors in the same column of the matrix, and each second bit line being electrically connected to the sources of the second pass-gate transistors in the same column of the matrix;

a driving unit electrically connected to the plurality of bit lines, the driving unit for simultaneously loading a low level to the second node and the fourth node through the bit lines and the transfer unit;

a reading unit electrically connected to the bit lines, the reading unit being configured to read a sum of a first output current of the first pull-up transistor and a second output current of the second pull-up transistor through the bit lines and the transfer unit, so as to perform a test on the memory module according to the test method of any one of claims 1 to 9;

the SRAM device further includes: the first enabling units are used for electrically connecting the driving unit and a plurality of bit lines, correspond to the memory modules one by one and are electrically connected with the bit lines of the corresponding memory modules; the plurality of second enabling units are used for electrically connecting the reading unit and a plurality of bit lines, correspond to the plurality of storage modules one by one and are electrically connected with the bit lines of the corresponding storage modules; a selection unit electrically connected to the plurality of first enable units and the plurality of second enable units at the same time;

the selection unit is used for controlling the first enabling unit and the second enabling unit corresponding to the same storage module to be simultaneously turned on or turned off;

the first enabling unit is used for controlling the driving unit to load low levels to the second node and the fourth node of the corresponding storage module at the same time;

the second enabling unit is used for controlling the reading unit to read the sum of the first output current of the first pull-up transistor and the second output current of the second pull-up transistor of the corresponding storage module.

13. The SRAM device of claim 12, wherein the first pull-up transistor and the second pull-up transistor are PMOS, and the first pull-down transistor, the second pull-down transistor, the first pass gate transistor, and the second pass gate transistor are NMOS.

14. The SRAM device of claim 12, further comprising an operating voltage supply and a common voltage supply;

the source electrodes of the first pull-up transistor and the second pull-up transistor in the SRAM device are electrically connected with a working voltage power supply, and the drain electrodes of the first pull-down transistor and the second pull-down transistor are electrically connected with a common voltage power supply.

15. The SRAM device of claim 12, wherein the first enable cell comprises a first transistor, the second enable cell comprises a second transistor, and the transistors of the first and second transistors are of the same type;

the selection unit is used for controlling the first transistor and the second transistor corresponding to the same storage module to be simultaneously turned on or turned off.

16. The SRAM device of claim 15, wherein the first transistor comprises a first gate, a first source, and a first drain, and the second transistor comprises a second gate, a second source, and a second drain;

the first source electrode is electrically connected with the driving unit;

the first drain electrode is electrically connected with the first bit line and the second bit line of the corresponding storage module;

the second source electrode is electrically connected with the first bit line and the second bit line of the corresponding storage module;

the second drain is electrically connected to the read unit.

17. The SRAM device of claim 15, wherein the first transistor and the second transistor are both NMOS; or, the first transistor and the second transistor are both PMOS.