CN104681585A - Organic light emitting diode display device and method of fabricating the same - Google Patents
Organic light emitting diode display device and method of fabricating the same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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Abstract
The invention provides an organic light emitting diode display device and a method of fabricating the same. The OLED display device comprises a first oxide semiconductor layer comprises a first area, a second area, a third area and a fourth area; a first insulation layer located on the first oxide semiconductor layer; a first grid electrode that is located on the first insulation layer and completely coincides with the first area; a first storage electrode that extends from the first grid electrode and coincides with the second area; a second insulation layer covering the first grid electrode and the first storage electrode and exposing the third area and the fourth area; a first source electrode and a drain electrode which are located on the second insulation layer and are in contact with the third area and the fourth area; a light emitting diode connected to the first drain electrode. Part of the second area at the edge of the first storage electrode beyond the center of the first storage electrode is conductive, so that a second storage electrode is formed. The first storage electrode, the second storage electrode and the first insulation layer form a first storage capacitor.
Description
This application claims the benefit of priority of the korean patent application No.10-2013-0144341 that on November 26th, 2013 submits in Korea S, this patent application is incorporated herein by reference.
Technical field
The present invention relates to a kind of Organic Light Emitting Diode (OLED) display unit, more particularly, relate to OLED display and the manufacture method thereof of a kind of memory capacity raising.
Background technology
Recently, along with society enters the information age, the various types of display unit signal of telecommunication of all kinds being shown as visual pattern are rapidly developed.Such as, liquid crystal display (LCD) device and Organic Light Emitting Diode (OLED) display unit are extensively introduced, as the substitute of cathode ray tube type display unit.
OLED display as novel flat-plate display unit is emissive type.OLED display has the excellent characteristic such as visual angle, contrast.In addition, because OLED display does not need backlight assembly, therefore OLED display has low weight and low-power consumption.In addition, OLED display has the advantages such as the high speed of response, low production cost.In addition, all elements of OLED display are solid-state phases, and the ability that OLED display resists external impact is strong.Especially, there is large advantage in production cost.The manufacturing process of OLED display is very simple, needs depositing device and sealed in unit.
In active array type OLED device, the voltage for the electric current controlling pixel is charged in holding capacitor, the size of electric current is kept, until next frame.
Fig. 1 is the circuit diagram of a pixel region of the OLED display of correlation technique.
As shown in fig. 1, OLED display comprises the select lines GL along first direction, the data wire DL along second direction, switching thin-film transistor (TFT) Tsw, holding capacitor Cst, drive TFT Tdr and light-emitting diode E.Select lines GL and data wire DL is intersected with each other to limit pixel region P.
Switching TFT Tsw is arranged on the cross section of select lines GL and data wire DL and is connected to select lines GL and data wire DL.Drive TFT Tdr is electrically connected to switching TFT Tsw.
Drive TFT Tdr and holding capacitor Cst is connected to switching TFT Tsw and high level voltage VDD.Light-emitting diode E is connected to drive TFT Tdr and low level voltage VSS.
When switching TFT Tsw is because of the gating signal applied by select lines GL during conducting, the data-signal from data wire DL is applied to the grid of drive TFT Tdr and the electrode of holding capacitor Cst.When drive TFT Tdr factor data signal during conducting, from high level voltage VDD to light-emitting diode E for induced current.As a result, light-emitting diode E is luminous.In this case, when drive TFT Tdr conducting, the size to the electric current of light-emitting diode E is determined, makes light-emitting diode E to produce GTG.
Holding capacitor Cst is used for the voltage of the grid keeping drive TFT Tdr when switching TFT Tsw ends.Therefore, even if switching TFT Tsw cut-off, the size to the electric current of light-emitting diode E is also retained to next frame.
In order to production high-definition display device, the quantity of the pixel region P in unit are should be increased.That is, in high-definition display device, the size of a pixel region P reduces.
When the size of a pixel region P reduces, the size of holding capacitor Cst also reduces, so that storage capacitance reduces.
When the size increasing holding capacitor Cst is to provide high storage capacitance, aperture is than reducing.
Summary of the invention
Therefore, the present invention is devoted to a kind of OLED display substantially eliminating one or more problem that restriction and shortcoming due to correlation technique cause.
Supplementary features of the present invention and advantage will be set forth in the description that follows and part be become apparent according to description, or learn by practice of the present invention.Structure by particularly pointing out in written description and claims and accompanying drawing thereof is realized and obtains these and other advantage of the present invention.
According to the present invention, as implemented herein and generalized description, a kind of organic LED display device comprises: the first oxide semiconductor layer, and it comprises the firstth district to the 4th district; First insulating barrier, it is on described first oxide semiconductor layer; First grid, it is with described firstth district completely overlapping on described first insulating barrier; First storage electrode, it to extend and overlapping with described secondth district from described first grid; Second insulating barrier, it covers described first grid and described first storage electrode and is exposed in described 3rd district and the 4th district; First source electrode and the first drain electrode, it is on described second insulating barrier and contact described 3rd district and described 4th district; Light-emitting diode, it is connected to described first drain electrode, wherein, the part in described secondth district of the edge of described first storage electrode except the center except described first storage electrode is conduction, to form the second storage electrode, and described first storage electrode, described second storage electrode and described first insulating barrier form the first holding capacitor.
On the other hand, a kind of method manufacturing organic LED display device, the method comprises: on substrate, form oxide semiconductor layer; Firstth district of described oxide semiconductor layer forms the first insulating pattern and grid, and form the second insulating pattern and the first storage electrode in the secondth district of described oxide semiconductor layer; By performing plasma treatment, reduce the part in described secondth district inside the edge of described first storage electrode; Form insulating barrier, the 3rd district in described first both sides, district of described oxide semiconductor layer and the 4th district expose and cover described grid and described first storage electrode by described insulating barrier; Described insulating barrier is formed source electrode and the drain electrode in described 3rd district of contact and described 4th district; And formed and the described light-emitting diode be connected that drains.
Be appreciated that above describe, in general terms and following detailed description are all exemplary and illustrative and are intended to further illustrate claimed the invention provides.
Accompanying drawing explanation
Accompanying drawing is included to provide a further understanding of the present invention, to be incorporated in this specification and to form the part of this specification, and accompanying drawing illustrates embodiments of the present invention and together with the description for illustration of principle of the present invention.
Fig. 1 is the circuit diagram of a pixel region of the OLED display of correlation technique.
Fig. 2 is the circuit diagram according to OLED display of the present invention.
Fig. 3 is the plane graph of a part for OLED display according to first embodiment of the invention.
Fig. 4 A and Fig. 4 B is plane graph and the cutaway view of the first holding capacitor in Fig. 3 respectively.
Fig. 5 is the cutaway view intercepted along V-V' line in Fig. 3.
Fig. 6 is the cutaway view intercepted along VI-VI' line in Fig. 3.
Fig. 7 is the plane graph for illustration of the problem in holding capacitor.
Fig. 8 A to Fig. 8 D is the cutaway view of the manufacture process that the first holding capacitor is shown.
Fig. 9 is the plane graph of a part for OLED display second embodiment of the invention.
Figure 10 is the plane graph of the 3rd holding capacitor in Fig. 9.
Figure 11 is the cutaway view intercepted along XI-XI' line in Fig. 9.
Embodiment
Now, will in detail with reference to the preferred embodiment of the present invention, the example of these execution modes shown in the drawings.
Fig. 2 is the circuit diagram according to OLED display of the present invention.
As shown in Figure 2, OLED display according to the present invention comprises switching thin-film transistor (TFT) Ts, drive TFT Td, with reference to TFT Tr, holding capacitor Cst and light-emitting diode E a pixel region.
In more detail, the select lines GL extended along first direction and the data wire DL along second direction extension is intersected with each other, to limit pixel region.In addition, formed to the power line VDD of drive TFT Td applying high level voltage with to the reference line RL applying reference voltage with reference to TFT Tr.
In each pixel region, form switching TFT Ts, drive TFT Td, with reference to TFT Tr, holding capacitor Cst and light-emitting diode E.
The grid of switching TFT Ts and source electrode are connected respectively to select lines GL and data wire DL, to receive gating signal and data-signal.The grid of drive TFT Td is connected to the drain electrode of switching TFT Ts.
The drain electrode of drive TFT Td is connected to the drain electrode of reference TFT Tr and first electrode (that is, anode) of light-emitting diode E, and the source electrode of drive TFT Td is connected to power line VDD.Second electrode (that is, negative electrode) of light-emitting diode E is connected to low level voltage.
Grid with reference to TFT Tr is connected to select lines GL, and the source electrode with reference to TFT Tr is connected to reference line RL.The source electrode of reference TFT " Tr " and the position of drain electrode can be changed.That is, the source electrode of reference TFT Tr is connected to the drain electrode of drive TFT Td, and the drain electrode with reference to TFT Tr is connected to reference line RL.In addition, the grid with reference to TFT Tr can be connected to another signal line, and is free of attachment to select lines GL.
Holding capacitor Cst comprises the first holding capacitor Cst1 (in Fig. 3) and the second holding capacitor Cst2 (in Fig. 3).
First storage electrode of the first holding capacitor Cst1 is electrically connected to the drain electrode of switching TFT Ts and the grid of drive TFT Td, and second storage electrode of the first holding capacitor Cst1 is electrically connected to the drain electrode of drive TFT Td.
In addition, first storage electrode of the second holding capacitor Cst2 is electrically connected to the drain electrode of drive TFT Td, and second storage electrode of the second holding capacitor Cst2 is electrically connected to the drain electrode of switching TFT Ts and the grid of drive TFT Td.
Switching TFT Ts carries out switch because of gating signal, provides data-signal with the grid to drive TFT Td, and drive TFT Td factor data signal carries out switch, to control the electric current passing into light-emitting diode E.Voltage for the electric current controlling light-emitting diode E is charged in holding capacitor Cst, makes the size of electric current be retained to next frame.
When switching TFT Ts is because of the gating signal applied by select lines GL during conducting, the data-signal from data wire DL is applied to the grid of drive TFT Td, makes drive TFT Td conducting.When drive TFT Td factor data signal during conducting, from power line VDD to light-emitting diode E for induced current.As a result, light-emitting diode E is luminous.In this case, when drive TFT Td conducting, to the size of the electric current of light-emitting diode E by what determine, light-emitting diode E is made to produce GTG.
Holding capacitor Cst is used for the voltage of the grid keeping drive TFT Td when switching TFT Tsw ends.Therefore, even if switching TFT Tsw cut-off, the size to the electric current of light-emitting diode E is also retained to next frame.
When with reference to TFT Tr conducting, the drain electrode with reference to TFT Tr is connected to the drain electrode of drive TFT Td, and the characteristic deviation of drive TFT Td is reduced.That is, because the characteristic deviation of drive TFT Td reduces to minimum because having three TFT in a pixel region, therefore the aperture of OLED display is than improving.On the other hand, can omit with reference to TFTTr.
In the present invention, the storage capacitance of holding capacitor Cst increases or is maximized, and aperture is than not reducing.As a result, the high-resolution OLED display of aperture than improving is provided.In addition, because the deviation of drive TFT Td reduces, the luminance difference of OLED display is therefore prevented.
Fig. 3 is the plane graph of a part for OLED display according to first embodiment of the invention, and Fig. 4 A and Fig. 4 B is plane graph and the cutaway view of the first holding capacitor in Fig. 3 respectively.
As shown in Figure 3, in OLED display according to first embodiment of the invention, select lines GL and data wire DL is intersected with each other, to limit pixel region.In addition, power line VDD and data wire DL separates and is parallel to data wire DL, and to intersect with select lines GL, reference line RL and select lines GL separates and is parallel to select lines GL, to intersect with data wire DL and power line VDD.
In each pixel region, form switching TFT Ts (in Fig. 2), drive TFT Td (in Fig. 2), with reference to TFT Tr (in Fig. 2), holding capacitor Cst (in Fig. 2) and light-emitting diode E (in Fig. 2).
Drive TFT Td comprises the first oxide semiconductor layer 110, first grid 142, first source electrode 162 and the first drain electrode 164, switching TFT Ts and comprises the second oxide semiconductor layer 120, second grid 144, second source electrode 166 and the second drain electrode 168.
Reference is Fig. 5 of the cutaway view along the intercepting of V-V' line of Fig. 3, first district 111 of the first oxide semiconductor layer 110 is overlapping with the raceway groove serving as drive TFT Td with first grid 142, and the first source electrode 162 contacts the 3rd district 113 in the first both sides, district 111 and the 4th district 114 of the first oxide semiconductor layer 110 respectively with the first drain electrode 164.In this case, the oxide semiconductor material in the 3rd district 113 of the first oxide semiconductor layer 110 and the 4th district 114 is reduced, and makes the 3rd district 113 and the 4th district 114 have conduction property.
Namely, first grid insulating barrier 130 and first grid 142 are stacked in the first district 111 of the first oxide semiconductor layer 110, and form the second insulating barrier 150 to cover first grid 142, the second insulating barrier 150 comprises the first semiconductor interface contact hole 151 and the second semiconductor interface contact hole 152 exposed in the 3rd district 113 of the first oxide semiconductor layer 110 and the 4th district 114 respectively.First source electrode 162 and the first drain electrode 164 to be formed on the second insulating barrier 150 and to contact the 3rd district 113 and the 4th district 114 of the first oxide semiconductor layer 110 respectively by the first semiconductor interface contact hole 151 with the second semiconductor interface contact hole 152.In this case, in the step of formation first insulating barrier 130 and first grid 142, each in the 3rd district 113 of the first oxide semiconductor layer 110 and the 4th district 114 is reduced into conduction because of plasma treatment.First insulating barrier 130 can be gate insulation layer, and the second insulating barrier 150 can be interlayer insulating film.
Reference is Fig. 6 of the cutaway view along the intercepting of VI-VI' line of Fig. 3, first district 121 of the second oxide semiconductor layer 120 is overlapping with the raceway groove serving as switching TFT Ts with second grid 144, and the second source electrode 166 contacts the second district 122 in the first both sides, district 121 and the 3rd district 123 of the second oxide semiconductor layer 120 respectively with the second drain electrode 168.In this case, the oxide semiconductor material in the second district 122 of the second oxide semiconductor layer 120 and the 3rd district 123 is reduced, and makes the second district 122 and the 3rd district 123 have conduction property.
Namely, first grid insulating barrier 130 and second grid 144 are stacked in the first district 121 of the second oxide semiconductor layer 120, and form the second insulating barrier 150 to cover second grid 144, the second insulating barrier 150 also comprises the 3rd semiconductor interface contact hole 153 and the 4th semiconductor interface contact hole 154 exposed in the second district 122 of the second oxide semiconductor layer 120 and the 3rd district 123 respectively.Second source electrode 166 and the second drain electrode 168 to be formed on the second insulating barrier 150 and to contact the second district 122 and the 3rd district 123 of the second oxide semiconductor layer 120 respectively by the 3rd semiconductor interface contact hole 153 with the 4th semiconductor interface contact hole 154.In this case, in the step of formation first insulating barrier 130 and second grid 144, each in the second district 122 of the second oxide semiconductor layer 120 and the 3rd district 123 is reduced into conduction because of plasma treatment.
Refer again to Fig. 3, comprise trioxide semiconductor layer, the 3rd grid 148, the 3rd source electrode 172 and the 3rd drain electrode 174 with reference to TFT Tr.In figure 3, the 3rd drain electrode 174 of reference TFT Tr and first drain electrode 164 of drive TFT Td are identical elements.Alternatively, can be formed as being separated from each other with reference to the 3rd drain electrode 174 of TFT Tr with first drain electrode 164 of drive TFT Td and be electrically connected to each other by being connected pattern.In addition, in figure 3, trioxide semiconductor layer is a part for the first oxide semiconductor layer 110.Alternatively, trioxide semiconductor layer can be formed to separate with the first oxide semiconductor layer 110.
Refer again to Fig. 5,6th district 116 of the first oxide semiconductor layer 110 and the 3rd grid 148 overlapping with the raceway groove served as with reference to TFT Tr, the 3rd source electrode 172 and the 3rd drain electrode 174 contact the 4th district 114 in the 6th both sides, district 116 and the SECTOR-SEVEN 117 of the first oxide semiconductor layer 110 respectively.The other end that one end of 3rd source electrode 172 contacts the first oxide semiconductor layer the 110, three source electrode 172 by the 5th semiconductor interface contact hole 156 contacts reference line RL by reference to contact hole 157.In this case, the oxide semiconductor material in the 4th district 114 of the first oxide semiconductor layer 110 and SECTOR-SEVEN 117 is reduced, and makes the 4th district 114 and SECTOR-SEVEN 117 have conduction property.
Refer again to Fig. 3, switching TFT Ts is electrically connected to select lines GL and data wire DL and is arranged on the cross section of select lines GL and data wire DL.That is, the second grid 144 of switching TFT Ts is connected to select lines GL, and second source electrode 166 of switching TFT Ts is connected to data wire DL.
The first grid 142 of drive TFT Td is electrically connected to second drain electrode 168 of switching TFT Ts.That is, the extension 170 extended from second drain electrode 168 of switching TFT Ts is contacted by grid contact hole 155 with the first grid 142 of drive TFT Td, makes the first grid 142 of drive TFT Td be electrically connected to second drain electrode 168 of switching TFT Ts.In more detail, the extension 170 of second drain electrode 168 of switching TFT Ts contacts the extension 146 of the first grid 142 of drive TFT Td.In addition, first source electrode 162 of drive TFT Td is connected to power line VDD, and first drain electrode 164 of drive TFT Td is connected to the 3rd drain electrode 174 with reference to TFT Tr.
In figure 3, drive TFT Td and reference TFT Tr common drain.Alternatively, drive TFT Td the first drain electrode 164 and with reference to the 3rd drain electrode 174 of TFT Tr can be formed be separately and can be electrically connected.
The 3rd grid 148 with reference to TFT Tr is connected to select lines GL, and the 3rd source electrode 172 with reference to TFT Tr is connected to reference line RL.
The extension 170 of extension 146, first source electrode 162, second source electrode 166 of first grid 142, second grid 144 and the 3rd grid 148, first grid 146 and the 3rd source electrode 172, first drain electrode 164, second drain electrode 168 and the 3rd drain electrode 172, second drain electrode 168 comprises low-resistance metal material, such as, aluminium (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr) and their alloy.
Light-emitting diode E is connected to first drain electrode 164 of drive TFT Td and comprises anode, organic luminous layer and negative electrode.Such as, anode is connected to first drain electrode 164 of drive TFT Td.In OLED display, the light from organic luminous layer passes anode and substrate 101 or passes negative electrode.That is, OLED display is bottom emissive type or top emission structure.
Anode comprises the electric conducting material of relatively high work function, and negative electrode comprises the electric conducting material of relatively low work function.Such as, anode can comprise the transparent conductive material of such as indium tin oxide (ITO) or indium-zinc oxide (IZO).Negative electrode can comprise Al, magnesium (Mg), silver (Ag), gold (Au) and their alloy.
In top emission structure OLED display, negative electrode has relatively little thickness, to have the light transmittance of about 45% to 50%.In addition, in top emission structure OLED display, anode also can comprise the reflector of opaque reflective conductive material.Such as, reflector comprises aluminium-palladium-copper (APC) alloy, and anode can comprise the three-decker of ITO/APC/ITO.
Organic luminous layer has single layer structure.On the other hand, in order to strengthen luminous efficiency, organic luminous layer can comprise the sandwich construction of the hole injection layer be stacked on anode, hole transmission layer, luminous material layer, electron transfer layer and electron injecting layer.Organic luminous layer comprises emitting red light pattern, green emitting pattern and blue-light-emitting pattern in pixel region.
In Organic Light Emitting Diode E, the hole from anode and the electronics from negative electrode compound in organic luminous layer, to produce exciton.Exciton is transformed into ground state from excitation state, makes organic luminous layer luminous.
Organic Light Emitting Diode E is formed with substrate 101 (in Fig. 5) top of drive TFT Td above can being formed in, or can be formed on the opposing substrate (counter substrate, not shown) of substrate 101.
Holding capacitor Cst comprises the first holding capacitor Cst1.A part for first oxide semiconductor layer 110 and the extension of first grid 142 overlapping, to form the first holding capacitor Cst1.
The second storage electrode 118 of the first storage electrode 149 of the marginal portion of the extension 146 as first grid 142 and the marginal portion as the second district 112 of the first semiconductor layer 110 is comprised with reference to Fig. 4 A and Fig. 4 B, the first holding capacitor Cst1.During the step of extension 146 forming first grid 142 or after this, the first oxide semiconductor layer 110 is reduced because of plasma treatment.In this case, because stop mask is served as in the extension 146 of first grid 142, marginal portion in the second district 112 of therefore the first oxide semiconductor layer 110 except the core in the second district 112 is reduced into conduction.That is, because the core in the second district 112 is stopped by the extension 146 of first grid 142 and the first insulating barrier 130, therefore the core in the second district 112 is not reduced and keeps non-conductive character.
Second storage electrode 118 is about 1.5 microns from the width that the edge termination of the extension 146 of first grid 142 is started at.
Therefore, the first holding capacitor Cst1 is formed as the first storage electrode 149 of the marginal portion of the extension 146 of first grid 142 and overlapping second storage electrode 118 of marginal portion in the second district 112 as the first oxide semiconductor layer 110 of the first storage electrode 149 and the first insulating barrier 130 between the first storage electrode 149 and the second storage electrode 118.
In addition, holding capacitor Cst also comprises the second holding capacitor Cst2.With reference to Fig. 5 and Fig. 6, the second holding capacitor Cst2 comprise the 5th district 115 of the conduction as the first oxide semiconductor layer 110 the 3rd storage electrode, as the second drain electrode the 4th storage electrode of extension 170 of 168 and the second insulating barrier 150 as the dielectric layer between the 3rd storage electrode and the 4th storage electrode.
In OLED display of the present invention, because the first holding capacitor Cst1 and the second holding capacitor Cst2 uses the second district 112 of the first oxide semiconductor layer 110 and the 5th district 115 as the second storage electrode and the 3rd storage electrode respectively, so storage capacitance increases or is maximized, and aperture is than not reducing.
In this case, because the first holding capacitor Cst1 is formed along the marginal portion of the extension 146 of first grid 142, therefore the first storage electrode 149 is relative little with the area of the second storage electrode 118.But because the first insulating barrier 130 of the dielectric layer as the first holding capacitor Cst1 has relatively little thickness, therefore the first holding capacitor Cst1 has enough storage capacitances.
Second holding capacitor Cst2 comprises the second insulating barrier 150 as the dielectric layer between the 3rd storage electrode and the 4th storage electrode, and the first holding capacitor Cst1 comprises the first insulating barrier 130 as the dielectric layer between the first storage electrode 149 and the second storage electrode 118.First insulating barrier 130 is formed by inorganic insulating material and has the first thickness.Second insulating barrier 150 is formed by organic insulating material and has second thickness larger than the first thickness.Therefore, although the area of first storage electrode 149 of the first holding capacitor Cst1 and the second storage electrode 118 is less than the 3rd storage electrode of the second holding capacitor Cst2 and the area of the 4th storage electrode, the first holding capacitor Cst1 and the second holding capacitor Cst2 have approximate or substantially the same storage capacitance.
In more detail, the first insulating barrier 130 is formed by inorganic insulating material (such as, Si oxide or silicon nitride) and has the first thickness of about 100 dust to 200 dusts.On the other hand, the second insulating barrier 150 is formed by organic insulating material (such as, photosensitive acrylic, photo-acryl) and has the second thickness of about 300 dust to 600 dusts.In order to make the parasitic capacitance between each and grid in source electrode and drain electrode minimum and minimum with the ladder difference of lower panel element, with organic insulating material the second insulating barrier 150 is formed thicker.
First insulating barrier 130 and the second insulating barrier 150 serve as the dielectric layer of the first holding capacitor Cst1 and the second holding capacitor Cst2 respectively, provide storage capacitance " C " with equation below:
C＝ε×A/d
(ε: dielectric constant, A: the area of storage electrode, d: the distance between storage electrode)
The dielectric constant " ε " of storage capacitance " C " and storage electrode area " A " and dielectric layer be directly proportional and and distance " d " between storage electrode be inversely proportional to.Electrode area " A " is larger, and dielectric constant " ε " is that high and between storage electrode distance " d " is less, and storage capacitance " C " increases.
Comprise
extremely
the first thickness the first insulating barrier 130 the first holding capacitor Cst1 in the first storage electrode 149 and the second storage electrode 118 between distance be comprise
extremely
the second thickness the second insulating barrier 150 the second holding capacitor Cst2 in the 3rd storage electrode and the 4th storage electrode between distance about 1/3rd (1/3).Therefore, when the area of the first holding capacitor Cst1 equals the area of the second holding capacitor Cst2, the storage capacitance of the first holding capacitor Cst1 is three times of the storage capacitance of the second holding capacitor Cst2.
Therefore, although the area of the first holding capacitor Cst1 is less than the area of the second holding capacitor Cst2, the first holding capacitor Cst1 has enough storage capacitances.As a result, when being down to minimum by the reduction of aperture ratio, storage capacitance is maximum.
Refer again to Fig. 4 A, the first holding capacitor Cst1 is formed in a part for the first oxide semiconductor layer 110.In this case, the current path of drive TFT Td should not be stored capacitor Cst1 and stops.That is, the extension 146 comprising the first storage electrode 149 of first grid 142 does not stride across the first oxide semiconductor layer 110.In other words, the both sides of the extension 146 of the first grid 142 in the current path of drive TFT Td are arranged on the first oxide semiconductor layer 110 inside.
Such as, as as shown in Fig. 7 of the plane graph for illustration of the problem in holding capacitor, when the side of the extension 146 of the first grid 142 in the current path of drive TFT Td strides across the first oxide semiconductor layer 110 to protrude past the first oxide semiconductor layer 110, stopped from the electric current of the first source electrode 162 to the first drain electrode 164.In this case, the grid of drive TFT Td is also served as in the extension 146 of first grid 142, makes the second district 112 of the first oxide semiconductor layer 110 serve as the raceway groove of drive TFT Td.As a result, do not provide required raceway groove, the character of drive TFT Td changes.
In order to prevent above problem, the extension 146 comprising the first storage electrode 149 of first grid 142 does not stride across the first oxide semiconductor layer 110.
In other words, second district 112 of the first oxide semiconductor layer 110 has the first length " d1 " relative to first direction, first direction intersects with 164 second directions be connected that the first source electrode 162 and first to be drained along the first oxide semiconductor layer 110, overlapping region (that is, the overlapping region between the first storage electrode 149 and the second district 112) between the extension 146 of first grid 142 and the second district 112 has the second length " d2 " relative to first direction.Second length " d2 " is less than the first length " d1 ".
As shown in Figure 7, when the 3rd length " d3 " in the second district 112 equals the 4th length " d4 " of overlapping region between the first storage electrode 149 and the second district 112, current path between first source electrode 162 and the first drain electrode 164 is stopped, makes the property-deterioration of drive TFT Td.
Fig. 8 A to Fig. 8 D is the cutaway view of the manufacture process that the first holding capacitor is shown.
As shown in Figure 8 A, oxide semiconductor layer is deposited on the substrate 101 and carries out composition by mask process, to form the first oxide semiconductor layer 110 (in Fig. 5) comprising the second district 112.Such as, oxide semiconductor material can comprise the one in indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium-zinc oxide (IZO), indium gallium oxide (IGO) and indium aluminium zinc oxide (IAZO).
Next, as seen in fig. 8b, inorganic insulating material floor 132 and metal level 134 are sequentially deposited in the second district 112 of the first oxide semiconductor layer 110, metal level 134 is formed photoresist (photoresist, PR) pattern 190, to correspond to the extension 146 (in Fig. 5) of first grid 142 (in Fig. 5).Inorganic insulating material layer 132 can comprise Si oxide or silicon nitride.
Next, as seen in fig. 8 c, use PR pattern 190 as etching mask etching inorganic insulating material layer 132 (in Fig. 8 B) and metal level 134 (in Fig. 8 B), to form extension 146 and first insulating barrier 130 of first grid 142.
Next, as seen in fig. 8d, use at least one in PR pattern 190, extension 146 and the first insulating barrier 130 as stop mask, plasma treatment is performed to the second district 112 of the first oxide semiconductor layer 110, to reduce the second district 112 of the first oxide semiconductor layer 110.Such as, plasma treatment uses the second district 112 of sulphur hexafluoride (SF6) gas or carbon tetrafluoride (CF4) gas reduction first oxide semiconductor layer 110.In this case, after eliminating PR pattern 190, plasma treatment can be performed.
Owing to a part for the first oxide semiconductor layer 110 should be reduced by plasma treatment, therefore the first insulating barrier 130 is of similar shape with the extension 146 of first grid 142.That is, the first insulating barrier 130 has substantially the same island-like shape with the extension 146 of first grid 142.
By reducing the first oxide semiconductor layer 110 by plasma treatment, the first oxide semiconductor layer 110 of the outside, extension 146 of first grid 142 is reduced.In addition, by the interior section of the first oxide semiconductor layer 110 below the extension 146 of the gas reduction first grid 142 of plasma treatment.That is, by plasma treatment, the second district 112 of the first oxide semiconductor layer 110 is divided into the center 112a be not reduced and the marginal zone 112b being reduced into conduction, and marginal zone 112b serves as the second storage electrode 118 (Fig. 4 B).
Therefore, provide the first holding capacitor Cst1 of the first insulating barrier 130 comprised as dielectric layer, the holding capacitor Cst of OLED display has enough storage capacitances and the reduction of aperture ratio is prevented from or is minimized.
Fig. 9 is the plane graph of a part for OLED display second embodiment of the invention.Figure 10 is the plane graph of the 3rd holding capacitor in Fig. 9, and Figure 11 is the cutaway view intercepted along XI-XI' line in Fig. 9.
As shown in FIG. 9 to 11, in OLED display second embodiment of the invention, select lines GL and data wire DL is intersected with each other, to limit pixel region.In addition, power line VDD and data wire DL separates and is parallel to data wire DL, and to intersect with select lines GL, reference line RL and select lines GL separates and is parallel to select lines GL, to intersect with data wire DL and power line VDD.
In each pixel region, form switching TFT Ts (in Fig. 2), drive TFT Td (in Fig. 2), with reference to TFT Tr (in Fig. 2), holding capacitor Cst (in Fig. 2) and light-emitting diode E (in Fig. 2).
Drive TFT Td comprises the first oxide semiconductor layer 210, first grid 242, first source electrode 262 and the first drain electrode 264, switching TFT Ts and comprises the second oxide semiconductor layer 220, second grid 244, second source electrode 266 and the second drain electrode 268.
First district's (not shown) of the first oxide semiconductor layer 210 and first grid 242 overlapping with the raceway groove serving as drive TFT Td, the 3rd district in the first (not shown) both sides, district and the 4th district's (not shown) that the first source electrode 262 and the first drain electrode 264 contact the first oxide semiconductor layer 210 respectively.In this case, the oxide semiconductor material in the 3rd district of the first oxide semiconductor layer 210 and the 4th district's (not shown) is reduced, and makes the 3rd district and the 4th district's (not shown) have conduction property.
Namely, first grid insulating barrier 230 and first grid 242 are stacked on first district's (not shown) of the first oxide semiconductor layer 210, and form the second insulating barrier 250 to cover first grid 242, the second insulating barrier 250 comprises the first semiconductor interface contact hole 251 and the second semiconductor interface contact hole 252 exposed in the 3rd district of the first oxide semiconductor layer 110 and the 4th district's (not shown) respectively.First source electrode 262 and the first drain electrode 264 to be formed on the second insulating barrier 250 and to contact the 3rd district and the 4th district's (not shown) of the first oxide semiconductor layer 210 respectively by the first semiconductor interface contact hole 251 with the second semiconductor interface contact hole 252.In this case, in the step of formation first insulating barrier 230 and first grid 242, each in the 3rd district of the first oxide semiconductor layer 210 and the 4th district's (not shown) is reduced into conduction because of plasma treatment.First insulating barrier 230 can be gate insulation layer, and the second insulating barrier 250 can be interlayer insulating film.
First district's (not shown) of the second oxide semiconductor layer 220 and second grid 244 overlapping with the raceway groove serving as switching TFT Ts, the secondth district in the first (not shown) both sides, district and the 3rd district's (not shown) that the second source electrode 266 and the second drain electrode 268 contact the second oxide semiconductor layer 220 respectively.In this case, the oxide semiconductor material in the secondth district of the second oxide semiconductor layer 220 and the 3rd district's (not shown) is reduced, and makes the secondth district and the 3rd district's (not shown) have conduction property.
Namely, first grid insulating barrier 230 and second grid 244 are stacked on first district's (not shown) of the second oxide semiconductor layer 220, and form the second insulating barrier 250 to cover second grid 244, the second insulating barrier 250 also comprises the 3rd semiconductor interface contact hole 153 and the 4th semiconductor interface contact hole 154 exposed in the secondth district of the second oxide semiconductor layer 220 and the 3rd district's (not shown) respectively.Second source electrode 266 and the second drain electrode 268 to be formed on the second insulating barrier 250 and to contact the secondth district and the 3rd district's (not shown) of the second oxide semiconductor layer 220 respectively by the 3rd semiconductor interface contact hole 253 with the 4th semiconductor interface contact hole 254.In this case, in the step of formation first insulating barrier 230 and second grid 244, each in the secondth district of the second oxide semiconductor layer 220 and the 3rd district's (not shown) is reduced into conduction because of plasma treatment.
Trioxide semiconductor layer, the 3rd grid 248, the 3rd source electrode 272 and the 3rd drain electrode 274 is comprised with reference to TFT Tr.In fig .9, the 3rd drain electrode 274 of reference TFT Tr and first drain electrode 264 of drive TFT Td are identical elements.Alternatively, can be formed as being separated from each other with reference to the 3rd drain electrode 274 of TFT Tr with first drain electrode 264 of drive TFT Td and be electrically connected to each other by being connected pattern.In addition, in fig .9, trioxide semiconductor layer is a part for the first oxide semiconductor layer 210.Alternatively, trioxide semiconductor layer can be formed to separate with the first oxide semiconductor layer 110.
6th district's (not shown) of the first oxide semiconductor layer 210 and the 3rd grid 248 overlapping with the raceway groove served as with reference to TFT Tr, the 3rd source electrode 272 and the 3rd drain electrode 274 contact the 4th district's (not shown) in the 6th (not shown) both sides, district and the SECTOR-SEVEN (not shown) of the first oxide semiconductor layer 210 respectively.The other end that one end of 3rd source electrode 272 contacts the first oxide semiconductor layer the 210, three source electrode 272 by the 5th semiconductor interface contact hole 256 contacts reference line RL by reference to contact hole 257.In this case, oxide semiconductor material in 4th district's (not shown) of the first oxide semiconductor layer 210 and SECTOR-SEVEN (not shown) is reduced, and makes the 4th district and SECTOR-SEVEN (not shown) have conduction property.
Switching TFT Ts is electrically connected to select lines GL and data wire DL and is arranged on the cross section of select lines GL and data wire DL.That is, the second grid 244 of switching TFT Ts is connected to select lines GL, and second source electrode 266 of switching TFT Ts is connected to data wire DL.
The first grid 242 of drive TFT Td is electrically connected to second drain electrode 268 of switching TFT Ts.That is, the extension 270 extended from second drain electrode 268 of switching TFT Ts is contacted by grid contact hole 255 with the first grid 242 of drive TFT Td, makes the first grid 242 of drive TFT Td be electrically connected to second drain electrode 268 of switching TFT Ts.In more detail, the extension 270 of second drain electrode 268 of switching TFT Ts contacts the first extension 246 of the first grid 242 of drive TFT Td.In addition, first source electrode 262 of drive TFT Td is connected to power line VDD, and first drain electrode 264 of drive TFT Td is connected to the 3rd drain electrode 274 with reference to TFT Tr.
In fig .9, drive TFT Td and reference TFT Tr common drain.Alternatively, drive TFT Td the first drain electrode 264 and with reference to the 3rd drain electrode 274 of TFT Tr can be formed be separately and can be electrically connected.
The 3rd grid 248 with reference to TFT Tr is connected to select lines GL, and the 3rd source electrode 272 with reference to TFT Tr is connected to reference line RL.
Light-emitting diode E is connected to first drain electrode 264 of drive TFT Td and comprises anode, organic luminous layer and negative electrode.Such as, anode is connected to first drain electrode 264 of drive TFT Td.In OLED display, the light from organic luminous layer passes anode and substrate 201 or passes negative electrode.That is, OLED display is bottom emissive type or top emission structure.
Organic Light Emitting Diode E is formed above can being formed in above the substrate 201 of drive TFT Td, or can be formed on the opposing substrate (not shown) of substrate 201.
Holding capacitor Cst comprises the first holding capacitor Cst1.A part for first oxide semiconductor layer 210 and the first extension 246 of first grid 242 overlapping, to form the first holding capacitor Cst1.
First holding capacitor Cst1 comprises the second storage electrode (not shown) of the first storage electrode (not shown) of the marginal portion of the first extension 246 as first grid 242 and the marginal portion as second district's (not shown) of the first oxide semiconductor layer 210.During the step of the first extension 246 forming first grid 242 or after this, the first oxide semiconductor layer 210 is reduced because of plasma treatment.In this case, because stop mask is served as in the first extension 246 of first grid 242, marginal portion in second district's (not shown) of therefore the first oxide semiconductor layer except the core of second district's (not shown) is reduced into conduction.That is, because the core of second district's (not shown) is stopped by the first extension 246 of first grid 242 and the first insulating barrier 230, therefore the core of second district's (not shown) is not reduced and keeps non-conductive character.
Second storage electrode (not shown) is about 1.5 microns from the width that the edge termination of the first extension 246 of first grid 242 is started at.
Therefore, the first holding capacitor Cst1 is formed as the first storage electrode (not shown) of the marginal portion of the first extension 246 of first grid 242 and the overlapping second storage electrode (not shown) of marginal portion of second district's (not shown) as the first oxide semiconductor layer 210 of the first storage electrode (not shown) and the first insulating barrier 230 between the first storage electrode (not shown) and the second storage electrode (not shown).
In addition, holding capacitor Cst also comprises the second holding capacitor Cst2.Second holding capacitor Cst2 comprise the 5th district's (not shown) of the conduction as the first oxide semiconductor layer 210 the 3rd storage electrode, as the second drain electrode the 4th storage electrode of extension 270 of 268 and the second insulating barrier 250 as the dielectric layer between the 3rd storage electrode and the 4th storage electrode.
In addition, holding capacitor Cst also comprises the 3rd holding capacitor Cst.3rd holding capacitor Cst comprises a part for the first semiconductor layer 210 and the second extension 247 of first grid 242.
Namely, 3rd holding capacitor Cst comprises the 6th storage electrode 284 of the 5th storage electrode 282 of the marginal portion of the second extension 247 as first grid 242 and the marginal portion as overlapping the first oxide semiconductor layer 210 in the second extension 247 (that is, the 5th storage electrode 282) with first grid 242.During the step of the second extension 247 forming first grid 242 or after this, the first oxide semiconductor layer 210 is reduced because of plasma treatment.In this case, because stop mask is served as in the second extension 247 of first grid 242, the marginal portion of the first oxide semiconductor layer 210 therefore except the core of the first oxide semiconductor layer 210 is reduced into conduction.That is, because the core of the first oxide semiconductor layer 210 is stopped by the second extension 247 of first grid 242 and the first insulating barrier 230, therefore the core of the first oxide semiconductor layer 210 is not reduced and keeps non-conductive character.
6th storage electrode 284 is about 1.5 microns from the width that the edge termination of the second extension 247 of first grid 242 is started at.
Therefore, the 3rd holding capacitor Cst3 is formed as the 5th storage electrode 282 of the marginal portion of the second extension 247 of first grid 242 and overlapping the 6th storage electrode 284 of the marginal portion as the first oxide semiconductor layer 210 of the 5th storage electrode 282 and the first insulating barrier 230 between the 5th storage electrode 282 and the 6th storage electrode 284.
In OLED display second embodiment of the invention, because the first holding capacitor Cst1, the second holding capacitor Cst2 and the 3rd holding capacitor Cst3 use a part for the first oxide semiconductor layer 210 as the second storage electrode, the 3rd storage electrode and the 6th storage electrode respectively, therefore storage capacitance increases or is maximized, and aperture is than not reducing.
In this case, because the marginal portion of each the first extension 246 along first grid 242 in the first holding capacitor Cst1 and the 3rd holding capacitor Cst3 and the second extension 247 is formed, therefore the first holding capacitor Cst1 is relative little with the area of the 3rd holding capacitor Cst3.But owing to having relative little thickness as the first holding capacitor Cst1 with the first insulating barrier 230 of the dielectric layer of the 3rd holding capacitor Cst3, therefore the first holding capacitor Cst1 and the 3rd holding capacitor Cst3 has enough storage capacitances.
Each the first insulating barrier 230 comprised as dielectric layer in first holding capacitor Cst1 and the 3rd holding capacitor Cst3.First insulating barrier 230 is formed by inorganic insulating material and has relatively little thickness.Therefore, although the first holding capacitor Cst1 is relative little with the area of the 3rd holding capacitor Cst3, the first holding capacitor Cst1 and the 3rd holding capacitor Cst3 has enough storage capacitances.
As mentioned above, in OLED display of the present invention, use storage electrode as stopping that oxide semiconductor layer to be reduced into conduction by mask, the part be reduced of oxide semiconductor layer is used as storage electrode.That is, other storage electrode is not needed.Therefore, storage capacitance increases, and aperture is than not reducing.
In addition, because the first holding capacitor and the 3rd holding capacitor comprise relative the first little insulating barrier of thickness as dielectric layer, therefore holding capacitor has enough storage capacitances when electrode area is relatively little.Therefore, the reduction of the aperture ratio of OLED display is minimized or is prevented from.
It will be apparent to those skilled in the art, without departing from the spirit or scope of the present invention, various amendment and distortion can be carried out in the present invention.Therefore, the present invention is intended to contain modification of the present invention and variant, as long as they are in the scope of appended claims and equivalent thereof.
Claims (10)
1. an organic LED display device, this organic LED display device comprises:
First oxide semiconductor layer, it comprises the firstth district to the 4th district;
First insulating barrier, it is on described first oxide semiconductor layer;
First grid, it is with described firstth district completely overlapping on described first insulating barrier;
First storage electrode, it to extend and overlapping with described secondth district from described first grid;
Second insulating barrier, it covers described first grid and described first storage electrode, and is exposed in described 3rd district and the 4th district;
First source electrode and the first drain electrode, it is on described second insulating barrier and contact described 3rd district and described 4th district;
Light-emitting diode, it is connected to described first drain electrode,
Wherein, the part in described secondth district of the edge of described first storage electrode except the center except described first storage electrode is conduction, to form the second storage electrode, and described first storage electrode and described second storage electrode and described first insulating barrier form the first holding capacitor.
2. organic LED display device according to claim 1, wherein, described secondth district has the first length relative to first direction, described first direction intersects with the second direction be connected along described first oxide semiconductor layer that described first source electrode and described first drained, overlapping region between described first storage electrode and described secondth district has the second length relative to described first direction, wherein, described second length is less than described first length.
3. organic LED display device according to claim 1, wherein, described first insulating barrier has the first thickness, and described second insulating barrier has the second thickness being greater than described first thickness.
4. organic LED display device according to claim 1, described organic LED display device also comprises:
Second oxide semiconductor layer, it is below described first insulating barrier;
Second grid, it is with described second oxide semiconductor layer overlapping on described first insulating barrier;
Second source electrode and the second drain electrode, it is on described second insulating barrier and contact the first side and second side of described second oxide semiconductor layer respectively; And
Extension, it extends from described second drain electrode, so that described second drain electrode is connected with described first grid,
Wherein, the 5th district of described extension and described first oxide semiconductor layer is overlapping, and described 5th district is conduction, and wherein, described extension, described 5th district and described second insulating barrier form the second holding capacitor.
5. organic LED display device according to claim 4, described organic LED display device also comprises:
Select lines, it extends along third direction;
Data wire, it extends along fourth direction, to intersect with described select lines; And
Power line, it is parallel to an extension in described select lines and described data wire,
Wherein, described second grid is connected to described select lines, and described second source electrode is connected to described data wire, and wherein, described first source electrode is connected to described power line.
6. organic LED display device according to claim 5, wherein, described first oxide semiconductor layer, described first grid, described first source electrode and described first drain electrode form driving thin-film transistor, and described second oxide semiconductor layer, described second grid, described second source electrode and described second drain electrode form switching thin-film transistor, and
Described organic LED display device also comprises:
Reference line, it is parallel to another extension in described select lines and described data wire;
Reference thin film transistor, it is connected to described select lines, described first drain electrode and described reference line, to control the threshold voltage of described driving thin-film transistor.
7. organic LED display device according to claim 4, described organic LED display device also comprises the 3rd storage electrode, described 3rd storage electrode to extend and overlapping with the 6th district of described first oxide semiconductor layer from described first grid
Wherein, the part in described 6th district of the edge of described 3rd storage electrode except the center except described 3rd storage electrode is conduction, to form the 4th storage electrode, and described 3rd storage electrode and described 4th storage electrode and described first insulating barrier form the 3rd holding capacitor.
8. manufacture a method for organic LED display device, the method comprises the following steps:
Substrate forms oxide semiconductor layer;
Firstth district of described oxide semiconductor layer is formed the first insulating pattern and grid and form the second insulating pattern and the first storage electrode in the secondth district of described oxide semiconductor layer;
By performing plasma treatment, reduce the part in described secondth district inside the edge of described first storage electrode;
Form insulating barrier, the 3rd district of the both sides in described firstth district of described oxide semiconductor layer and the 4th district expose by described insulating barrier, and cover described grid and described first storage electrode;
Described insulating barrier is formed source electrode and the drain electrode in described 3rd district of contact and described 4th district; And
Formed and the described light-emitting diode be connected that drains.
9. method according to claim 8, wherein, be reduced in the step of the described part in described secondth district of a part inside the described edge by performing described first storage electrode of plasma treatment reduction in described secondth district of the edge of described first storage electrode except the center except described first storage electrode, the part be reduced is made to form the second storage electrode, and
Wherein, described first storage electrode and described second storage electrode and described first insulating barrier form the first holding capacitor.
10. method according to claim 8, wherein, described firstth district of described oxide semiconductor layer is formed described first insulating pattern and described grid and the step forming described second insulating pattern and described first storage electrode in described secondth district of described oxide semiconductor layer comprises:
Described oxide semiconductor layer sequentially forms dielectric film and metal film;
Described metal level forms the first photoetching agent pattern and the second photoetching agent pattern corresponding to described firstth district and described secondth district; And
Described first photoetching agent pattern and described second photoetching agent pattern is used to etch described metal film and described dielectric film to form described first insulating pattern, described second insulating pattern, described grid and described first storage electrode,
Wherein, described plasma treatment uses at least one in described second photoetching agent pattern and described first storage electrode as stop mask, and uses SF
6gas or CF
4gas.
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| WO2021114660A1 (en) * | 2019-12-13 | 2021-06-17 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
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| CN104681585B (en) | 2017-10-20 |
| KR102407538B1 (en) | 2022-06-13 |
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