CN104637525B - A kind of delay counter - Google Patents
A kind of delay counter Download PDFInfo
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- CN104637525B CN104637525B CN201510051140.6A CN201510051140A CN104637525B CN 104637525 B CN104637525 B CN 104637525B CN 201510051140 A CN201510051140 A CN 201510051140A CN 104637525 B CN104637525 B CN 104637525B
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Abstract
The present invention relates to a kind of delay counters, including input counter, output counter, FIFO and synchronous circuit, internal clock signal clk_rcv inputs input counter simultaneously and output counter, the input counter count internal clock signal clk_rcv, output input pointer；Output counter counts internal clock signal clk_rcv, exports output pointer.The present invention solves existing delay counter and DLL delay circuits is needed to work always, the technical problem for causing DRAM power consumptions high, and the present invention provides a kind of delay counter, for reducing power consumptions of the DRAM in no read command.
Description
Technical field
The present invention relates to semiconductor DRAM memory design fields, and in particular to a kind of delay counter and method of counting.
Background technology
Computer and various electronic equipments are widely used in the various aspects of the modern life, to memory article (DRAM
Memory) demand is increasing.People are getting faster rate request, and the power consumption of memory is with regard to increasing.Based on FIFO framves
Delay counter two asynchronous clocks of needs of structure design generate the input pointer and output pointer of counter FIFO respectively.
In Fig. 1：
External timing signal clk postpones (RCV delay circuits) by δ 0 and generates internal clock signal clk_rcv；
Internal clock signal clk_rcv generates delay clock signals clk_dll by δ dll delays (DLL delay circuits)；
Delay clock signals clk_dll is than external timing signal clk advanced phases δ 1 (output delay):δ 0+ δ dll+ δ 1=N*Tck (when
The clock period)；
Simulation clock signal clk_fb is delay clock signals clk_dll simulation RCV delays (δ 0) and output delay (δ 1)
The internal clocking of generation：δ fb=δ 0+ δ 1.So simulation clock signal clk_fb and internal clock signal clk_rcv phases are complete
It is identical；
It simulates clock signal clk_fb and generates input pointer (input point) sampling internal reading instruction；
The reading that delay clock signals clk_dll generates output pointer (output point) output clk_dll clock domains refers to
It enables；
The premise of the above-mentioned delay counter work based on FIFO frameworks is that input pointer and output pointer is needed to hold always
Continuous, this just needs simulation clock signal clk_fb and delay clock signals clk_dll to be continued for, when in order to ensure above-mentioned two
Clock then needs DLL delay circuits to work always.Even if DRAM memory no read command for a long time occurs being also required to DLL delays
Circuit continue working thus greatly wastes the power consumption of DRAM.
Invention content
DLL delay circuits are needed to work always in order to solve existing delay counter, the technology for causing DRAM power consumptions high
Problem, the present invention provides a kind of delay counter, for reducing power consumptions of the DRAM in no read command.
Technical solution of the invention：
A kind of delay counter, including input counter, output counter, FIFO and synchronous circuit, special character
It is：Internal clock signal clk_rcv inputs input counter and output counter simultaneously, the input counter to it is internal when
Clock signal clk_rcv is counted, output input pointer；
The output counter counts internal clock signal clk_rcv, exports output pointer.
Further include DLL delay circuits, the DLL delay circuits carry out delay disposal to internal clock signal clk_rcv and obtain
To signal clk_dll, and it is sent to synchronous circuit.
Advantage for present invention：
The internal clock signal clk_rcv of the present invention inputs input counter and output counter simultaneously, inputs counter
Internal clock signal clk_rcv is counted, output input pointer；Output counter to internal clock signal clk_rcv into
Row counts, and output pointer is exported, for reducing power consumptions of the DRAM in no read command.
Description of the drawings
Fig. 1 is the basic schematic diagram of delay counter based on FIFO frameworks；
Fig. 2 is delay counter operating diagram of the present invention；
Fig. 3 is the schematic diagram of embodiment 1；
Fig. 4 is the schematic diagram of embodiment 2；
Fig. 5 is the schematic diagram of embodiment 3；
Fig. 6 is the structural schematic diagram of delay counter of the present invention.
Specific implementation mode
As shown in Fig. 2, internal clock signal clk_rcv inputs input counter and output counter, the input simultaneously
Counter counts internal clock signal clk_rcv, output input pointer；
Output counter counts internal clock signal clk_rcv, exports output pointer.
Inputting pointer and output pointer is generated by internal clock signal clk_rcv, counts relationship and Fig. 1 is kept not
Become.
There is no need to the participations of clk_dll and clk_fb in this way in delay counter, can be closed in non-reading instruction
DLL delay circuits are to greatly reduce the power consumption of DRAM.
But equally if there is the output of reading instruction then delay counter is just in clk_rcv clock domains.Then in reading instruction,
Internal clock signal clk_dll is needed to synchronize the output of delay counter, above-mentioned two clock is different clock-domains, is led to
It crosses adjustment and generates the clock edge of output pointer to meet the settling time and retention time of synchronous needs.
After the locking of DLL delay circuits, (postpone to be less than 0.5* using a delayed clock of clk_dll and clk_dll
Tck clk_rcv) is sampled.Due to δ dll<Tck, so will appear following 3 kinds of situations.
Situation 1：
It is arbitrary value, such as Fig. 3 that clk_dll_delay, which is sampled as 0, clk_dll sampled results,：
In this case, 0.5*Tck<δdll+Tdelay<Tck
0.5*Tck-Tdelay<δdll<Tck-Tdelay
So when detecting situation 1, the output pointer of delay counter is by the rising edge generation of clk_rcv, output letter
Number by clk_dll synchronize settling time be：
0.5*Tck-Tdelay<Tsetup=δ dll<Tck-Tdelay.
Situation 2：
It is 1 that clk_dll_delay, which is sampled as 1, clk_dll sampled results, such as Fig. 4：
In this case, 0<δdll；δdll+Tdelay<0.5*Tck
0<δdll<0.5*Tck-Tdelay
So when detecting situation 2, the output pointer of delay counter is by the failing edge generation of clk_rcv, output letter
Number by clk_dll synchronize settling time be：
0.5*Tck<Tsetup=δ dll+0.5*Tck<Tck-Tdelay.
Situation 3：It is 1 that clk_dll_delay, which is sampled as 0, clk_dll sampled results, such as Fig. 5,
In this case, 0.5*Tck<δdll<Tck；δdll+Tdelay>Tck
Tck-Tdelay<δdll<Tck
So when detecting situation 3, the output pointer of delay counter is generated by the failing edge of clk_rcv, and will be inputted
Pointer add 1 or output pointer subtract 1, output signal by clk_dll synchronize settling time be：
0.5*Tck-Tdelay<Tsetup=δ dll-0.5*Tck<0.5*Tck.
Claims (1)
1. a kind of delay counter, including input counter, output counter, FIFO and synchronous circuit, it is characterised in that：It is interior
Portion clock signal clk_rcv inputs input counter and output counter simultaneously, and the input counter is to internal clock signal
Clk_rcv is counted, output input pointer；
The output counter counts internal clock signal clk_rcv, exports output pointer；
The input pointer and output pointer are generated by internal clock signal clk_rcv；
The delay counter further includes DLL delay circuits, and the DLL delay circuits carry out internal clock signal clk_rcv
Delay disposal obtains signal clk_dll, and is sent to synchronous circuit；
The internal clock signal clk_rcv and signal clk_dll synchronize the output of delay counter；When described internal
Clock signal clk_rcv and signal clk_dll is different clock-domains, by adjusting the clock of output pointer is generated along meeting synchronization
The settling time and retention time needed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510051140.6A CN104637525B (en) | 2015-01-30 | 2015-01-30 | A kind of delay counter |
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|---|---|---|---|
| CN201510051140.6A CN104637525B (en) | 2015-01-30 | 2015-01-30 | A kind of delay counter |
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| CN104637525A CN104637525A (en) | 2015-05-20 |
| CN104637525B true CN104637525B (en) | 2018-08-21 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807429A (en) * | 2009-02-13 | 2010-08-18 | 南亚科技股份有限公司 | Control circuit and method of dynamic random access memory line command address |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100375830B1 (en) * | 2001-03-22 | 2003-03-15 | 한국전자통신연구원 | Apparatus and Method for removing PCR jitter by inserting receiving time stamp |
| KR100625296B1 (en) * | 2004-12-30 | 2006-09-19 | 주식회사 하이닉스반도체 | Method and apparatus for latency control in high frequency synchronous semiconductor device |
| US7292080B2 (en) * | 2005-08-25 | 2007-11-06 | Infineon Technologies Ag | Delay locked loop using a FIFO circuit to synchronize between blender and coarse delay control signals |
| JP2010206603A (en) * | 2009-03-04 | 2010-09-16 | Yokogawa Electric Corp | Delay generator and ic tester |
| CN103700393B (en) * | 2012-09-28 | 2016-08-03 | 国际商业机器公司 | Intermediate circuit and method for DRAM |
| CN103198858B (en) * | 2013-03-19 | 2017-04-19 | 西安紫光国芯半导体有限公司 | Grading power saving circuit and method used for DRAM (Dynamic Random Access Memory) |
| CN204480670U (en) * | 2015-01-30 | 2015-07-15 | 西安华芯半导体有限公司 | A kind of delay counter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807429A (en) * | 2009-02-13 | 2010-08-18 | 南亚科技股份有限公司 | Control circuit and method of dynamic random access memory line command address |
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Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant before: Xi'an Sinochip Semiconductors Co., Ltd. |
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