CN104635215A - Jamming decision device based on SOPC (System-on-a-Programmable-Chip) - Google Patents
Jamming decision device based on SOPC (System-on-a-Programmable-Chip) Download PDFInfo
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- CN104635215A CN104635215A CN201310547953.5A CN201310547953A CN104635215A CN 104635215 A CN104635215 A CN 104635215A CN 201310547953 A CN201310547953 A CN 201310547953A CN 104635215 A CN104635215 A CN 104635215A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/38—Jamming means, e.g. producing false echoes
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- Radar, Positioning & Navigation (AREA)
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- Design And Manufacture Of Integrated Circuits (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention belongs to the technical field of electronic countermeasure and particularly relates to a jamming decision device based on SOPC (System-on-a-Programmable-Chip), so as to improve the intelligent degree of a jammer and improve the jamming decision device. An FPGA is used for building the SOPC (System-on-a-Programmable-Chip), jamming decision is carried out in real time, and the radar jamming function is realized. The following modules such as a soft-core processor, a program RAM, a data RAM, a jamming algorithm module, an IIC and a GPIO in the FPGA are realized. The testing result shows that the SOPC platform achieves expected functions, jamming decision parameters can be configured in real time, and the scheme is feasible. The jamming decision technology based on the SOPC is applied to the jammer, and the radar docking test result shows that intelligent jamming on the radar can be realized by the product.
Description
Technical field
The invention belongs to ECM (Electronic Countermeasures) field.
Background technology
This kind based on the interfering well cluster Technology origin of programmable system on chip (System-on-a-Programmable-Chip, SOPC) in the design of jammer.Jammer can realize compacting to radar, cheating interference, reduces its tracking to real goal, recognition capability.Adopt the mode that interfering well cluster parameter is pre-configured in traditional design, carry out parameter calculating according to loading data, generate interfering well cluster parameter list in advance, be configured by the parameter list generated when implementing interference.
In this kind of mode, because conflicting mode is fixed in advance, the requirement of real-time intelligent interference can not be met.Therefore, the jammer can implementing interference according to radar kind and external environment condition intelligence is needed.
Summary of the invention
The object of the invention is the intelligence degree for improving jammer, interfering well cluster device is improved.
The present invention is a kind of interfering well cluster device based on SOPC, for generation of the interfering well cluster of radar jammer, wherein, uses FPGA to construct programmable system on chip (SOPC), carries out interfering well cluster in real time, realize the interference function to radar.
As above based on the interfering well cluster device of SOPC, wherein, realize as lower module at described FPGA: soft-core processor, program RAM, data RAM, algorithm of interference module, IIC and GPIO; Obtained the data comprising radar signal real-time measurements by GPIO, be supplied to soft-core processor and carry out computing; Obtained the information of external sensor by IIC, be supplied to soft-core processor and carry out computing; Soft-core processor carries out disturbing with parameter calculating according to the information of radar signal real-time measurements and external sensor, generates Decision Control table, and exports interference parameter and Decision Control table for algorithm of interference module; The interference parameter that algorithm of interference module inputs according to soft-core processor and Decision Control table, control peripheral hardware, realize the interference function to radar.
As above based on the interfering well cluster device of SOPC, wherein, described module carries out interfering well cluster in the following manner:
A) in SOPC, GPIO module receives external load data, and obtain positional information and the velocity information of jammer and radar, the soft core of Microblaze calculates the distance of jammer and radar accordingly;
B) in SOPC, IIC module receives the temperature information of temperature sensor input, is mapped, tackle the gain compensation that power amplifier gives under determining this temperature by the soft core of Microblaze and power amplifier property list;
C) in SOPC, algorithm of interference module measures the radar signal power received in real time, and this performance number is together with distance parameter, and Shared Decision Making goes out the jamming power that now jammer should be launched;
D) in SOPC, algorithm of interference module measures the radar signal parameter received in real time, and the parameter that prestores in combined memory carries out interfering well cluster, implements interfering process.
The present invention adopts SOPC technology, realize real-time generation and the configuration of interfering well cluster parameter, use Xilinx company FPGA, construct programmable system on chip (SOPC), the collaborative design method taking hardware description language (HDL) to combine with C language, realizes the interfering well cluster function of jammer.This system is made up of MicroBlaze soft-core processor, algorithm of interference module, timer module, peripheral interface module, and processor and each module adopt external bus interface and external interrupt interface to carry out alternately.Processor, according to parameter result of calculation and signal measurement result, generates interfering well cluster parameter and configures in real time algorithm of interference module related register.
Test result shows, this SOPC platform reaches the function of anticipation, can realize the real-time configuration of interfering well cluster parameter, concept feasible.At present, this kind is applied based on the interfering well cluster technology of SOPC in jammer, and radar docking test findings shows, this product can realize disturbing the intellectuality of radar.
Accompanying drawing explanation
Fig. 1 is based on the design architecture of SOPC.
Fig. 2 software workflow figure.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described further.
For improving the intelligence degree of jammer, the present invention adopts SOPC technology, realizes real-time generation and the configuration of interfering well cluster parameter.
SOPC is programmable SOC (system on a chip).It is a kind of special embedded system, not only can be completed the main logic function of whole system by one single chip, and due to its programmable characteristic, make design more flexible, can cut out, expand, upgrade, and possess software and hardware system programmable functions.
The present invention selects the fpga chip of Xilinx company, uses embedded development external member (EDK, developing instrument), realizes SOPC design by the mode being embedded in soft processor core (MicroBlaze, the product provided by Xilinx company) at FPGA.This kind of design can build the general-purpose platform of interfering well cluster technology, and when needs are expanded, by adding users customized IP core, and the mode such as flexible construction Peripheral Interface carries out Function Extension.
1 based on the design architecture of SOPC
Based on SOPC design architecture as shown in Figure 1.SOPC is built by Xilinx company FPGA, and this system is made up of Microblaze soft processor core, interference module, timer module, peripheral interface module etc.Soft processor core and each module adopt external bus interface to carry out alternately.
The reception of 1553B data is mainly completed and verification, parameter calculate and the generation of Decision Control table in soft processor core.Algorithm of interference module carries out signal transacting according to the decision information inputted by Microblaze, and exports peripheral hardware to.Sensor passes through IIC(Inter-Integrated Circuit, IC bus) interface input external sensor data (such as, temperature information), adjust the Decision Control information under varying environment for Microblaze.By adding timer and interrupt service routine, control the information interaction of each module interface.
As the expansion of interface, system reserves GPIO(General Purpose Input Output, universal input exports) interface, for external communication, such as, by CPLD(Complex Programmable Logic Device, CPLD) carry out data transmission, such as can transmit 1553B data.Generally, each GPIO can comprise at most two passages, is articulated to PLB(Pipeline Burst Cache, burst of pulses formula buffer memory) in bus.PLB bus is realized by access register the read-write of GPIO.All data are all first write d type flip flop, are passing through the input of tri-state port controlling, output characteristics.By adding the relevant bottom document of GPIO, corresponding driving function can be called, complete the operations such as the initialization of GPIO, direction setting, digital independent and assignment.
2 software simulating
After hardware design completes, carry out bit stream and produce operation, can output in SDK by hardware design, automatically produce corresponding library file in hardware design, this is the basis of Software for Design.
After Software for Design completes, by hardware net table and bit stream file, the executable code of the ELF form generated with software translating merges, and forms final binary bits file, by the programming of JTAG Programme Line in program storage.Described modular construction can be realized.
Above-mentioned programming process is common practise.
Wherein, software workflow as shown in Figure 2.After software carries out initialization, carry out parameter calculating, go out conflicting mode this moment and emissive power with reference to external sensor data (such as, temperature information) and the real-time measurements Shared Decision Making of radar signal, and with the algorithm of specifying, signal is modulated.Such as, can switch between compacting jamming pattern and cheating interference pattern, and the condition switched is determined by the result of calculation of MicroBlaze.
A concrete computation process is as described below:
A) in SOPC, GPIO module receives external load data, and extract positional information and the velocity information of jammer and radar, the soft core of Microblaze calculates the distance of jammer and radar accordingly;
B) in SOPC, I2C module receives the temperature information of temperature sensor input, map through the soft core of Microblaze and power amplifier property list, the gain compensation that power amplifier gives is tackled, to guarantee that the transmission channel gain of jammer remains unchanged under can determining this temperature; Power amplifier property list stores power amplifier characteristic, i.e. transmission channel gain characteristic under different temperatures in mapping;
C) in SOPC, algorithm of interference module measures the radar signal power received in real time, and this performance number is together with distance parameter, and Shared Decision Making goes out the jamming power that now jammer should be launched;
D) in SOPC, algorithm of interference module measures the parameter such as frequency, pulse width, repetition cycle, bandwidth receiving radar signal in real time, carries out interfering well cluster, implement different interfering processes in conjunction with the parameter that prestores in ferroelectric memory.
Described interfering process can comprise common compacting jamming pattern, cheating interference pattern and various antagonism patterns etc.The parameter that prestores can be specified jamming pattern.Further, if interfering well cluster Data import is unsuccessful, namely soft-core processor calculates unsuccessful in real time, can not obtain useful interfering well cluster, then can enter autonomous jamming pattern, is disturbed by the mode preset.
After reaching certain hour, software sends interference termination signal, and program is run complete.
Should illustrate, said process is the one in order to illustrate in the interfering well cluster process that the present invention can carry out, and is not to limit, and on basis of the present invention, can carry out various decision process.
The present invention, while simplification hardware circuit design, meets the designing requirement of system low-power consumption, high reliability, meets embedded technology trend.
Above embodiments of the invention are explained in detail, above-mentioned embodiment is only optimum embodiment of the present invention, but the present invention is not limited to above-described embodiment, in the ken that those of ordinary skill in the art possess, various change can also be made under the prerequisite not departing from present inventive concept.
Claims (3)
1. based on an interfering well cluster device of SOPC, for generation of the interfering well cluster of radar jammer, it is characterized in that, use FPGA to construct programmable system on chip (SOPC), carry out interfering well cluster in real time, realize the interference function to radar.
2. as claimed in claim 1 based on the interfering well cluster device of SOPC, it is characterized in that, realize as lower module at described FPGA: soft-core processor, program RAM, data RAM, algorithm of interference module, IIC and GPIO; Obtained the data comprising radar signal real-time measurements by GPIO, be supplied to soft-core processor and carry out computing; Obtained the information of external sensor by IIC, be supplied to soft-core processor and carry out computing; Soft-core processor carries out disturbing with parameter calculating according to the information of radar signal real-time measurements and external sensor, generates Decision Control table, and exports interference parameter and Decision Control table for algorithm of interference module; The interference parameter that algorithm of interference module inputs according to soft-core processor and Decision Control table, control peripheral hardware, realize the interference function to radar.
3., as claimed in claim 2 based on the interfering well cluster device of SOPC, it is characterized in that, described module carries out interfering well cluster in the following manner:
A) in SOPC, GPIO module receives external load data, and obtain positional information and the velocity information of jammer and radar, the soft core of Microblaze calculates the distance of jammer and radar accordingly;
B) in SOPC, IIC module receives the temperature information of temperature sensor input, is mapped, tackle the gain compensation that power amplifier gives under determining this temperature by the soft core of Microblaze and power amplifier property list;
C) in SOPC, algorithm of interference module measures the radar signal power received in real time, and this performance number is together with distance parameter, and Shared Decision Making goes out the jamming power that now jammer should be launched;
D) in SOPC, algorithm of interference module measures the radar signal parameter received in real time, and the parameter that prestores in combined memory carries out interfering well cluster, implements interfering process.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444831A (en) * | 2018-09-06 | 2019-03-08 | 中国人民解放军战略支援部队航天工程大学 | A kind of radar chaff decision-making technique based on transfer learning |
| CN109444832A (en) * | 2018-10-25 | 2019-03-08 | 哈尔滨工程大学 | Colony intelligence interfering well cluster method based on more jamming effectiveness values |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1050094A (en) * | 1990-08-10 | 1991-03-20 | 中国人民解放军电子工程学院 | Covering jamming effect measuring instrument for radar |
| CN102170302A (en) * | 2011-03-23 | 2011-08-31 | 西安电子科技大学 | Anti-interference system-on-chip and method of intelligent antenna based on FPGA (Field Programmable Gate Array) |
| CN102955151A (en) * | 2012-10-09 | 2013-03-06 | 中国人民解放军63892部队 | Adaptive cross-polarization active jamming method and device |
-
2013
- 2013-11-07 CN CN201310547953.5A patent/CN104635215B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1050094A (en) * | 1990-08-10 | 1991-03-20 | 中国人民解放军电子工程学院 | Covering jamming effect measuring instrument for radar |
| CN102170302A (en) * | 2011-03-23 | 2011-08-31 | 西安电子科技大学 | Anti-interference system-on-chip and method of intelligent antenna based on FPGA (Field Programmable Gate Array) |
| CN102955151A (en) * | 2012-10-09 | 2013-03-06 | 中国人民解放军63892部队 | Adaptive cross-polarization active jamming method and device |
Non-Patent Citations (4)
| Title |
|---|
| 江海清等: "基于FPGA的雷达欺骗干扰信号调制器的设计", 《现代雷达》 * |
| 王正林等: "抗相参雷达的侦察干扰一体化处理技术", 《航天电子对抗》 * |
| 薛慧敏: "基于SoPC的分布式干扰系统嵌入式网关设计", 《现代电子技术》 * |
| 谈江海: "雷达干扰系统仿真研究", 《中国优秀博硕学位论文全文数据库(硕士)信息科技辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444831A (en) * | 2018-09-06 | 2019-03-08 | 中国人民解放军战略支援部队航天工程大学 | A kind of radar chaff decision-making technique based on transfer learning |
| CN109444831B (en) * | 2018-09-06 | 2023-03-10 | 中国人民解放军战略支援部队航天工程大学 | Radar interference decision method based on transfer learning |
| CN109444832A (en) * | 2018-10-25 | 2019-03-08 | 哈尔滨工程大学 | Colony intelligence interfering well cluster method based on more jamming effectiveness values |
| CN109444832B (en) * | 2018-10-25 | 2023-02-14 | 哈尔滨工程大学 | Group intelligent interference decision method based on multiple interference effect values |
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