CN104617100A - Sonos memory structure and manufacturing method thereof - Google Patents
Sonos memory structure and manufacturing method thereof Download PDFInfo
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- CN104617100A CN104617100A CN201510050958.6A CN201510050958A CN104617100A CN 104617100 A CN104617100 A CN 104617100A CN 201510050958 A CN201510050958 A CN 201510050958A CN 104617100 A CN104617100 A CN 104617100A
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Abstract
The invention discloses a SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory structure and a method for manufacturing the memory structure. The memory structure is characterized in that an acquisition charge layer in an existing technology is replaced with a barrier enhancement layer, and the barrier enhancement layer comprises multiple oxygen-enriched silicon nitride layers and silicon-enriched silicon nitride layers all which are staggered, so that multi-level energy levels are introduces, barriers are increased, electric charges are limited in random hopping, and the disadvantage of easily losing data is improved, and the reliability of the SONOS memory structure is increased.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of SONOS memory construction and preparation method thereof.
Background technology
Usually, the semiconductor memory for storing data is divided into volatile memory and nonvolatile memory, loses its data when volatile memory is easily disconnected in the supply, even and if nonvolatile memory is disconnected in the supply time still can preserve its data.As compared to other nonvolatile storage technologies (such as, disc driver), nonvolatile semiconductor memory is relatively little.Therefore, nonvolatile memory is widely used in mobile communication system, storage card etc.
Nonvolatile memory (Non-Volatile Memory) can be realized by one of floating gate structure or the large major technique of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon is called for short SONOS) structure two.The tunnel oxide that floating gate type memory is relatively thick provides good charge holding performance, and technological process ratio is easier to control, but once existing defects in tunnel oxide, stored charge is easily lost from polysilicon accumulation layer along defect.The thinner thickness of the tunnel oxide of SONOS memory, utilize the silicon nitride medium layer of insulation to capture and stored charge, the trap that silicon nitride is used for catching electric charge is independently, can not cause a large amount of loss of electric charge because of a defect.SONOS also has that anti-erasable ability is good, operating voltage is low and power is low, technical process is simple and with the advantage such as standard CMOS process is compatible.
Fig. 1 is the schematic diagram of the SONOS structure of prior art, please refer to Fig. 1, the SONOS structure of prior art comprises substrate 10, be positioned at the tunneling medium layer 11 on described substrate 10, catch charge layer 12, top dielectric layer 13 and control gate 14, wherein, the material of tunneling medium layer 11 is silica, the material of catching charge layer 12 is silicon nitride, the material of top dielectric layer 13 is silica, tunneling medium layer 11, catches the laminated construction that charge layer 12 and top dielectric layer 13 constitute ONO (oxide-nitride-oxide).
Nonvolatile memory (Non-Volatile Memory) mainly emphasizes data retention (DataRetention, DRB).But the memory data retention at high temperature of existing SONOS structure is also unstable, and main manifestations is that data are easily lost.The electric charge of existing SONOS structure mainly concentrates near control gate.
Summary of the invention
The object of the present invention is to provide a kind of SONOS memory construction and preparation method thereof can improve data and easily lose this defect, improve the performance of SONOS.
To achieve these goals, the present invention proposes a kind of SONOS memory construction, comprising: substrate, form tunneling medium layer, Barrier-enhancement Layer, electric charge barrier layer and control gate over the substrate successively; Wherein, described Barrier-enhancement Layer comprises oxygen rich silicon nitride layer and the silicon-rich silicon nitride layer of multi-layer intercrossed arrangement.
Further, in described SONOS memory construction, the oxygen atom content in described oxygen rich silicon nitride layer is 20% ~ 70% than scope.
Further, in described SONOS memory construction, the thickness range of described oxygen rich silicon nitride layer is between 40 dusts to 70 dusts.
Further, in described SONOS memory construction, the silicon atom content in described silicon-rich silicon nitride layer is 40% ~ 70% than scope.
Further, in described SONOS memory construction, the thickness range of described silicon-rich silicon nitride layer is between 40 dusts to 70 dusts.
Further, in described SONOS memory construction, described tunneling medium layer is oxide layer, and thickness range is between 10 dusts to 30 dusts.
Further, in described SONOS memory construction, described tunneling medium layer adopts thermal oxidation method to be formed.
Further, in described SONOS memory construction, described electric charge barrier layer is silica, and thickness range is between 30 dusts to 70 dusts.
Further, in described SONOS memory construction, the thickness of described control gate is between 800 dusts to 1200 dusts.
The invention allows for a kind of manufacture method of SONOS memory construction, for the formation of SONOS memory construction as described above, comprise step:
Substrate is provided;
Form tunneling medium layer over the substrate;
Described tunneling medium layer forms Barrier-enhancement Layer, and described Barrier-enhancement Layer comprises oxygen rich silicon nitride layer and the silicon-rich silicon nitride layer of multi-layer intercrossed arrangement;
Described Barrier-enhancement Layer forms electric charge barrier layer and control gate successively.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: in the present invention, use Barrier-enhancement Layer substituted for and of the prior artly catch charge layer, Barrier-enhancement Layer comprises oxygen rich silicon nitride layer and the silicon-rich silicon nitride layer of multi-layer intercrossed arrangement, thus introduce multistage energy level, increase obstacle potential barrier, restriction electric charge stochastic transition, improve data and easily lose this defect, improve the reliability of SONOS memory construction.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of SONOS structure in prior art;
Fig. 2 is the flow chart of the manufacture method of SONOS memory construction in the embodiment of the present invention;
Fig. 3 to Fig. 8 is the structural profile schematic diagram in the embodiment of the present invention in SONOS memory construction preparation process.
Embodiment
Below in conjunction with schematic diagram, SONOS memory construction of the present invention and preparation method thereof is described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, in the present embodiment, propose a kind of manufacture method of SONOS memory construction, for the formation of SONOS memory construction, described method comprises step:
S100: substrate is provided;
S200: form tunneling medium layer over the substrate;
S300: form Barrier-enhancement Layer in described tunneling medium layer, described Barrier-enhancement Layer comprises oxygen rich silicon nitride layer and the silicon-rich silicon nitride layer of multi-layer intercrossed arrangement;
S400: form electric charge barrier layer and control gate successively on described Barrier-enhancement Layer.
Concrete, please refer to Fig. 3, in the step s 100, substrate 100 can be the substrates such as monocrystalline silicon, polysilicon or silicon-on-insulator; Please refer to Fig. 4, in step s 200, described tunneling medium layer 110 is silica, and it adopts thermal oxidation method to be formed, and the thickness range of formation is between 10 dusts to 30 dusts, for the electron tunneling of programming and in erase process; It is pointed out that substrate 100 is at the necessary clean free from admixture of the front surface of the described tunneling medium layer 110 of growth, so just can guarantee that the silica formed is functional.
Please refer to Fig. 5, in step S300, the oxygen atom content in described oxygen rich silicon nitride layer 121 is 20% ~ 70% than scope, such as, be 50%, and its thickness range between 40 dusts to 70 dusts, such as, is 50 dusts; Please refer to Fig. 6, the silicon atom content in described silicon-rich silicon nitride layer 122 is 40% ~ 70% than scope, such as, be 60%, and the thickness range of described silicon-rich silicon nitride layer 122 between 40 dusts to 70 dusts, such as, is 60 dusts; Described oxygen rich silicon nitride layer 121 and silicon-rich silicon nitride layer 122 constitute Barrier-enhancement Layer, Barrier-enhancement Layer can be 2 layers, i.e. 1 layer of oxygen rich silicon nitride layer 121 and 1 layer of silicon-rich silicon nitride layer 122, Barrier-enhancement Layer also can for after multilayer i.e. 1 layer of oxygen rich silicon nitride layer 121 and 1 layer of silicon-rich silicon nitride layer 122, then 1 layer of oxygen rich silicon nitride layer 121 and 1 layer of silicon-rich silicon nitride layer 122 is formed again, circulate successively stacking, the concrete number of plies can need to decide according to difference, in this no limit.
It is to be noted, atomic composition in Barrier-enhancement Layer must strictly control, the i.e. content of oxygen in oxygen rich silicon nitride, the content of silicon in silicon-rich silicon nitride, can guarantee like this can introduce new energy level in Barrier-enhancement Layer, avoid the random transition of electronics, improve the performance of the SONOS memory construction formed.In addition, strictly must control the technique stand-by period between hot oxygen silica (i.e. tunneling medium layer 110) to Barrier-enhancement Layer technique, within being generally 1 hour, if the stand-by period is oversize, easily cause tunneling medium layer 110 to lose efficacy.
Please refer to Fig. 7 and Fig. 8, electric charge barrier layer 130 (for silica is also referred to as barrier oxidation silicon, Blocking Oxide) described in step S400, its thickness range between 30 dusts to 70 dusts, such as, is 40 dusts; The thickness of described control gate 140 between 800 dusts to 1200 dusts, such as, is 1000 dusts; In this process, strictly must control the technique stand-by period between Barrier-enhancement Layer to electric charge barrier layer 130 technique, usually also for being less than 1 hour for good, need the quality controlling electric charge barrier layer 130 in addition, otherwise also can cause the inefficacy of data retention.
To sum up, in SONOS memory construction that the embodiment of the present invention provides and preparation method thereof, in the present invention, use Barrier-enhancement Layer substituted for and of the prior artly catch charge layer, Barrier-enhancement Layer comprises oxygen rich silicon nitride layer and the silicon-rich silicon nitride layer of multi-layer intercrossed arrangement, thus introduces multistage energy level, increase obstacle potential barrier, restriction electric charge stochastic transition, improves data and easily loses this defect, improve the reliability of SONOS memory construction.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (10)
1. a SONOS memory construction, is characterized in that, comprising: substrate, form tunneling medium layer, Barrier-enhancement Layer, electric charge barrier layer and control gate over the substrate successively; Wherein, described Barrier-enhancement Layer comprises oxygen rich silicon nitride layer and the silicon-rich silicon nitride layer of multi-layer intercrossed arrangement.
2. SONOS memory construction as claimed in claim 1, it is characterized in that, the oxygen atom content in described oxygen rich silicon nitride layer is 20% ~ 70% than scope.
3. SONOS memory construction as claimed in claim 2, it is characterized in that, the thickness range of described oxygen rich silicon nitride layer is between 40 dusts to 70 dusts.
4. SONOS memory construction as claimed in claim 1, it is characterized in that, the silicon atom content in described silicon-rich silicon nitride layer is 40% ~ 70% than scope.
5. SONOS memory construction as claimed in claim 4, it is characterized in that, the thickness range of described silicon-rich silicon nitride layer is between 40 dusts to 70 dusts.
6. SONOS memory construction as claimed in claim 1, it is characterized in that, described tunneling medium layer is oxide layer, and thickness range is between 10 dusts to 30 dusts.
7. SONOS memory construction as claimed in claim 6, is characterized in that, described tunneling medium layer adopts thermal oxidation method to be formed.
8. SONOS memory construction as claimed in claim 1, it is characterized in that, described electric charge barrier layer is silica, and thickness range is between 30 dusts to 70 dusts.
9. SONOS memory construction as claimed in claim 1, it is characterized in that, the thickness of described control gate is between 800 dusts to 1200 dusts.
10. a manufacture method for SONOS memory construction, for the formation of SONOS memory construction as claimed in any one of claims 1-9 wherein, is characterized in that, comprise step:
Substrate is provided;
Form tunneling medium layer over the substrate;
Described tunneling medium layer forms Barrier-enhancement Layer, and described Barrier-enhancement Layer comprises oxygen rich silicon nitride layer and the silicon-rich silicon nitride layer of multi-layer intercrossed arrangement;
Described Barrier-enhancement Layer forms electric charge barrier layer and control gate successively.
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Citations (5)
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| CN1851932A (en) * | 2006-04-21 | 2006-10-25 | 北京大学深圳研究生院 | Non-volatile storage device structure |
| CN101170135A (en) * | 2006-10-23 | 2008-04-30 | 海力士半导体有限公司 | Non volatile memory device possessing charge trapping layer and its manufacture method |
| CN101494225A (en) * | 2009-02-23 | 2009-07-29 | 中国科学院微电子研究所 | Memory and method for producing the same |
| CN104254921A (en) * | 2012-03-27 | 2014-12-31 | 赛普拉斯半导体公司 | Sonos stack with split nitride memory layer |
| CN104321877A (en) * | 2012-03-29 | 2015-01-28 | 赛普拉斯半导体公司 | Method of ONO integration into logic CMOS flow |
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- 2015-01-30 CN CN201510050958.6A patent/CN104617100A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1851932A (en) * | 2006-04-21 | 2006-10-25 | 北京大学深圳研究生院 | Non-volatile storage device structure |
| CN101170135A (en) * | 2006-10-23 | 2008-04-30 | 海力士半导体有限公司 | Non volatile memory device possessing charge trapping layer and its manufacture method |
| CN101494225A (en) * | 2009-02-23 | 2009-07-29 | 中国科学院微电子研究所 | Memory and method for producing the same |
| CN104254921A (en) * | 2012-03-27 | 2014-12-31 | 赛普拉斯半导体公司 | Sonos stack with split nitride memory layer |
| CN104321877A (en) * | 2012-03-29 | 2015-01-28 | 赛普拉斯半导体公司 | Method of ONO integration into logic CMOS flow |
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Application publication date: 20150513 |