CN104617041B - A kind of pattern-producing method, array substrate and display device - Google Patents
A kind of pattern-producing method, array substrate and display device Download PDFInfo
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- CN104617041B CN104617041B CN201510062159.0A CN201510062159A CN104617041B CN 104617041 B CN104617041 B CN 104617041B CN 201510062159 A CN201510062159 A CN 201510062159A CN 104617041 B CN104617041 B CN 104617041B
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- 239000000758 substrate Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000013507 mapping Methods 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
The present invention provides a kind of pattern-producing method array substrate, display device, is related to display field.Wherein, method includes:The groove structure identical with the functional pattern is etched on the insulating layer, the thickness of the groove structure is less than the thickness of the insulating layer；The pattern layer to be etched for functional pattern is formed on the substrate of the groove structure is etched with；The pattern layer in non-recessed structure is etched, obtains the functional pattern formed by the pattern layer being retained on the groove structure.The solution of the present invention can effectively reduce the protrusion of the functional pattern formed on insulating layer, and the adjacent edges for making pixel region are more flat, so as to improve the friction process of PI films, avoid that light leakage phenomena occurs.
Description
Technical field
The present invention relates to display field, particularly a kind of pattern-producing method, array substrate and display device.
Background technology
Liquid crystal display device includes array substrate, color membrane substrates and the liquid being arranged between array substrate and color membrane substrates
It is brilliant.In order to enable array substrate and color membrane substrates the stabilizing liquid crystal direction in the case where being not added with voltage, need in array substrate
It is provided with PI (Polyimide, polyimides) film.
Fig. 1 is the schematic diagram (by taking top gate structure as an example) of friction PI films on the tft substrate, it can be seen from the figure that mesh
Source electrode 6, drain electrode 7, semiconductor layer pattern 8 above front insulation layer are the presence of protrusion, therefore the edge of pixel region 9
Nearby blind area Rubbing Shadow can be formed when roller 10 can be because segment difference h in the PI thin-film process that rubs there are segment difference h.
So, the PI films in blind area because not by friction to due to cause Liquid Crystal Molecules Alignment chaotic so that light can not it is anticipated that
Direction reflects, and the light leakage phenomena of pixel edges occurs.
Invention content
The technical problem to be solved in the present invention is to provide a kind of pattern-producing method array substrate, display device, Neng Gouyou
Effect reduces the protrusion that functional pattern is formed on the insulating layer.
In order to solve the above technical problems, the embodiment of the present invention offer technical solution is as follows：
On the one hand, an embodiment of the present invention provides a kind of pattern-producing method, in the substrate that top layer is insulating layer
Upper formation functional pattern, the pattern-producing method include：
The groove structure identical with the functional pattern is etched on the insulating layer, the thickness of the groove structure is small
In the thickness of the insulating layer；
The pattern layer to be etched for functional pattern is formed on the substrate of the groove structure is etched with；
The pattern layer in non-recessed structure is etched away, obtains being formed by the pattern layer being retained on the groove structure
The functional pattern.
Wherein, the functional pattern is semiconductor layer pattern；The pattern layer is semiconductor layer.
Alternatively, the functional pattern is source-drain electrode pattern；The pattern layer is source-drain electrode metal layer.
Again alternatively, the functional pattern is semiconductor layer pattern and source-drain electrode pattern；The pattern layer is semiconductor layer
With source-drain electrode metal layer.
Wherein, the groove structure identical with the functional pattern is etched on the insulating layer, including：
It is gradually performed etching on the insulating layer according to the semiconductor layer pattern and source-drain electrode pattern；Or institute
The pattern that meets formed according to the semiconductor layer pattern and source-drain electrode pattern on insulating layer is stated to perform etching.
On the other hand, the embodiment of the present invention additionally provides a kind of array substrate, and the insulating layer of the array substrate is with recessed
Slot structure, the functional pattern at least part being formed on the insulating layer are Chong Die with the groove structure.
In addition, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned array substrate.
The above-mentioned technical proposal of the present invention has the beneficial effect that：
In the solution of the present invention, the groove on insulating layer can offset the protrusion of its functional pattern above, therefore can make picture
The adjacent edges in plain region are more flat, and then improve PI thin-film friction techniques, avoid that light leakage phenomena occurs.
Description of the drawings
Fig. 1 is the schematic diagram of the friction PI films in the TFT substrate of the prior art；
Fig. 2 is the step schematic diagram of the pattern-producing method of the present invention；
Fig. 3 A- Fig. 3 E are the process schematic representation that the embodiment of the present invention one makes figure；
Fig. 4 is structure diagram of the pixel region on substrate in invention realization method one；
Fig. 5 A- Fig. 5 E are the process schematic representation that the embodiment of the present invention two makes figure；
Fig. 6 is structure diagram of the pixel region on substrate in invention realization method two；
Fig. 7 A- Fig. 7 E are the process schematic representation that the embodiment of the present invention three makes figure；
Fig. 8 is structure diagram of the pixel region on substrate in invention realization method three；
Fig. 9 is the contrast schematic diagram of the tft array substrate and the tft array substrate of the present invention of the prior art.
Specific embodiment
To make the technical problem to be solved in the present invention, technical solution and advantage clearer, below in conjunction with attached drawing and tool
Body embodiment is described in detail.
In tft array substrate made of traditional handicraft, the adjacent edges of pixel region are there are larger segment difference, therefore right
During pixel region friction matching film, blind area is had.To solve this problem, the present invention provides a kind of new pattern-producing method system
Make method, the flatness that can be effectively improved between TFT regions and pixel region, as shown in Fig. 2, the side of the present embodiment
Method includes：
Step 21, the groove structure identical with the functional pattern is etched on the insulating layer；The groove structure
Thickness be less than the insulating layer thickness；
Step 22, the pattern layer to be etched for functional pattern is formed on the substrate of the groove structure is etched with；
Step 23, the pattern layer in non-recessed structure is etched away, obtains the figure by being retained on the groove structure
The functional pattern that pattern layer is formed.
In the production method of the present embodiment, the groove structure on insulating layer can offset the protrusion of its functional pattern above,
Therefore the adjacent edges of pixel region can be made more flat, and then avoid friction PI thin-film process in there are blind areas.
It needs to be described, in the method for the present embodiment, as long as the pattern formed on the insulating layer all may be used
Protrusion is offset with (thickness for depending on groove structure) to a certain extent.Such as, it is desirable to the protrusion of source-drain electrode pattern is offset,
The groove structure of source-drain electrode pattern can be then etched on the insulating layer or wants to offset the protrusion for having semiconductor layer pattern,
Then can etching semiconductor layer pattern on the insulating layer groove structure, then want to offset simultaneously source semiconductor layer pattern and
The protrusion of drain electrode pattern then can on the insulating layer, etch the groove structure of semiconductor layer pattern and drain electrode pattern.Under
Face describes to said program in detail with reference to several realization methods.
<Realization method one>, offset the protrusion of semiconductor layer pattern：
In realization method one, the technical process of the pattern-producing method as shown in Fig. 3 A- Fig. 3 E, including：
Step 31, the groove structure 3 of semiconductor layer pattern is etched on the insulating layer 2 of substrate 1；Wherein, etch thicknesses
It is less than the thickness of insulating layer；
Step 32, semiconductor layer 4 is formed on the substrate for be etched with groove structure；
Step 33, semiconductor layer is performed etching, removes the semiconductive layer outside groove structure, obtain semiconductor layer pattern；
In the step, if etch thicknesses are equal to the thickness of semiconductor layer pattern, the semiconductor layer pattern produced can be in insulating layer
Same plane；
Step 34, the sedimentary origin drain metal layer 5 on the substrate for producing semiconductor pattern layer；
Step 35, source-drain electrode metal layer is performed etching, obtains data line, source electrode 6 and drain electrode 7；
On above-mentioned basis, if after subsequently producing pixel electrode pattern, structure as shown in Figure 4 is can obtain, is compared
The TFT substrate of top gate structure shown in FIG. 1, it can be seen that the segment difference h height near pixel edges is about etc. in the prior art
In semiconductor layer pattern 8 and source-drain electrode pattern (6,7) thickness and, and in this realization method one, it is assumed that etch thicknesses is partly
Conductor layer pattern thickness, then the segment difference height h1 near last pixel edges be approximately equal to source-drain electrode pattern thickness.
<Realization method two>, the protrusion of counteracting source-drain electrode pattern：
In realization method two, the technical process of the pattern-producing method as shown in Fig. 5 A- Fig. 5 E, including：
Step 51, (the left groove structure pair of groove structure 3 of source-drain electrode pattern is etched on the insulating layer 2 of substrate 1
It answers data line and pattern that source electrode collectively constitutes, right groove structure corresponds to drain electrode pattern)；Wherein, etch thicknesses should be small
In the thickness of insulating layer；
Step 52, semiconductor layer 4 is formed on the substrate for be etched with groove structure；
Step 53, semiconductor layer is performed etching to obtain semiconductor layer pattern；
Step 54, the sedimentary origin drain metal layer 5 on the substrate for producing semiconductor pattern layer；
Step 55, source-drain electrode metal layer is performed etching, obtains data line, source electrode 6 and drain electrode 7；
On above-mentioned basis, if after subsequently producing pixel electrode pattern, structure as shown in Figure 6 is can obtain, is compared
The TFT substrate of top gate structure shown in FIG. 1, it can be seen that the segment difference height h of 9 adjacent edges of pixel region is about in the prior art
Equal to semiconductor layer pattern 8 and source-drain electrode pattern (6,7) thickness and, and in this realization method two, it is assumed that etch thicknesses are
Source-drain electrode pattern thickness, then the segment difference height h2 near last pixel edges be approximately equal to semiconductor layer pattern thickness-
Pixel electrode thickness (i.e. the pattern layer of pixel region).
<Realization method three>, offset the protrusion of semiconductor layer pattern and source-drain electrode pattern：
In the present embodiment three, the technical process of the pattern-producing method as shown in Fig. 7 A- Fig. 7 E, including：
Step 71, by the first recess etch technique, the of semiconductor layer pattern is first etched in the insulating layer 2 of substrate 1
One groove structure 3；
Step 72, by the second recess etch technique, on the insulating layer of the first groove structure is etched with, according to source and drain electricity
Pole figure case continues to etch, and obtains the insulating layer of 3 ＇ of the second groove structure；Wherein, it is described to ensure that insulating layer is not cut through
The etch thicknesses of first recess etch technique and the thickness of insulating layer described in the etch thicknesses ＜ of the+the second recess etch technique
Degree；
Furthermore, it is necessary to be described, the method for the etched recesses structure of this step is not unique, such as：It can also be
On insulating layer, it is right directly once to etch the composite pattern institute that data line, source-drain electrode and semiconductor layer pattern collectively constitute
The groove structure answered；
Step 73, deposited semiconductor layer 4；
Step 74, sedimentary origin drain metal layer 5；
Step 75, source-drain electrode metal layer and the semiconductor layer in non-recessed structure are etched away by a Mapping Technology,
So as to once directly produce semiconductor pattern, data line, source electrode 6 and drain electrode 7；
On above-mentioned basis, if after subsequently producing pixel electrode pattern, structure as shown in Figure 8 is can obtain, is compared
The TFT substrate of top gate structure shown in FIG. 1, it can be seen that the segment difference h height near pixel edges 9 is about in the prior art
Equal to semiconductor layer pattern 8 and source-drain electrode pattern (6,7) thickness and, and in this realization method three, the edge of pixel region 9
Segment difference is nearby not present.
By embodiment one, embodiment two and embodiment three it is recognised that the present invention pattern-producing method either only
It etches the groove structure of semiconductor layer pattern or the groove structure of source-drain electrode pattern or etches semiconductor simultaneously
The groove structure of layer pattern and source-drain electrode pattern can improve the flatness near pixel edges.
In addition, another embodiment of the present invention also provides a kind of array substrate manufactured using above-mentioned pattern-producing method,
The insulating layer of the array substrate has groove structure, and the insulating layer of the array substrate has groove structure, is formed in described
Functional pattern at least part on insulating layer is Chong Die with the groove structure.
Illustratively, the array substrate (on the left of Fig. 9) and the present embodiment of the bottom grating structure shown in Fig. 9 for being the prior art
The contrast schematic diagram of the array substrate (on the right side of Fig. 9) of bottom grating structure, the permutation substrate source-drain electrode region (source electrode of the prior art
6th, drain electrode 7 and semiconductor layer pattern 8) pixel region segment difference height for h, the permutation substrate of the present embodiment is in pixel region
The segment difference height in domain is h ＇.Due to being etched with groove structure 11 on the insulating layer 1 of the array substrate of the present embodiment, can support
Disappear protrusion of the source-drain electrode region on insulating layer 1, makes h ＇ ＜ h.
In addition, another embodiment of the present invention also provides a kind of display device, including above-mentioned array substrate.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, several improvements and modifications can also be made, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (3)
1. a kind of pattern-producing method, for forming semiconductor layer pattern and source-drain electrode on substrate of the top layer for insulating layer
Pattern, which is characterized in that the pattern-producing method includes：
The first groove structure of semiconductor layer pattern is etched in the insulating layer of substrate；
On the insulating layer of the first groove structure is etched with, continue to etch according to source-drain electrode pattern, obtain the second groove
The insulating layer of structure；Wherein, the etching of the etch thicknesses of the first recess etch technique+the second recess etch technique is thick
Spend the thickness of insulating layer described in ＜；
Deposited semiconductor layer；
Sedimentary origin drain metal layer；
Source-drain electrode metal layer and the semiconductor layer in non-recessed structure are etched away by a Mapping Technology, so as to primary direct
Produce semiconductor pattern and source-drain electrode pattern.
2. a kind of array substrate, which is characterized in that the functional pattern of the array substrate is by graphic making described in claim 1
Method makes to obtain.
3. a kind of display device, which is characterized in that including array substrate as claimed in claim 2.
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| CN201510062159.0A CN104617041B (en) | 2015-02-05 | 2015-02-05 | A kind of pattern-producing method, array substrate and display device |
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| CN201510062159.0A CN104617041B (en) | 2015-02-05 | 2015-02-05 | A kind of pattern-producing method, array substrate and display device |
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| CN104617041B true CN104617041B (en) | 2018-06-26 |
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| CN109698206B (en) * | 2018-12-26 | 2021-05-28 | 上海天马微电子有限公司 | Array substrate, preparation method thereof, display panel and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101561602A (en) * | 2008-04-15 | 2009-10-21 | 北京京东方光电科技有限公司 | Array substrate of liquid crystal display device |
| CN104078470A (en) * | 2014-06-18 | 2014-10-01 | 京东方科技集团股份有限公司 | Array substrate, producing method thereof, display device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101561602A (en) * | 2008-04-15 | 2009-10-21 | 北京京东方光电科技有限公司 | Array substrate of liquid crystal display device |
| CN104078470A (en) * | 2014-06-18 | 2014-10-01 | 京东方科技集团股份有限公司 | Array substrate, producing method thereof, display device |
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