CN103489878A - Array substrate, preparing method of array substrate and display device of array substrate - Google Patents
Array substrate, preparing method of array substrate and display device of array substrate Download PDFInfo
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- CN103489878A CN103489878A CN201310469636.6A CN201310469636A CN103489878A CN 103489878 A CN103489878 A CN 103489878A CN 201310469636 A CN201310469636 A CN 201310469636A CN 103489878 A CN103489878 A CN 103489878A
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Abstract
The invention provides an array substrate, a preparing method of the array substrate and a display device of the array substrate. The array substrate comprises a substrate body, a thin film transistor, a grid line and a data line, wherein the thin film transistor, the grid line and the data line are arranged on the substrate body. The thin film transistor comprises a grid electrode, a source electrode, a drain electrode and a grid insulating layer arranged between the grid electrode, the source electrode and the drain electrode, wherein the grid electrode is electrically connected with the grid line, a data line embedding area is arranged in the grid insulating layer, the data line is positioned in the data line embedding area, and the data line is electrically connected with the source electrode. The array substrate is arranged in the data line embedding area of the grid insulating layer through the data line, so that no offset or small offset is generated in the edge area, corresponding to other areas in a pixel area, of the data line. Thus, no friction weak area is generated in alignment layer friction, no light leakage is generated, accordingly the black array width above the data line is reduced, and the aperture opening rate of a display panel is improved. The display device uses the array substrate to improve contract ratio and light transmittance.
Description
Technical field
The present invention relates to the Display Technique field, particularly, relate to a kind of array base palte and preparation method thereof and display unit.
Background technology
Along with the development of Display Technique, people are more and more higher to the requirement of high brightness, high-contrast, low energy consumption display unit.
At present, panel display apparatus is prevailing, and panel display apparatus generally faces problem how to avoid light leak in manufacture process.
As: for ADS (Advanced Super Dimension Switch, a senior super dimension switch technology) liquid crystal indicator of pattern, light leak easily occurs in display floater usually when black state picture, this light leak can cause the black state picture brightness of display floater higher, causes the display floater contrast on the low side; For HADS(High Aperture Ratio Advanced Super Dimension Switch, the senior super dimension of a high aperture switch technology), there is equally above-mentioned light leak in the liquid crystal indicator of pattern and causes contrast problem on the low side.
The main cause that causes the pixel edge light leak is that the weak district of friction (rubbing) forms light leak, wherein, the weak district of friction refers to while by friction mode, in the inboard of array base palte, forming alignment films, be formed with metal wire (as data wire, grid line etc.) zone, because other regional offsets of the relative pixel region of fringe region of metal wire are larger, make friction cloth when this zone because of the zone a little less than the insufficient friction formed that rubs.Usually, the liquid crystal molecular orientation in the weak district of friction is poor, and when black state or white state, can't be orientated according to specific direction may appear in the liquid crystal molecule in the weak district of friction, thereby forms the phenomenon of light leak; Array base palte and color membrane substrates involutory after, when black matrix also can't hide the weak district of friction, light leak will show.
Generally, in the color membrane substrates of grid line top correspondence, black matrix width is larger, therefore, and near rare light leak grid line; And, in order not affect the aperture opening ratio of display floater, black matrix width corresponding to data wire top is generally less, in the situation that array base palte and color membrane substrates contraposition are bad, near data wire particularly the corresponding region, edge of data wire light leakage phenomena often easily appears.
Summary of the invention
The present invention is directed to the above-mentioned technical problem existed in prior art, a kind of array base palte and preparation method thereof and display floater are provided.This array base palte, by data wire data wire is arranged in gate insulation layer, embed in district, be in bar-shaped trough, make other zones in the relative pixel region of fringe region of data wire can not form the offset of offset or formation less, thereby weaken the light leak that the weak district of friction forms, make the fringe region of data wire region in the situation that do not sheltered from by black matrix, also not there will be light leakage phenomena, guaranteed the quality of array base palte.
The invention provides a kind of array base palte, comprise: substrate and be arranged at thin-film transistor, grid line and the data wire on described substrate, described thin-film transistor comprise grid, source electrode and drain electrode and be arranged at described grid and described source electrode and the drain electrode between gate insulation layer, described grid is electrically connected to described grid line, be provided with data wire in described gate insulation layer and embed district, described data wire is arranged at described data wire and embeds in district, and described data wire is electrically connected to described source electrode.
Preferably, described grid line and described data wire are arranged in a crossed manner is divided into a plurality of pixel regions by described substrate, described thin-film transistor is arranged in described pixel region, described data wire embeds district and is opened in the bar-shaped trough beyond corresponding described thin-film transistor setting area in described gate insulation layer, and the bearing of trend of described bar-shaped trough is vertical with the bearing of trend of described grid line.
Preferably, described bar-shaped trough is opened in the data wire cabling zone between corresponding adjacent pixel regions, and the width of described data wire is less than or equal to the width of described bar-shaped trough.
Preferably, the degree of depth of described bar-shaped trough equals the thickness of described gate insulation layer, and described data wire and described grid line arrange with layer, and the height of described data wire is less than or equal to the thickness of described gate insulation layer;
Perhaps, described bar-shaped trough is opened in the top layer of described gate insulation layer, and the degree of depth of described bar-shaped trough is less than the thickness of described gate insulation layer, and described data wire is arranged at the bottom of described bar-shaped trough, and the height of described data wire is less than or equal to the degree of depth of described bar-shaped trough.
The present invention also provides a kind of display unit, comprises above-mentioned array base palte.
The present invention also provides a kind of preparation method of array base palte, comprise: the step that forms thin-film transistor, grid line and data wire on substrate, the step that forms described thin-film transistor comprises the step of the figure of the figure that forms grid, the source electrode arranged with layer and drain electrode, described method also comprises, adopt composition technique, formation comprises the figure of gate insulation layer and the step that data wire embeds the figure in district, described data wire is formed at described data wire and embeds in district, and described data wire is electrically connected to described source electrode.
Preferably, described data wire embeds district and is formed at the bar-shaped trough beyond corresponding described thin-film transistor setting area in described gate insulation layer, and the bearing of trend of described bar-shaped trough is vertical with the bearing of trend of described grid line.
Preferably, formation comprises that the figure of gate insulation layer and the step that data wire embeds the figure in district comprise: adopt panchromatic tune mask plate, form and comprise the figure of described gate insulation layer and the figure of described bar-shaped trough in composition technique, the degree of depth of described bar-shaped trough equals the thickness of described gate insulation layer;
Perhaps, adopt half-tone mask plate, in composition technique, form and comprise the figure of described gate insulation layer and the figure of described bar-shaped trough, described bar-shaped trough is formed at the top layer of described gate insulation layer, and the degree of depth of described bar-shaped trough is less than the thickness of described gate insulation layer.
Preferably, described bar-shaped trough is formed on the data wire cabling zone between corresponding adjacent pixel regions, and the width of described data wire is less than or equal to the width of described bar-shaped trough.
Preferably, the height of described data wire is less than or equal to the degree of depth of described bar-shaped trough.
Beneficial effect of the present invention: array base palte provided by the present invention, by data wire data wire is arranged in gate insulation layer, embed in district, be in bar-shaped trough, make other zones in the relative pixel region of fringe region of data wire can not form the offset of offset or formation less, thereby make array base palte when friction forms alignment films, friction cloth is all more consistent with the friction in other zones to the data wire region, the weak district of friction that can not form the weak district of friction or formation is less, and then make the fringe region of data wire region in the situation that do not sheltered from by black matrix, not there will be light leakage phenomena yet, guaranteed the quality of array base palte.Display unit provided by the present invention, owing to adopting above-mentioned array base palte, on the one hand, display unit not there will be light leakage phenomena, thereby has improved the contrast of display unit; On the other hand, even the width of the black matrix of data wire top correspondence reduces, can not cause display unit light leakage phenomena to occur yet, thereby improve the light transmittance of display unit yet.
The accompanying drawing explanation
The floor map that Fig. 1 is array base palte in the embodiment of the present invention 1;
Fig. 2 be in Fig. 1 array base palte along the cutaway view of AA cutting line position;
Fig. 3 be in Fig. 1 array base palte along the cutaway view of BB cutting line position;
Fig. 4 A is for forming the step schematic diagram of the figure that comprises grid and grid line;
Fig. 4 B is for forming the step schematic diagram of the figure that comprises gate insulation layer and bar-shaped trough;
Fig. 4 C is for forming the step schematic diagram of the figure that comprises active layer;
Fig. 4 D is for forming the step schematic diagram of the figure that comprises pixel electrode;
Fig. 4 E is for forming the step schematic diagram of the figure that comprises data wire, source electrode and drain electrode;
Fig. 4 F is for forming the step schematic diagram of the figure that comprises passivation layer;
Fig. 4 G is for forming the step schematic diagram of the figure that comprises public electrode;
Fig. 5 is that in the embodiment of the present invention 2, the array base palte correspondence in Fig. 1 the cutaway view along BB cutting line position.
Description of reference numerals wherein:
1. substrate; 2. thin-film transistor; 21. grid; 22. source electrode; 23. drain electrode; 24. gate insulation layer; 241. bar-shaped trough; 25. active layer; 3. grid line; 4. data wire; 5. pixel electrode; 6. passivation layer; 7. public electrode.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with the drawings and specific embodiments, a kind of array base palte of the present invention and preparation method thereof and display unit are described in further detail.
Embodiment 1:
The present embodiment provides a kind of array base palte, as depicted in figs. 1 and 2, comprise: substrate 1 and be arranged at thin-film transistor 2, grid line 3 and the data wire 4 on substrate 1, thin-film transistor 2 comprises grid 21, the source electrode 22 arranged with layer and drains 23 and the gate insulation layer 24 that is arranged at grid 21 and source electrode 22 and drains between 23, grid 21 is electrically connected to grid line 3, be provided with data wire in gate insulation layer 24 and embed district, data wire 4 is arranged at data wire and embeds in district, and data wire 4 is electrically connected to source electrode 22.
In addition, in the present embodiment, thin-film transistor also comprises active layer 25, active layer 25 be arranged on source electrode 22 and drain 23 and gate insulation layer 24 between, and with the corresponding setting of grid 21.
Wherein, grid line 3 and data wire 4 are arranged in a crossed manner is divided into a plurality of pixel regions by substrate 1, thin-film transistor 2 is arranged in pixel region, data wire embeds district and is opened in the bar-shaped trough 241 beyond corresponding thin-film transistor 2 setting areas in gate insulation layer 24, and the bearing of trend of bar-shaped trough 241 is vertical with the bearing of trend of grid line 3.
In addition, also be provided with pixel electrode 5 in pixel region, pixel electrode 5 is arranged between gate insulation layer 24 and drain electrode 23.Array base palte in the present embodiment also comprises passivation layer 6 and public electrode 7, and passivation layer 6 is arranged on source electrode 22 and drain electrode 23 tops and covers whole array base palte, and public electrode 7 is arranged on passivation layer 6 tops.Wherein, public electrode 7 is bar shaped slit-shaped structure, and pixel electrode 5 is tabular.
In the present embodiment, as shown in Figure 3, bar-shaped trough 241 is opened in the data wire cabling zone between corresponding adjacent pixel regions, and the width of data wire 4 is less than or equal to the width of bar-shaped trough 241.The degree of depth of bar-shaped trough 241 equals the thickness of gate insulation layer 24, and data wire 4 arranges with layer with grid line 3, and the height of data wire 4 is less than or equal to the thickness of gate insulation layer 24.So arrange, can make data wire 4 be embedded in fully in bar-shaped trough 241, preferably make the upper surface of data wire 4 flush with the notch of bar-shaped trough 241, thereby make other zones in the relative pixel region of data wire 4 only can form less offset or can not form offset.
Wherein, gate insulation layer 24 adopts silicon nitride or silica material, and data wire 4 adopts molybdenum, aluminium, neodymium aluminium alloy, copper, titanium or alloy material.
The present embodiment also provides a kind of preparation method of above-mentioned array base palte, as shown in Fig. 4 A-4G, comprise: the step that forms thin-film transistor 2, grid line 3 and data wire 4 on substrate, the step that forms thin-film transistor 2 comprises the figure that forms grid 21, with the step of the source electrode 22 of layer setting and 23 the figure of draining, this preparation method also comprises, adopt one time composition technique, formation comprises the figure of gate insulation layer 24 and the step that data wire embeds the figure in district, data wire 4 is formed at data wire and embeds in district, and data wire 4 is electrically connected to source electrode 22.In addition, this preparation method also comprises the step of the figure of the figure of figure, passivation layer 6 of the figure that forms active layer 25, pixel electrode 5 and public electrode 7.
Wherein, data wire embeds district and is formed at the bar-shaped trough 241 beyond corresponding thin-film transistor 2 setting areas in gate insulation layer 24, and the bearing of trend of bar-shaped trough 241 is vertical with the bearing of trend of grid line 3.
Particularly, the preparation method of this array base palte comprises the following steps:
Step S1: adopt composition technique one time, on substrate 1, form and comprise the figure of grid 21 and the figure (as shown in Figure 4 A) of grid line 3.
In this step, at first, adopt sputtering method to deposit layer of metal film on substrate 1, this metal film adopts molybdenum, aluminium, neodymium aluminium alloy, copper, titanium or alloy material; Then by exposure, development and wet-etching technology, form the figure of grid 21 and the figure of grid line 3.Wherein, grid 21 is electrically connected to grid line 3.
Step S2: adopt composition technique one time, on the substrate 1 of completing steps S1, form and comprise the figure of gate insulation layer 24 and the figure (as shown in Figure 4 B) of bar-shaped trough 241.
In this step, first by chemical vapour deposition technique, on the substrate 1 of completing steps S1, deposit one deck layer gate insulating film, this layer gate insulating film adopts silicon nitride or silica material;
Apply one deck photoresist on layer gate insulating film;
Adopt panchromatic tune mask plate, by single exposure and developing process, retain on layer gate insulating film corresponding the photoresist that forms the gate insulation layer part fully, remove fully corresponding the photoresist that forms the bar-shaped trough part and except gate insulation layer partly the photoresist of other parts;
Through dry etch process, correspondence to the layer gate insulating film etching of having removed photoresist fully and remove;
Remove or peel off the photoresist of remainder.Thereby form the bar-shaped trough in gate insulation layer and gate insulation layer.Wherein, the degree of depth of bar-shaped trough equals the thickness of gate insulation layer.
Form the figure of gate insulation layer 24 and the figure of bar-shaped trough 241 by above step.Wherein, the degree of depth of bar-shaped trough 241 equals the thickness of gate insulation layer 24, and bar-shaped trough 241 is formed on the data wire cabling zone between corresponding adjacent pixel regions.
Step S3: adopt composition technique, form the figure (as shown in Figure 4 C) of active layer 25 on the substrate 1 of completing steps S2.
In this step, first by chemical vapour deposition technique, on the substrate 1 of completing steps S2, deposit active tunic, this active tunic adopts amorphous silicon material; Then by exposure, development and dry etch process, form the figure of active layer 25.Active layer 25 and the corresponding setting of grid 21.
Step S4: adopt composition technique, form the figure (as shown in Figure 4 D) of pixel electrode 5 on the substrate 1 of completing steps S3.
In this step, first adopt sputtering method to deposit the layer of metal oxidation film on the substrate 1 of completing steps S3, this metal oxide film adopts tin indium oxide (ITO) material; Then by exposure, development and wet-etching technology, form the figure of pixel electrode 5.Pixel electrode 5 is formed in pixel region.
Step S5: adopt composition technique one time, form the figure of the figure comprise data wire 4, source electrode 22 and 23 the figure (as shown in Figure 4 E) of draining on the substrate 1 of completing steps S4.
In this step, first adopt sputtering method to deposit layer of metal film on the substrate 1 of completing steps S4, this metal film adopts molybdenum, aluminium, neodymium aluminium alloy, copper, titanium or alloy material; Then by exposure, development and wet-etching technology, form figure and 23 the figure of draining of figure, the source electrode 22 of data wire 4.Wherein, data wire 4 is formed in bar-shaped trough 241, and with grid line 3 in same layer; And the width of data wire 4 is less than or equal to the width of bar-shaped trough 241, the height of data wire 4 is less than or equal to the thickness of gate insulation layer 24.Therefore, data wire 4 can be embedded in bar-shaped trough 241 fully, thereby makes other zones in the relative pixel region of data wire 4 can not form offset.Drain electrode 23 is arranged on pixel electrode 5 tops and is electrically connected to it.
Step S6: adopt composition technique, form the figure (as shown in Fig. 4 F) of passivation layer 6 on the substrate 1 of completing steps S5.
In this step, first by chemical vapour deposition technique, on the substrate 1 of completing steps S5, deposit one deck passivation tunic, this passivation tunic adopts silicon nitride or silica material; Then by exposure, development and dry etch process, form the figure of passivation layer 6.Passivation layer 6 covers the whole substrate of completing steps S5 1.
Step S7: adopt composition technique, form the figure (as shown in Fig. 4 G) of public electrode 7 on the substrate 1 of completing steps S6.
In this step, first adopt sputtering method to deposit the layer of metal oxidation film on the substrate 1 of completing steps S6, this metal oxide film adopts tin indium oxide (ITO) material; Then by exposure, development and wet-etching technology, form the figure of public electrode 7.Wherein, public electrode 7 is formed on passivation layer 6 tops, and public electrode 7 is bar shaped slit-shaped structure.
So far, array base palte prepares complete substantially, and then next step be in the inboard alignment films that forms of this array base palte, alignment films forms by the friction of friction cloth pair array substrate inner surface, in the present embodiment, because data wire 4 is embedded in the bar-shaped trough 241 in gate insulation layer 24 fully, make other zones of the relative pixel region of fringe region of data wire 4 only have less offset or not have offset, be also that the array base palte inner surface is relatively smooth, thereby make friction cloth friction ratio through data wire 4 region the time more abundant, can not form the weak district of friction, therefore, even the fringe region of data wire 4 regions is not blocked by black matrix, not there will be light leakage phenomena yet.
In addition, it should be noted that, in the preparation method of above-mentioned array base palte, in step S2, can first by chemical vapour deposition technique, on the substrate of completing steps S1, deposit one deck layer gate insulating film; Then after completing steps S3 and S4, then adopt panchromatic tune mask plate, by single exposure, development and dry etch process, form the figure of gate insulation layer and the figure of bar-shaped trough.
Embodiment 2:
The present embodiment provides a kind of array base palte, as different from Example 1, as shown in Figure 5, bar-shaped trough 241 is opened in the top layer of gate insulation layer 24, and the degree of depth of bar-shaped trough 241 is less than the thickness of gate insulation layer 24, data wire 4 is arranged at the bottom of bar-shaped trough 241, and the height of data wire 4 is less than or equal to the degree of depth of bar-shaped trough 241.So arrange, can make equally data wire 4 be embedded in fully in bar-shaped trough 241, thereby make other zones in the relative pixel region of data wire 4 only form less offset or can not form offset.
In addition, because grid line (not shown in Fig. 5) is arranged on the below of gate insulation layer 24, so between data wire 4 and grid 21/ grid line 3 also between across the gate insulation layer 24 of skim, the difference between the gross thickness that the thickness of the gate insulation layer 24 of this skim is gate insulation layer 24 and the degree of depth of bar-shaped trough 241.So arrange, be conducive between data wire 4 and grid 21/ grid line 3 keep insulation and antistatic puncturing.
In the present embodiment, other structures, size and the material of array base palte is in the same manner as in Example 1, repeats no more herein.
Correspondingly, the present embodiment also provides a kind of preparation method of above-mentioned array base palte, different from the preparation method in embodiment 1, in formation, comprises in the step of the figure of gate insulation layer and the figure that data wire embeds district, also in step S2, is specially:
Apply one deck photoresist on layer gate insulating film;
Adopt half-tone mask plate, by single exposure and developing process, retain on layer gate insulating film corresponding the photoresist that forms the gate insulation layer part fully, part retains corresponding the photoresist that forms the bar-shaped trough part, removes other photoresist except these two parts fully;
Through dry etch process, correspondence to the layer gate insulating film etching of having removed photoresist fully and remove;
Again by a cineration technics, continue to retain corresponding the photoresist that forms the gate insulation layer part, and to the photoresist that forms the bar-shaped trough part, correspondence removes;
Through dry etch process, correspondence to the gate insulation layer membrane portions of having removed photoresist and carry out the partial etching removal, thereby form bar-shaped trough in layer gate insulating film.Wherein, the degree of depth of bar-shaped trough can be controlled by the concentration of etch rate and etching liquid, and the degree of depth of bar-shaped trough is less than the thickness of layer gate insulating film.
Remove or peel off the photoresist of remainder.
Form the figure of gate insulation layer and the figure of bar-shaped trough by above step.Wherein, bar-shaped trough is formed at the top layer of gate insulation layer, and the degree of depth of bar-shaped trough is less than the thickness of gate insulation layer.
Other preparation methods and the step of array base palte are in the same manner as in Example 1, repeat no more herein.
Embodiment 3:
The present embodiment provides a kind of array base palte, different from embodiment 1-2, the location swap of public electrode and pixel electrode in this array base palte, and pixel electrode is arranged on the passivation layer top, and pixel electrode is bar shaped slit-shaped structure; And public electrode is arranged between gate insulation layer and passivation layer, and public electrode is tabular.
Correspondingly, the preparation method based on array base palte in embodiment 1, in the preparation method of this array base palte, the step (being step S4) that forms pixel electrode is successively exchanged and is got final product with the step (being step S7) that forms public electrode.
In the present embodiment, other structures, size, material and the preparation method of array base palte, with identical in embodiment 1 or 2, repeat no more herein.
Array base palte in embodiment 1-3, be applicable to ADS(ADvanced Super Dimension Switch, a senior super dimension switch technology) and HADS(High Aperture Ratio Advanced Super Dimension Switch, the senior super dimension of a high aperture field switch technology) in the display panels of pattern.
Embodiment 4:
The present embodiment provides a kind of array base palte, different from embodiment 1-3, in this array base palte, does not comprise public electrode.
Correspondingly, the preparation method based on the arbitrary middle array base palte of embodiment 1-3, do not comprise the step that forms public electrode in the preparation method of array base palte in the present embodiment.
In the present embodiment, other structures, size, material and the preparation method of array base palte, with arbitrary identical in embodiment 1-3, repeat no more herein.
Array base palte in the present embodiment, be applicable to TN(Twisted Nematic, twisted-nematic) pattern, VA(Vertical Alignment, vertical orientated) in the display panels of pattern.
The beneficial effect of embodiment 1-4: the array base palte provided in embodiment 1-4, by data wire data wire is arranged in gate insulation layer, embed in district, be in bar-shaped trough, make other interior zones of the relative pixel region of fringe region of data wire only form less offset or can not form offset, thereby make array base palte when friction forms alignment films, friction cloth is more abundant to the friction ratio of data wire region, only form the weak district of less friction or can not form the weak district of friction, and then make the fringe region of data wire region in the situation that do not sheltered from by black matrix, not there will be light leakage phenomena, guaranteed the quality of array base palte.
Embodiment 5:
The present embodiment provides a kind of display unit, comprises the array base palte of embodiment 1-4 in arbitrary.
The display unit that the present embodiment provides, owing to adopting the arbitrary array base palte of embodiment 1-4, on the one hand, display unit not there will be light leakage phenomena, thereby has improved the contrast of display unit; On the other hand, even the width of the black matrix of data wire top correspondence reduces, can not cause display unit light leakage phenomena to occur yet, thereby improve the light transmittance of display unit yet.
Described display unit can be: any product or parts with Presentation Function such as liquid crystal panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Be understandable that, above execution mode is only the illustrative embodiments adopted for principle of the present invention is described, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement also are considered as protection scope of the present invention.
Claims (10)
1. an array base palte, comprise: substrate and be arranged at thin-film transistor, grid line and the data wire on described substrate, described thin-film transistor comprise grid, source electrode and drain electrode and be arranged at described grid and described source electrode and the drain electrode between gate insulation layer, described grid is electrically connected to described grid line, it is characterized in that, be provided with data wire in described gate insulation layer and embed district, described data wire is arranged at described data wire and embeds in district, and described data wire is electrically connected to described source electrode.
2. array base palte according to claim 1, it is characterized in that, described grid line and described data wire are arranged in a crossed manner is divided into a plurality of pixel regions by described substrate, described thin-film transistor is arranged in described pixel region, described data wire embeds district and is opened in the bar-shaped trough beyond corresponding described thin-film transistor setting area in described gate insulation layer, and the bearing of trend of described bar-shaped trough is vertical with the bearing of trend of described grid line.
3. array base palte according to claim 2, is characterized in that, described bar-shaped trough is opened in the data wire cabling zone between corresponding adjacent pixel regions, and the width of described data wire is less than or equal to the width of described bar-shaped trough.
4. array base palte according to claim 3, is characterized in that, the degree of depth of described bar-shaped trough equals the thickness of described gate insulation layer, and described data wire and described grid line arrange with layer, and the height of described data wire is less than or equal to the thickness of described gate insulation layer;
Perhaps, described bar-shaped trough is opened in the top layer of described gate insulation layer, and the degree of depth of described bar-shaped trough is less than the thickness of described gate insulation layer, and described data wire is arranged at the bottom of described bar-shaped trough, and the height of described data wire is less than or equal to the degree of depth of described bar-shaped trough.
5. a display unit, is characterized in that, comprises the described array base palte of claim 1-4 any one.
6. the preparation method of an array base palte, comprise: the step that forms thin-film transistor, grid line and data wire on substrate, the step that forms described thin-film transistor comprises the step of the figure of the figure, source electrode and the drain electrode that form grid, it is characterized in that, described method also comprises, adopts composition technique, and formation comprises the figure of gate insulation layer and the step that data wire embeds the figure in district, described data wire is formed at described data wire and embeds in district, and described data wire is electrically connected to described source electrode.
7. preparation method according to claim 6, it is characterized in that, it is characterized in that, described data wire embeds district and is formed at the bar-shaped trough beyond corresponding described thin-film transistor setting area in described gate insulation layer, and the bearing of trend of described bar-shaped trough is vertical with the bearing of trend of described grid line.
8. preparation method according to claim 7, it is characterized in that, formation comprises that the figure of gate insulation layer and the step that data wire embeds the figure in district comprise: adopt panchromatic tune mask plate, form and comprise the figure of described gate insulation layer and the figure of described bar-shaped trough in composition technique, the degree of depth of described bar-shaped trough equals the thickness of described gate insulation layer;
Perhaps, adopt half-tone mask plate, in composition technique, form and comprise the figure of described gate insulation layer and the figure of described bar-shaped trough, described bar-shaped trough is formed at the top layer of described gate insulation layer, and the degree of depth of described bar-shaped trough is less than the thickness of described gate insulation layer.
9. preparation method according to claim 8, is characterized in that, described bar-shaped trough is formed on the data wire cabling zone between corresponding adjacent pixel regions, and the width of described data wire is less than or equal to the width of described bar-shaped trough.
10. preparation method according to claim 9, is characterized in that, the height of described data wire is less than or equal to the degree of depth of described bar-shaped trough.
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| WO2017148029A1 (en) * | 2016-03-02 | 2017-09-08 | 京东方科技集团股份有限公司 | Display panel, display apparatus and manufacturing method for display panel |
| CN107422543A (en) * | 2017-07-04 | 2017-12-01 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof, display device |
| CN113495387A (en) * | 2020-03-18 | 2021-10-12 | 株式会社日本显示器 | Semiconductor substrate and display device |
| CN114578608A (en) * | 2022-03-30 | 2022-06-03 | 北京京东方显示技术有限公司 | Display substrate and display panel |
| WO2023206626A1 (en) * | 2022-04-29 | 2023-11-02 | 广州华星光电半导体显示技术有限公司 | Display panel and display apparatus |
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| WO2017148029A1 (en) * | 2016-03-02 | 2017-09-08 | 京东方科技集团股份有限公司 | Display panel, display apparatus and manufacturing method for display panel |
| US10606132B2 (en) | 2016-03-02 | 2020-03-31 | Boe Technology Group Co., Ltd. | Display panel, display device, and method for manufacturing display panel |
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| CN106932942B (en) * | 2017-03-24 | 2020-07-28 | 厦门天马微电子有限公司 | Touch control display device |
| CN107422543A (en) * | 2017-07-04 | 2017-12-01 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof, display device |
| CN113495387A (en) * | 2020-03-18 | 2021-10-12 | 株式会社日本显示器 | Semiconductor substrate and display device |
| JP7434005B2 (en) | 2020-03-18 | 2024-02-20 | 株式会社ジャパンディスプレイ | Semiconductor substrates and display devices |
| CN113495387B (en) * | 2020-03-18 | 2024-03-22 | 株式会社日本显示器 | Semiconductor substrate and display device |
| CN114578608A (en) * | 2022-03-30 | 2022-06-03 | 北京京东方显示技术有限公司 | Display substrate and display panel |
| WO2023206626A1 (en) * | 2022-04-29 | 2023-11-02 | 广州华星光电半导体显示技术有限公司 | Display panel and display apparatus |
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