CN104616991B - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN104616991B CN104616991B CN201310541727.6A CN201310541727A CN104616991B CN 104616991 B CN104616991 B CN 104616991B CN 201310541727 A CN201310541727 A CN 201310541727A CN 104616991 B CN104616991 B CN 104616991B
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- 239000002184 metal Substances 0.000 claims abstract description 49
- OKTJSMMVPCPJKN-UHFFFAOYSA-N carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 27
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- 239000010410 layer Substances 0.000 claims description 105
- 239000000463 material Substances 0.000 claims description 46
- 239000011229 interlayer Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
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- MYMOFIZGZYHOMD-UHFFFAOYSA-N oxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 10
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- 238000000227 grinding Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
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- 239000010703 silicon Substances 0.000 claims description 7
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- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
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- XCCANNJCMHMXBZ-UHFFFAOYSA-N hydroxyiminosilicon Chemical compound ON=[Si] XCCANNJCMHMXBZ-UHFFFAOYSA-N 0.000 claims description 4
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Abstract
A kind of forming method of fin formula field effect transistor, including：Substrate is provided；Hard mask is formed over the substrate, and there is hard mask flagpole pattern to define the region of fin；It is formed on the substrate and the flagpole pattern and the pseudo- grid structure across the flagpole pattern；Using dummy gate structure as mask, ion implanting is carried out to the substrate, forms source, drain region；Remove the pseudo- grid；The substrate is performed etching, forms a plurality of fin with certain altitude；Gate dielectric layer, metal gates are formed on the upper surface of a plurality of fin, side wall.Forming method of the present invention can make the pseudo- grid pattern being lithographically formed more preferably；And source/drain region engagement pad is eliminated, avoids the influence of resistance, parasitic capacitor variations to fin formula field effect transistor performance caused by source/drain region engagement pad and metal gates are not parallel；By being processed further, the double-gated transistor with graphene oxide gate dielectric layer can also be formed.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of fin formula field effect transistor.
Background technology
With being gradually reduced for semiconductor feature sizes, transistor starts gradually from planar transistor to three-dimensional（3D）Fin
Field-effect transistor（FinFET）The transition of device architecture.In fin formula field effect transistor, grid at least can be from both sides to super
The fin of thin body is controlled, therefore grid is stronger to the control ability of raceway groove, can be good at inhibiting short-channel effect.
Fig. 1 shows a kind of dimensional structure diagram of fin formula field effect transistor of the prior art.As shown in Figure 1, fin
Formula field-effect transistor includes：Semiconductor substrate 10 is formed with projective structure in the Semiconductor substrate 10（It is not indicated in figure）；
Oxide layer 11 covers the surface of the Semiconductor substrate 10 and a part for projective structure side wall, and projective structure is beyond oxidation
The part of layer 11 becomes the fin of fin formula field effect transistor（Fin）14；Gate structure, across on the fin 14, described in covering
The top of fin 14 and side wall, gate structure include gate dielectric layer（It is not shown in figure）With the grid on gate dielectric layer
12.For fin formula field effect transistor, the part that the top of fin 14 and the side wall of both sides are in contact with gate structure all becomes
Channel region that is, with multiple grid, is conducive to increase driving current, improves device performance.
In the prior art since a plurality of elongated fin parallel arrangement in fin formula field effect transistor is, it is necessary at fin both ends
Engagement pad is formed, is used to implement being electrically connected for fin and source-drain area.As engagement pad 13 is parallel to the strip of bar shaped grid 12 in Fig. 1
Structure, but can not accomplish to be aligned completely between current engagement pad 13 and grid 12, that is to say, that the engagement pad 13 of bar shaped with
Complete parallel relation between grid 12 so that parasitic capacitance between grid 12 and engagement pad 13 and resistance with bar shaped
The parallel direction of grid on constantly change, influence the performance of fin formula field effect transistor.
It in addition, in existing fin formula field effect transistor forming method, is formed after fin, gate structure is covered in fin,
Since fin has certain altitude, rough surface is provided to the photoetching of the grid of strip afterwards, influences follow-up strip
The lithographic accuracy of grid, and the surface flatness of gate structure is poor, it is necessary to using chemical mechanical grinding after fin is covered
Technique handles the surface of gate structure, but chemical mechanical milling tech be easy to cause device damage, so as to influence most
End form into fin formula field effect transistor electric property.
The content of the invention
The present invention solves the problems, such as it is to propose a kind of forming method of the fin formula field effect transistor of energy optimized device performance.
To solve the above problems, the present invention proposes a kind of forming method of fin formula field effect transistor, including：
Substrate is provided；
Hard mask is formed over the substrate, and the hard mask has the flagpole pattern for forming fin；
The pseudo- grid structure of the flagpole pattern is developed across over the substrate, and dummy gate structure includes pseudo- grid and position
Side wall on pseudo- grid side wall；
Using dummy gate structure and hard mask as mask, ion implanting is carried out to the substrate, forms source, drain region；
Source, drain region substrate on formed and the interlayer dielectric layer that flushes of puppet grid structure；
The pseudo- grid are removed, expose the hard mask below pseudo- grid；
Using the interlayer dielectric layer and the hard mask as mask, the substrate is performed etching, formed multiple fins and
Multiple grooves between fin；
Remove the hard mask of fin upper surface, the upper surface of the fin and side wall, the groove bottom and side wall and
Side wall side wall forms gate dielectric layer；
It is metal filled to groove progress, to form metal gates.
Optionally, the step of providing substrate includes：
Oxygen buried layer and the silicon substrate on the oxygen buried layer are provided；
Performing etching the step of forming fin to substrate includes：The silicon substrate is performed etching and using the oxygen buried layer as
Etching stop layer.
Optionally, the step of forming hard mask on substrate includes：Multiple flagpole patterns are formed on substrate, these
It is mutually parallel between flagpole pattern.
Optionally, in the step of forming hard mask on substrate, the thickness of the hard mask is less than the height of the fin.
Optionally, in the step of forming hard mask on substrate, the material of the hard mask include silicon nitride, silica or
One or more in silicon oxynitride.
Optionally, in the step of forming pseudo- grid structure on substrate, the puppet grid use spin coating proceeding or chemical vapor deposition
Area method is formed.
Optionally, in the step of forming pseudo- grid structure on substrate, the materials of the puppet grid is silicon oxide carbide, amorphous
One kind in carbon, organosiloxane.
Optionally, in the step of forming interlayer dielectric layer, the material of the interlayer dielectric layer includes silicon nitride, silica
Or the one or more in silicon oxynitride.
Optionally, in the step of removal pseudo- grid, gone using the method for cineration technics, wet etching or plasma etching
Except the pseudo- grid.
Optionally, the material of the gate dielectric layer includes hafnium.
Optionally, forming method of the present invention further includes after metal filled to groove progress：
Chemical mechanical grinding is carried out, until exposing the upper surface of the fin, makes the metal gates being located on fin different lateral
Separation；
Removal is located at the gate dielectric layer on the fin side wall, and gap is formed between the fin and metal gates；
Graphene oxide dielectric layer is formed in the gap.
Optionally, the step of graphene oxide dielectric layer is formed in the gap includes：
Graphene oxide dispersion is filled in gap；
Processing is passivated to the graphene dispersing solution, to form graphene oxide dielectric layer.
Optionally, the material of the gate dielectric layer includes amorphous carbon.
Optionally, the step of removing the gate dielectric layer includes：It is gone using wet etching, cineration technics or dry etching
Except the gate dielectric layer.
Compared with prior art, technical scheme has the following advantages：
In the forming method of the present invention, the hard mask with flagpole pattern is formed on substrate, and is formed on the hard mask
The pseudo- grid of flagpole pattern in hard mask since the thickness of hard mask is less than the thickness of fin, carry out on the flagpole pattern
The flatness on surface of the surface of pseudo- grid photoetching than carrying out gate lithography directly on fin is good so that is lithographically formed the precision of pseudo- grid
More preferably, more preferably, the puppet grid are used to define the forming region of fin and metal gates to the follow-up metal gates pattern for substituting pseudo- grid, and
It performs etching to form fin by the substrate to pseudo- grid bottom, the fin that this mode is formed is located in substrate, and does not protrude from lining
Bottom surface carries out flatening process when forming metal gates on fin, and the flatening process is relatively small to the damage of fin, can
To optimize the performance of fin formula field effect transistor.
In alternative, source, drain region are formed as mask using pseudo- grid structure and the hard mask, and pass through multiple parallel strips
Substrate of the figure below pseudo- grid structure is patterned to form fin, so as to so that fin is contacted with source, drain region realization and saved
Source, drain contact pad are avoided because source, drain contact pad and metal gates are not parallel to fin formula field effect transistor performance
It influences.
In alternative, the double grid fin formula field effect transistor with graphene oxide gate dielectric layer, Ke Yijin are formed
One-step optimization device performance.
Description of the drawings
Fig. 1 is a kind of dimensional structure diagram of fin formula field effect transistor of the prior art；
Fig. 2 is the flow chart of one embodiment of manufacturing method of fin formula field effect transistor of the present invention；
Fig. 3 to Figure 19 is the schematic diagram for the fin formula field effect transistor that forming method of the present invention is formed.
Specific embodiment
Be used to implement in the prior art in fin formula field effect transistor source, the engagement pad that drain region is in contact with fin and grid it
Between can not realize the relation being substantially parallel so that the parasitic capacitance between grid and engagement pad is with resistance in the direction of parallel grid
Upper constantly variation affects the performance of fin formula field effect transistor.
Further, since fin has certain altitude, rough surface, shadow are provided to the photoetching of the grid of strip afterwards
Ring the lithographic accuracy of the grid of follow-up strip, and after fin is covered the surface flatness of gate structure it is poor, it is necessary to using
Chemical mechanical milling tech handles the surface of gate structure, but chemical mechanical milling tech be easy to cause device damage
Wound, so as to influence the electric property of finally formed fin formula field effect transistor.
For this purpose, the present invention provides a kind of forming method of fin formula field effect transistor, first being formed on substrate has strip
The hard mask of figure, and the pseudo- grid of flagpole pattern in hard mask are developed across on the hard mask, since the thickness of hard mask is less than
The height of fin carries out the flat of surface of the surface of pseudo- grid photoetching than carrying out gate lithography directly on fin on the flagpole pattern
It is whole to spend so as to be lithographically formed that the precision of pseudo- grid is more preferable, more preferably, the puppet grid are used for the follow-up metal gates pattern for substituting pseudo- grid
The forming region of fin and metal gates is defined, and performs etching to form fin by the substrate to pseudo- grid bottom, this mode is formed
Fin be located in substrate, and do not protrude from substrate surface, flatening process carried out when forming metal gates on fin, it is described flat
Smooth chemical industry skill is relatively small to the damage of fin, can optimize the performance of fin formula field effect transistor.
Width of the length for a plurality of fin that the forming method of fin formula field effect transistor of the present invention is formed with metal gates
It is equal, i.e., a plurality of fin all under the covering of metal gates, the substrate at a plurality of fin both ends by ion implanting form whole source/
Drain region eliminates source/drain region engagement pad, avoids resistance, parasitism caused by source/drain region engagement pad and metal gates are not parallel
Influence of the capacitance variations to fin formula field effect transistor performance.
Further, it is processed further on the basis of the forming method of fin formula field effect transistor provided by the invention, it can
To form the double-gated transistor with graphene oxide dielectric layer.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
With reference to figure 2, the flow chart of one embodiment of manufacturing method of fin formula field effect transistor of the present invention is shown.Manufacturer
Method generally comprises following steps：
Step S1, provides substrate, and the substrate interior is provided with oxygen buried layer；
Step S2, forms hard mask over the substrate, and the hard mask has multiple flagpole patterns for being used to form fin；
Step S3 is developed across the pseudo- grid structure of flagpole pattern in hard mask, dummy gate structure bag over the substrate
Include pseudo- grid and the side wall on pseudo- grid side wall；
Step S4, using dummy gate structure and hard mask as mask, to the substrate carry out ion implanting, formed source,
Drain region；
Step S5, source, drain region substrate on formed and the interlayer dielectric layer that flushes of puppet grid structure；
Step S6 removes the pseudo- grid, exposes the hard mask below pseudo- grid；
Step S7 using the interlayer dielectric layer and the hard mask as mask, performs etching the substrate, is formed multiple
Fin and multiple grooves between fin；
Step S8, the hard mask of removal fin upper surface, in the upper surface of the fin and side wall, the bottom and side of the groove
Gate dielectric layer is formed on wall and side wall side wall；
Step S9, it is metal filled to groove progress, to form metal gates.
With reference to Fig. 3 to Figure 15, the specific steps of the present invention are described in detail.
With reference to figure 3, step S1 is performed, substrate is provided；Substrate described in the present embodiment includes oxygen buried layer 101 and positioned at burying
Silicon substrate 100 in oxygen layer 101.The silicon substrate 100 for forming fin, the performance of the fin of silicon materials by fin profile influenced compared with
Small, the oxygen buried layer 101 is used as etching stop layer during forming fin for etching.
It should be noted that the present invention is not restricted the material of substrate, in other embodiments, the substrate can be with
By being epitaxially-formed germanium silicon layer.
With reference to reference to figure 4 and Fig. 5, described Fig. 5 is sectional views of the Fig. 4 along AA ' hatching lines, in order to clearly show that the shape of pseudo- grid
Into process, compared with Fig. 4, Fig. 5 adds pseudo- gate material layer 201.
Step S2 is performed, hard mask is formed on the substrate 100, the hard mask has multiple flagpole patterns 102, with
Define the position of fin and size in subsequent technique, the multiple 102 flat shape of flagpole pattern arrangement, after the hard mask thickness is less than
The height of the continuous a plurality of fin formed, the i.e. thickness of flagpole pattern 102 are the height less than a plurality of fin being subsequently formed so that follow-up
The pseudo- gate material layer surface smoothness of formation is more preferable, improves the lithographic accuracy of pseudo- grid, and causes the metal gates being subsequently formed
Pattern is more preferably.
In the present embodiment, the material of the hard mask is silicon nitride, and in other embodiments, the hard mask can be with
Using silica or the material different from the pseudo- grid and substrate.
With continued reference to Fig. 4, Fig. 5, and combining with reference to figure 6, Fig. 7, Fig. 7 is sectional views of the Fig. 6 along BB ' lines, performs step S3,
The substrate 100 and described in the pseudo- grid structure of the flagpole pattern 102 is developed across in hard mask.
Include the pseudo- grid structure of flagpole pattern 102 in hard mask is developed across on the substrate 100 the step of：
Organic reflective coating materials are resisted in the substrate 100 and 102 surface of flagpole pattern deposition using spin coating proceeding,
Form pseudo- gate material layer 201.Patterned mask layer is formed on pseudo- 201 surface of gate material layer（It is not shown）, with the figure
The mask layer of shape performs etching the pseudo- gate material layer 201, is developed across the pseudo- grid 104 of flagpole pattern 102 in hard mask,
Side wall 103, the side wall that dummy gate structure includes pseudo- grid 104 and pseudo- 104 both sides of grid are formed are formed in pseudo- 104 both sides of grid
103。
In the present embodiment, pseudo- gate material layer 201 is formed using spin coating proceeding, such to be advantageous in that, spin coating proceeding shape
Into 201 surface smoothness of pseudo- gate material layer it is high, uniformity is good, in other embodiments, can also use chemical vapor deposition
Method forms the pseudo- gate material layer 201.
In the present embodiment, the material of pseudo- gate material layer 201 is organosiloxane（DUO）, it is in other embodiments, described
The material of pseudo- gate material layer 201 can also be silicon oxide carbide, amorphous carbon or other organic antireflective coating materials.
Due to hard mask thickness be less than a plurality of fin being subsequently formed height, i.e., the thickness of flagpole pattern 102 for less than
The height for a plurality of fin being subsequently formed so that 201 surface smoothness of pseudo- gate material layer being subsequently formed is more preferable, improves pseudo- grid
104 lithographic accuracy, and so that the surface of pseudo- grid 104 is flatter, the follow-up metal gates pattern for substituting pseudo- grid 104 is more preferably.Institute
Pseudo- grid 104 are stated for defining the forming region of fin and metal gates, and perform etching to be formed by the substrate to pseudo- 104 bottom of grid
Fin, the fin that this mode is formed is located in substrate, and does not protrude from substrate surface, is put down when forming metal gates on fin
Smooth chemical industry skill, the flatening process are relatively small to the damage of fin, can optimize the performance of fin formula field effect transistor.
Continuing with reference to figure 6 and Fig. 7, step S4 is performed, with the pseudo- grid 104, side wall 103 and flagpole pattern 102
For mask, ion implanting is carried out to the substrate 100, forms source region, drain region（It does not mark）, the source region, drain region are located at respectively
In the substrate 100 of 103 both sides of the puppet grid 104 and grid curb wall.
With reference to reference to figure 8, Fig. 9, Fig. 9 is the cutaway perspective view of Fig. 8, step S5 is performed, in the substrate 100, the item
Interlayer dielectric layer 106 and carry out chemical mechanical grinding on shape figure 102 and pseudo- grid structure, make interlayer dielectric layer 106 with it is pseudo-
Grid structure flushes, and exposes the upper surface of the pseudo- grid 104.
In the present embodiment, the material of the interlayer dielectric layer 106 is silicon nitride, in other embodiments, the interlayer
The material of dielectric layer 106 can also be silica or other materials different from the pseudo- grid material and substrate material.
With reference to reference to figure 10, Figure 11, Figure 11 is sectional views of the Figure 10 along CC ' lines, performs step S6, removes the pseudo- grid
104, expose multiple flagpole patterns 102 in the hard mask of pseudo- 104 lower section of grid.
In the present embodiment, the material organic antireflective coating material of the pseudo- grid 104, using plasma etching removal
The material is the pseudo- grid 104 of organic antireflective coating material, and in other embodiments, the material of the puppet grid 104 can be with
For materials such as silicon oxide carbide, amorphous carbon.
In other embodiments, wet etching, cineration technics or other dry method can also be used to carve in the pseudo- grid 104 of removal
The etching technique removal pseudo- grid 104.It should be noted that the technique of the pseudo- grid 104 of removal is much larger than the removal rate of pseudo- grid 104
The flagpole pattern 102, the rate of interlayer dielectric layer 106 are removed, to ensure during the pseudo- grid 104 of removal, the item
Shape figure 102, interlayer dielectric layer 106 will not be destroyed.
With reference to reference to figure 12, Figure 13, Figure 13 is sectional views of the Figure 12 along DD ' lines, step S7 is performed, with the inter-level dielectric
Layer 106 and the flagpole pattern 102 are mask, and the substrate 100 is performed etching, and are etching stop layer with oxygen buried layer 101, shape
Into a plurality of fin 202 with certain altitude of corresponding 102 shape of flagpole pattern（Dotted line represents the region of fin）And positioned at fin
Groove between 202（It does not mark）, the height of fin 202 is suitable with the thickness of silicon substrate 100, and the width of fin 202 is the strip
The width of figure 102, the length of a plurality of fin 202 are equal with the width of pseudo- grid 104.
Oxygen buried layer 101 is set to be advantageous in that as etching stop layer, fin 202 in the substrate 100 being achieved in that
Height is average, in other embodiments, can not also set the oxygen buried layer 101.
100 region of substrate that ion is diffused in pseudo- grid structure both sides is respectively formed source region and drain region, because follow-up puppet grid 104
Position can form metal gates, so a plurality of fin 202 is all under the covering of metal gates, the substrate 100 at a plurality of 202 both ends of fin
Whole source/drain region is formd through overdoping, so as to fulfill contact of a plurality of fin 202 with source/drain region.The present embodiment eliminates
Source/drain region engagement pad avoids resistance or parasitic capacitor variations pair caused by source/drain region engagement pad and metal gates are not parallel
The influence of fin formula field effect transistor performance.
With reference to figure 14, Figure 15, it is necessary to which explanation, in order to show the position relationship of fin 202 and metal gates, Figure 14 is fin
The downward projection figure of formula field-effect transistor, Figure 15 are sectional views of the Figure 14 along EE ' lines.Step S8 is performed, removes 202 upper table of fin
The flagpole pattern 102 in face, in the channel bottom and side wall, the upper surface of a plurality of fin 202 and side wall, side wall 103
Gate dielectric layer 109 is formed on side wall.
In the present embodiment, the material of the gate dielectric layer 109 be hafnium, hafnium have thickness it is thinner, leakage
The advantages that electric smaller so that the performance of fin formula field effect transistor is more preferably.In other embodiments, the gate dielectric layer 109
Material can also be amorphous carbon or other materials.
With continued reference to Figure 14, Figure 15, perform step S9, the groove is carried out it is metal filled and to the surface after filling into
Row chemical mechanical grinding so that the metal layer of filling is flushed with 106 surface of interlayer dielectric layer, forms metal gates 108.
Since fin 202 is located in substrate 100, and 100 surface of substrate is not protruded from, metal gates are formed on fin 202
When flatening process is carried out when 108, the flatening process is relatively small to the damage of fin 202, can optimize fin field effect
The performance of transistor.
By above-mentioned technique, three grid structures can be formed（Grid Jie is all covered on the top of fin and two side walls
Matter layer and metal gates）Fin formula field effect transistor.
Due to fin formula field effect transistor of the present invention forming method formed a plurality of fin 202 all in metal gates 108
Under covering, i.e., the width of the length of a plurality of fin 202 with metal gates 108（The width of i.e. pseudo- grid 104）It is equal, the substrate at both ends
100 form the whole source/drain region for being located at 108 both sides of metal gates respectively by ion implanting, naturally by a plurality of fin 202
The source/drain region at both ends forms electrical connection, eliminates the engagement pad that source/drain region is formed to electrical connection in the prior art, avoid because
Source/drain region engagement pad is with metal gates 108 not parallel caused resistance, parasitic capacitor variations to fin formula field effect transistor performance
Influence.
In addition, fin formula field effect transistor forming method of the present invention also provides another embodiment, there is oxidation for being formed
The fin formula field effect transistor of the double-gate structure of graphene gate dielectric layer.The present embodiment and embodiment illustrated in fig. 2 something in common
Repeat no more, the present embodiment and embodiment illustrated in fig. 2 the difference is that：It is further included on the basis of step S1 to S9 following
Step：
Step S10 carries out chemical mechanical grinding, until exposing the upper surface of the fin, so that on fin different lateral
Metal gates separation；
Step S11, removal are located at the gate dielectric layer on the fin side wall, and seam is formed between the fin and metal gates
Gap；
Step S12 forms graphene oxide dielectric layer in the gap.
Gate dielectric layer 109 is a part for the fin formula field effect transistor of three grid structures in embodiment illustrated in fig. 2, and this
In embodiment, the effect of gate dielectric layer 109 is to define the position with graphene oxide gate dielectric layer, in the present embodiment
The material selection amorphous carbon of gate dielectric layer 109 can so be convenient to use cineration technics removal and be located at fin 202 and metal
Gate dielectric layer 109 between grid 108, and it is smaller on being influenced caused by fin 202 and metal gates 108, in other implementations
In example, the material of the gate dielectric layer 109 can also be other materials, the invention is not limited in this regard.
With reference to Figure 16 to Figure 19, the step of to forming the double-gated transistor with graphene oxide gate dielectric layer into
Row is introduced.
Specifically, with reference to reference to figure 16, Figure 17, Figure 17 is Figure 16 along FF ' line profiles, step S10 is performed, to described
Groove carry out it is metal filled after, chemical mechanical grinding is carried out to the surface after filling, until exposing the substrate 100 and described more
The upper surface of fin 202, so that the metal gates 108 on 202 different lateral of fin separate.
Step S11 is performed, cineration technics is used to remove the material as the gate dielectric layer 109 of amorphous carbon, is being removed
Gate dielectric layer 109 forms gap 111 in 109 original position of gate dielectric layer.
Cineration technics is used to be advantageous in that herein smaller on being influenced caused by fin 202 and metal gates 108, but this hair
The bright removal technique to gate dielectric layer 109 is not limited, and dry etching or wet etching can also be used to remove the grid
Dielectric layer 109.
Step S12 is performed, with reference to reference to figure 18, Figure 19, Figure 19 is sectional views of the Figure 18 along GG ' lines, is situated between in removal grid
Graphene oxide dispersion is filled in the gap 111 exposed after matter layer 109, the graphene oxide filled in the gap is disperseed
Liquid is passivated processing, forms graphene oxide layer, removes the graphene oxide layer of 100 surface of the substrate covering, forms position
Graphene oxide dielectric layer 110 on the substrate 100 of the two side of fin and trenched side-wall.
By process above, graphene oxide dielectric layer 110 is all formd on the two side of every fin, graphene oxide is situated between
110 outside of matter layer is metal gates 108.Since the metal gates 108 on 202 top of fin have been removed, form with oxygen
Graphite alkene 110 double grid as gate dielectric layer of dielectric layer（Only in 202 two side walls of fin）Transistor.
Since graphene oxide has good insulating properties and trapped electron ability, the present embodiment fin formula field effect transistor
Gate dielectric layer is used as using graphene oxide, the performance of fin formula field effect transistor can be improved.
And the present embodiment forms graphene oxide dielectric layer and is located in the later step of manufacturing method, with existing fin field
The method of effect transistor has preferable compatibility, reduces technology difficulty.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (12)
1. a kind of forming method of fin formula field effect transistor, which is characterized in that including：
Substrate is provided；
Hard mask is formed over the substrate, and the hard mask has the flagpole pattern for forming fin, the thickness of the hard mask
Degree is less than the height of the fin；
The pseudo- grid structure of the flagpole pattern is developed across over the substrate, and dummy gate structure includes pseudo- grid and positioned at puppet
Side wall on grid side wall；
Using dummy gate structure and hard mask as mask, ion implanting is carried out to the substrate, forms source, drain region；
Source, drain region substrate on formed and the interlayer dielectric layer that flushes of puppet grid structure；
The pseudo- grid are removed, expose the hard mask below pseudo- grid；
Using the interlayer dielectric layer and the hard mask as mask, the substrate is performed etching, form multiple fins and is located at
Multiple grooves between fin；
The hard mask of fin upper surface is removed, in the upper surface of the fin and side wall, the bottom and side wall of the groove and side wall
Side wall forms gate dielectric layer；
It is metal filled to groove progress, to form metal gates；
Chemical mechanical grinding is carried out, until exposing the upper surface of the fin, makes the metal gates being located on fin different lateral separation；
Removal is located at the gate dielectric layer on the fin side wall, and gap is formed between the fin and metal gates；
Graphene oxide dielectric layer is formed in the gap.
2. forming method as described in claim 1, which is characterized in that the step of providing substrate includes：
Oxygen buried layer and the silicon substrate on the oxygen buried layer are provided；
Performing etching the step of forming fin to substrate includes：The silicon substrate is performed etching and using the oxygen buried layer as etching
Stop-layer.
3. forming method as described in claim 1, which is characterized in that the step of forming hard mask on substrate includes：It is serving as a contrast
Multiple flagpole patterns are formed on bottom, are mutually parallel between these flagpole patterns.
4. forming method as described in claim 1, which is characterized in that described hard in the step of forming hard mask on substrate
The material of mask includes the one or more in silicon nitride, silica or silicon oxynitride.
5. forming method as described in claim 1, which is characterized in that described in the step of forming pseudo- grid structure on substrate
Pseudo- grid are formed using spin coating proceeding or chemical vapour deposition technique.
6. forming method as described in claim 1, which is characterized in that described in the step of forming pseudo- grid structure on substrate
The material of pseudo- grid is silicon oxide carbide, one kind in amorphous carbon, organosiloxane.
7. forming method as described in claim 1, which is characterized in that in the step of forming interlayer dielectric layer, the interlayer
The material of dielectric layer includes the one or more in silicon nitride, silica or silicon oxynitride.
8. forming method as described in claim 1, which is characterized in that in the step of removal pseudo- grid, using cineration technics, wet
Method etches or the method for the plasma etching removal pseudo- grid.
9. forming method as described in claim 1, which is characterized in that the material of the gate dielectric layer includes hafnium.
10. forming method as described in claim 1, which is characterized in that graphene oxide dielectric layer is formed in the gap
The step of include：
Graphene oxide dispersion is filled in gap；
Processing is passivated to the graphene oxide dispersion, to form graphene oxide dielectric layer.
11. forming method as described in claim 1, which is characterized in that the material of the gate dielectric layer includes amorphous carbon.
12. forming method as described in claim 1, which is characterized in that the step of removing the gate dielectric layer includes：Using
Wet etching, cineration technics or dry etching remove the gate dielectric layer.
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