CN104601173A - Analog-digital conversion method and relevant analog-digital converter thereof - Google Patents
Analog-digital conversion method and relevant analog-digital converter thereof Download PDFInfo
- Publication number
- CN104601173A CN104601173A CN201310530745.4A CN201310530745A CN104601173A CN 104601173 A CN104601173 A CN 104601173A CN 201310530745 A CN201310530745 A CN 201310530745A CN 104601173 A CN104601173 A CN 104601173A
- Authority
- CN
- China
- Prior art keywords
- voltage
- analog
- reference voltage
- electric capacity
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses an analog-digital conversion method and a relevant analog-digital converter thereof. The conversion method comprises the following steps: charging a capacitor through an analog signal in order to sample the voltage of the analog signal; when the voltage of the capacitor is equal to the voltage of the analog signal, coupling the capacitor and a plurality of reference voltages to a comparator in order to compare the voltage of the capacitor with the plurality of reference voltages and generate a first comparison result; when the state of the first comparison result changes, coupling the capacitor to an oblique wave generator in order to compare an oblique wave signal of the oblique wave generator with a voltage difference and generate a second comparison result; when the state of the second comparison result changes, acquiring a first voltage value of the oblique wave signal; and acquiring a digital code of the analog signal according to the first reference voltage and the first voltage value of the oblique wave signal.
Description
Technical field
The present invention relates to a kind of method and analog-digital converter thereof of Analog-digital Converter, particularly relate to one and utilize Multiple reference voltage and single ramp generator to realize the analog digital conversion method of two stepwises and analog-digital converter thereof.
Background technology
It is fast that image inductor develops into speed goes, and can catch more accurately various material object (such as, visible ray, infrared ray ...) image.Such as, daily life commodity have been become with the handheld camera more than 10M picture element catching 120 figure per second.Similarly, extremely fast (per second 10,000 figure) and super science inductor are accurately to be used for development life science, robot, building etc.In order to the demand in market, constantly improve these images, need to set about from the design of system and technological innovation.Such as, improve speed and inductor quality, the mutual storehouse of multiple integrated circuit, with the succinct imaging device realized.In addition, new sense architecture exploitation, to realize higher reading speed.But this needs the design innovation of analog-digital converter (analog-to-digital converters, ADC), reduce area and power consumption, improve speed and resolution simultaneously.
Along with the progress of integrated circuit manufacture process technology, the figure place of the digital signal that analog-digital converter exports is more and more higher.That is, the value of digital signal representation and the analog signal of input more and more close.Certainly, the figure place raising of digital signal also represents that the circuit complexity of analog-digital converter rises, layout area increases and improves with noise demand of resisting.Following patent document instruction analog-digital converter and relevant method thereof.
U.S. Patent number US20120025062 discloses a kind of hybrid simulation digital quantizer, an image sensor and is used to provide the method for multiple digital code.But realizing described patent needs a large amount of electric capacity must utilize larger pixel inductor.Therefore, the image sensor realizing small size is difficult to.
IEEE file " Multiple-Ramp Column-Parallel ADC Architectures for COMSImage Sensor " discloses a kind of imaging device, it has parallel processing analog digital, and according to according to the single slope analog-digital converter of a multiple oblique wave.Its shortcoming is to need to organize ramp generator more, causes power consumption problem.
European patent number EP1351490 discloses a kind of image sensor improving reading circuit.And U.S. Patent number US6670904 discloses a kind of dual oblique wave analog-digital converter for CMOS (Complementary Metal Oxide Semiconductor).But the implementation of above-mentioned patent is only confined to a linear approach (Linear search).
Summary of the invention
Therefore, namely main purpose of the present invention is the analog digital conversion method of open one, to reach economization electrical source consumption and to shorten change-over time.
The present invention discloses a kind of analog digital conversion method.Described conversion method includes by described analog signal to a capacitor charging, to sample the voltage of described analog signal; When the voltage of described electric capacity equals the voltage of described analog signal, couple described electric capacity and multiple reference voltage to comparator, produce one first comparative result with the voltage of more described electric capacity and described multiple reference voltage; When the state of described first comparative result changes, couple described electric capacity to one ramp generator, produce one second comparative result with the pressure reduction between a ramp signal of more described ramp generator and one first reference voltage of described multiple reference voltage and the voltage of described electric capacity; When the state of described second comparative result changes, obtain one first magnitude of voltage of described ramp signal; And according to described first magnitude of voltage of described first reference voltage and described ramp signal, obtain the described digital code of described analog signal.
The present invention also discloses a kind of analog-digital converter.Described analog-digital converter includes plural parallel processing row, a reference voltage generator and a ramp generator.Described plural parallel processing row are used for inputting multiple analog signal simultaneously.Wherein, each parallel processing row include an electric capacity, one first switch, a second switch and a comparator.Described electric capacity is used for sampling according to an analog signal of described multiple analog signal the voltage of described analog signal.Described first switch is coupled to a first end of described electric capacity, and what be used for controlling described electric capacity couples relation.Described second switch is coupled to one second end of described electric capacity, and what be used for controlling described electric capacity couples relation.Described comparator has that a first input end is coupled to described reference voltage generator, one second input is coupled to each second switch described and an output is used for generation one first comparative result and one second comparative result.Described reference voltage generator is used for producing multiple reference voltage.Described ramp generator is coupled to described first switch, is used for generation one ramp signal.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the embodiment of the present invention one analog-digital converter.
Fig. 2 is a sequential chart of the analog-digital converter 10 of Fig. 1 of the present invention.
Fig. 3 is the schematic diagram of another analog-digital converter of the embodiment of the present invention.
Fig. 4 is the schematic diagram of the embodiment of the present invention one flow process.
Wherein, description of reference numerals is as follows:
10,30 analog-digital converters
100 reference voltage generators
120 ramp generators
130 counters
140 electric capacity
160 comparators
180 logic memory unit
40 flow processs
400,402,404,406,408,410,412 steps
S1, S2 switch
V, V ' voltage
T_V+, T_V-input
Rmp ramp signal
P, Q, N digital code
Vinp_1, Vinp_2 ..., Vinp_n analog signal
Colmn_1, Colmn_2 ..., Colmn_n parallel processing row
Rv_1, rv_2 ..., rv_n, rv_p, rv_p-1 reference voltage
Embodiment
Please refer to Fig. 1, Fig. 1 is the schematic diagram of the embodiment of the present invention one analog-digital converter 10.Analog-digital converter 10 can parallel processing analog signal Vinp_1, Vinp_2 ..., Vinp_n.Analog-digital converter 10 include parallel processing row Colmn_1, Colmn_2 ..., Colmn_n, reference voltage generator 100, ramp generator 120 and a counter 130.Reference voltage generator 100 be used for producing reference voltage rv_1, rv_2 ...., rv_n, with to analog signal Vinp_1, Vinp_2 ..., Vinp_n perform a thick portion compare (coarse conversion).Parallel processing row Colmn_1, Colmn_2 ..., Colmn_n, be used for inputting simultaneously analog signal Vinp_1, Vinp_2 ..., Vinp_n, and the digital code that parallel output is corresponding.Parallel processing row Colmn_1, Colmn_2 ..., Colmn_n each parallel processing row include an electric capacity 140, switch S 1 and S2, comparator 160 and a logic memory unit 180.Electric capacity 140 be used for sampled analog signals Vinp_1, Vinp_2 ..., Vinp_n the voltage of an analog signal.Switch S 1 is coupled to a first end of electric capacity 140, and what be used for control capacitance 140 couples relation.Switch S 2 is coupled to one second end of electric capacity 140, and what be used for control capacitance 140 couples relation.Comparator 160 has a first input end T_V-and is coupled to reference voltage generator 100,1 second input T_V+ and is coupled to switch S 2 and an output and is used for producing comparative result cmpr_1 and comparative result cmpr_2.Ramp generator 120, is coupled to switch S 1, is used for generation one ramp signal Rmp, changes (fine conversion) to perform a thin portion to described analog signal.
For convenience of description, only for parallel processing row colmn_1.When switch S 1 is " 1 " and switch S 2 is " 1 ", one end of electric capacity 140 is coupled to analog signal Vinp_1, the other end ground connection of electric capacity 140, and analog signal Vinp_1 charges to electric capacity 140.When switch S 1 is " 1 " and switch S 2 is " 0 ", electric capacity 140 is coupled to the second input T_V+ of comparator 160, and the first input end T_V-of comparator 160 is coupled to reference voltage generator 100.Now, the voltage of electric capacity 140 is charged to the voltage of analog signal Vinp_1, comparator 160 start to compare the voltage (that is, the voltage of analog signal Vinp_1) of electric capacity 140 and reference voltage rv_1, rv_2 ...., rv_n, and produce comparative result cmpr_1.Comparator 140 can adopt a dichotomy (Binary search) or a linear approach (Linearsearch) compare the voltage of electric capacity 140 and reference voltage rv_1, rv_2 ...., rv_n.During according to dichotomy, logic memory unit 180 also includes an incremental buffer (Successive ApproximateRegister, SAR).Preferably, reference voltage rv_1, rv_2 ...., rv_n can binary mode be ascending increases progressively.If the voltage of electric capacity 140 is when comparatively reference voltage is large, comparative result cmpr_1 is " 1 ".If the voltage of electric capacity 140 comparatively reference voltage hour, comparative result cmpr_1 is " 0 ".When the voltage of one reference voltage rv_p and electric capacity 140 compares, the state of comparative result is changed (from " 0 " to " 1 ").Its representative, the voltage (that is, the voltage of analog signal Vinp_1) of electric capacity 140 is between a reference voltage rv_p-1 and reference voltage rv_p.Because reference voltage rv_p-1 can be represented by a digital code P, analog-digital converter 10 obtains the digital code (that is, higher significance bit (More Significant Bit, MSB)) of thick portion conversion.And the first input end T_V-of comparator 160 is coupled to reference voltage rv_p-1, to perform the conversion of thin portion further.
When performing the conversion of thin portion, switch S 1 switches to " 0 " and switch S 2 switches to " 0 ".Now, electric capacity 140 is coupled to the second input T_V+ and the ramp generator 120 of comparator 160, and the first input end T_V-of comparator 160 is coupled to reference voltage rv_p-1.Comparator 160 starts to compare the voltage (that is, reference voltage rv_p-1) of first input end T_V-and the voltage (that is, the voltage of electric capacity 140 adds ramp signal Rmp) of the second input T_V+.In other words, comparator 160 compares the pressure reduction V between the voltage of ramp signal Rmp and reference voltage rv_p-1 and electric capacity 140, and produces comparative result cmpr_2.Preferably, ramp signal Rmp has a negative slope or a positive slope.Counter 130 is coupled to ramp generator 120, is used for increasing progressively one when ramp signal Rmp often successively decreases/increase progressively (depending on negative slope or positive slope) single order thereupon.When ramp signal Rmp successively decreases/be incremented to magnitude of voltage V ' (the pressure reduction V between the voltage being slightly less than reference voltage rv_p-1 and electric capacity 140), the state of comparative result cmpr_2 changes.For example, the voltage of electric capacity is 0.35 volt, and reference voltage rv_p-1 is 0.30 volt.Comparator 160 comparison reference voltage rv_p-1(0.30 volt) and the voltage (0.35 volt) of electric capacity 140 and the totalling of ramp signal Rmp.Because ramp signal Rmp has negative slope, it makes the voltage of the second input T_V+ of comparator 160 successively decrease from 0.35 volt downwards.When the voltage of the second input T_V+ of comparator 160 is decremented to 0.30 volt that is slightly less than reference voltage rv_p-1 from 0.35 volt, the state of comparative result cmpr_2 changes.
When the state of comparative result cmpr_2 changes, counter 130 exports digital code Q when ramp signal Rmp is magnitude of voltage V ' to logic memory unit 180.Thus, analog-digital converter 10 obtains the digital code (that is, all the other comparatively low orders (Less Significant Bit, LSB)) of thin portion conversion.Analog-digital converter 10 can according to the digital code P(of reference voltage rv_p-1 and voltage V ' namely, higher significance bit) and digital code Q(is namely, all the other are low order comparatively), obtain a digital code N(of analog signal Vinp_1 wherein, N=P+Q).Analog-digital converter 10 needs 2
p+ 2
qchange-over time.In prior art, the analog-digital converter equally with N position then needs 2
nchange-over time.Compare down, the analog-digital converter 10 of the embodiment of the present invention can save change-over time.In addition, a final described digital code can obtain by performing a mathematical operation to higher significance bit (More Significant Bit, MSB) and all the other comparatively low orders (LessSignificant Bit, LSB).
Simple, analog-digital converter 10 utilizes switch S 1 and S2 two of comparator 160 inputs to be coupled to reference voltage generator 100, oblique wave produces device 120 or electric capacity 140, can to analog signal Vinp_1, Vinp_2 ..., Vinp_n is parallel carries out the conversion of thick portion and the conversion of thin portion.In execution thick portion conversion, analog-digital converter 10 can flexibly adopt linear dichotomy or linear approach.In addition, the analog-digital converter of the embodiment of the present invention only needs a ramp generator, therefore not only can save change-over time compared to prior art and also can solve power consumption problem.
Please refer to Fig. 2, Fig. 2 is a sequential chart of analog-digital converter 10.Fig. 2 includes the voltage signal of the voltage signal of switch S 1 and S2, the voltage signal of the first output T_V-of comparator 160, the voltage signal of the second output T_V+ of comparator 160 and the output of comparator 160.The change of the output of comparator 160 as seen from Figure 2.
Please refer to Fig. 3, Fig. 3 is the schematic diagram of another analog-digital converter 30 of the embodiment of the present invention.The basic framework of analog-digital converter 30 and analog-digital converter 10 and similar, therefore same components and signal continue to use identical label.Analog-digital converter 30 and the difference of analog-digital converter 10 are only that electric capacity 140 and switch S 1 and S2's couples position.When switch S 1 switches to " 0 " and switch S 2 switches to " 0 ", electric capacity 140 is coupled to first input end T_V-and the reference voltage rv_p-1 of comparator 160, and the second input T_V+ of comparator 160 is coupled to ramp generator 120.Comparator 160 compares the pressure reduction V between the voltage of ramp signal Rmp and reference voltage rv_p-1 and electric capacity 140, and produces comparative result cmpr_2.All the other operating procedures with reference to above-mentioned, can not repeat them here.
Please refer to Fig. 4, the operating procedure about analog-digital converter 10 can be summarized as a flow process 40.Flow process 40, in analog-digital converter 10, is used for conversion one analog signal to digital code.Flow process 40 comprises the following step:
Step 400: start.
Step 402: by analog signal Vinp_1, Vinp_2 ..., Vinp_n charges to electric capacity 140, with sampled analog signals Vinp_1, Vinp_2 ..., Vinp_n voltage.
Step 404: the voltage of electric capacity 140 equal analog signal Vinp_1, Vinp_2 ..., Vinp_n voltage time, coupling capacitance 140 and reference voltage rv_1, rv_2 ...., rv_n is to comparator 160, with compare the voltage of electric capacity 140 and reference voltage rv_1, rv_2 ...., rv_n, and produce comparative result cmpr_1.
Step 406: when the state of comparative result cmpr_1 changes, coupling capacitance 140 to ramp generator 120, with the pressure reduction V between the voltage comparing ramp signal Rmp and reference voltage rv_p-1 and electric capacity 140, and produces comparative result cmpr_2.
Step 408: when the state of comparative result cmpr_2 changes, obtain the magnitude of voltage V ' of ramp signal Rmp.
Step 410: according to reference voltage rv_p-1 and magnitude of voltage V ', parallel obtain analog signal Vinp_1, Vinp_2 ..., Vinp_n digital code.
Step 412: terminate.
The detailed embodiment of flow process 40 with reference to above-mentioned, can not repeat at this.
In sum, the ratio digital quantizer of the embodiment of the present invention utilizes switch that two of comparator inputs are coupled to reference voltage generator, ramp generator or electric capacity, the conversion of thick portion and the conversion of thin portion can be carried out to analog signal is parallel, therefore can save simulation to digital change-over time.In addition, the analog-digital converter of the embodiment of the present invention only needs a ramp generator, therefore also can solve the power consumption problem of prior art.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (18)
1. an analog digital conversion method, described conversion method includes:
By an analog signal to a capacitor charging, to sample the voltage of described analog signal;
When the voltage of described electric capacity equals the voltage of described analog signal, couple described electric capacity and multiple reference voltage to comparator, produce one first comparative result with the voltage of more described electric capacity and described multiple reference voltage;
When the state of described first comparative result changes, couple described electric capacity to one ramp generator, produce one second comparative result with the pressure reduction between a ramp signal of more described ramp generator and one first reference voltage of described multiple reference voltage and the voltage of described electric capacity;
When the state of described second comparative result changes, obtain one first magnitude of voltage of described ramp signal; And
According to described first magnitude of voltage of described first reference voltage and described ramp signal, obtain a digital code of described analog signal.
2. conversion method as claimed in claim 1, is characterized in that the voltage of more described electric capacity and described multiple reference voltage are the voltage of employing one dichotomy or the more described electric capacity of a linear approach and described multiple reference voltage.
3. conversion method as claimed in claim 1, is characterized in that the state of described first comparative result changes when the voltage of described electric capacity compares with one second reference voltage of multiple reference voltage.
4. conversion method as claimed in claim 3, is characterized in that described analog signal is between described first reference voltage and described second reference voltage.
5. conversion method as claimed in claim 3, it is characterized in that one of described digital code high significance bit can be obtained by described first reference voltage, and all the other low orders of described digital code can be obtained by described first magnitude of voltage of described ramp signal.
6. conversion method as claimed in claim 1, is characterized in that described ramp signal has a plus or minus slope.
7. conversion method as claimed in claim 6, is characterized in that described ramp signal often successively decreases or increases progressively single order and makes a numerical value of a counter increase progressively one thereupon.
8. an analog-digital converter, is used for the multiple analog signal of parallel processing, and described analog-digital converter includes:
One reference voltage generator, is used for producing multiple reference voltage;
Plural number parallel processing row, are used for inputting described multiple analog signal simultaneously, and wherein each parallel processing row include:
One electric capacity, is used for sampling according to an analog signal of described multiple analog signal the voltage of described analog signal;
One first switch, is coupled to a first end of described electric capacity, and what be used for controlling described electric capacity couples relation;
One second switch, is coupled to one second end of described electric capacity, and what be used for controlling described electric capacity couples relation; And
One comparator, has that a first input end is coupled to described reference voltage generator, one second input is coupled to each second switch described and an output, and wherein said output is used for generation one first comparative result and one second comparative result; And
One ramp generator, is coupled to described first switch, is used for generation one ramp signal.
9. analog-digital converter as claimed in claim 8, is characterized in that when described electric capacity is coupled to described comparator by described second switch, and the voltage of the more described electric capacity of described comparator and described multiple reference voltage also produce described first comparative result.
10. analog-digital converter as claimed in claim 9, is characterized in that described comparator adopts the voltage of a dichotomy or the more described electric capacity of a linear approach and described multiple reference voltage.
11. analog-digital converters as claimed in claim 9, it is characterized in that when described first comparative result change, described ramp generator is coupled to described comparator by described first switch, and the pressure reduction between one first reference voltage of the more described ramp signal of described comparator and described multiple reference voltage and the voltage of described electric capacity also produces described second comparative result.
12. analog-digital converters as claimed in claim 11, is characterized in that the state of described first comparative result changes when the voltage of described electric capacity compares with one second reference voltage of multiple reference voltage.
13. analog-digital converters as claimed in claim 12, is characterized in that described analog signal is between described first reference voltage and described second reference voltage.
14. analog-digital converters as claimed in claim 8, it also comprises a logic memory unit, and one first magnitude of voltage be used for according to described first reference voltage and described ramp signal, obtains a digital code of described analog signal.
15. analog-digital converters as claimed in claim 14, is characterized in that one of described digital code high significance bit can be obtained by described first reference voltage, and all the other low orders of described digital code can be obtained by one first magnitude of voltage of described ramp signal.
16. analog-digital converters as claimed in claim 8, is characterized in that described ramp signal has a negative slope.
17. analog-digital converters as claimed in claim 16, it also comprises a counter, is coupled to described ramp generator, is used for increasing progressively one when described ramp signal often successively decreases or increase progressively single order thereupon.
18. analog-digital converters as claimed in claim 15, it is characterized in that a final described digital code be to higher significance bit and all the other comparatively low order perform a mathematical operation and obtain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310530745.4A CN104601173B (en) | 2013-10-30 | 2013-10-30 | The conversion method of simulation numeral and its associated analog digital quantizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310530745.4A CN104601173B (en) | 2013-10-30 | 2013-10-30 | The conversion method of simulation numeral and its associated analog digital quantizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104601173A true CN104601173A (en) | 2015-05-06 |
| CN104601173B CN104601173B (en) | 2018-06-05 |
Family
ID=53126730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310530745.4A Active CN104601173B (en) | 2013-10-30 | 2013-10-30 | The conversion method of simulation numeral and its associated analog digital quantizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104601173B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109714057A (en) * | 2018-12-26 | 2019-05-03 | 北京华大九天软件有限公司 | A kind of dynamic digital and analogue signals transformation model and modeling method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102209210A (en) * | 2010-03-30 | 2011-10-05 | 索尼公司 | Solid-state image pickup apparatus, signal processing method for the solid-state image pickup apparatus and electronic apparatus |
| US20120025062A1 (en) * | 2010-08-02 | 2012-02-02 | Harald Neubauer | Hybrid analog-to-digital converter, an image sensor and a method for providing a plurality of digital signals |
| CN102572325A (en) * | 2010-11-09 | 2012-07-11 | 三星电子株式会社 | Analog to digital converters, image sensor systems, and methods of operating the same |
-
2013
- 2013-10-30 CN CN201310530745.4A patent/CN104601173B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102209210A (en) * | 2010-03-30 | 2011-10-05 | 索尼公司 | Solid-state image pickup apparatus, signal processing method for the solid-state image pickup apparatus and electronic apparatus |
| US20120025062A1 (en) * | 2010-08-02 | 2012-02-02 | Harald Neubauer | Hybrid analog-to-digital converter, an image sensor and a method for providing a plurality of digital signals |
| CN102572325A (en) * | 2010-11-09 | 2012-07-11 | 三星电子株式会社 | Analog to digital converters, image sensor systems, and methods of operating the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109714057A (en) * | 2018-12-26 | 2019-05-03 | 北京华大九天软件有限公司 | A kind of dynamic digital and analogue signals transformation model and modeling method |
| CN109714057B (en) * | 2018-12-26 | 2020-04-07 | 北京华大九天软件有限公司 | Dynamic digital-to-analog signal conversion model and modeling method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104601173B (en) | 2018-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105322964B (en) | Method and circuit for noise shaping SAR analog-digital converter | |
| Cho et al. | A 9-bit 80 MS/s successive approximation register analog-to-digital converter with a capacitor reduction technique | |
| CN100527632C (en) | Analogue to digital converter | |
| WO2017006297A2 (en) | Hybrid charge-sharing charge-redistribution dac for successive approximation analog-to-digital converters | |
| CN102111156B (en) | Successive approximation register analog-to-digital conversion circuit for realizing minimal dynamic range | |
| CN103916127A (en) | Analog/digital converter | |
| US10778242B2 (en) | Analog-to-digital converter device | |
| CN108781082B (en) | Analog-to-digital conversion circuit, image sensor, and analog-to-digital conversion method | |
| CN102386923A (en) | Asynchronous successive approximation analog-to-digital converter and conversion method | |
| TWI532328B (en) | Analog to digital converter and converting method thereof | |
| US20140002291A1 (en) | Analog to digital conversion architecture and method with input and reference voltage scaling | |
| CN102055475B (en) | Successive approximation analog-digital converter and method thereof | |
| US9007252B1 (en) | Analog to digital conversion method and related analog to digital converter | |
| CN106656190B (en) | Successive approximation type analog-digital conversion circuit and method thereof | |
| EP2629426A1 (en) | Device, system and method for analogue-to-digital conversion with noise shaping function | |
| CN104143983B (en) | Continuous Approximation formula analog-digital converter and its method | |
| CN104601173A (en) | Analog-digital conversion method and relevant analog-digital converter thereof | |
| Kuo et al. | An 18.39 fJ/conversion-step 1-MS/s 12-bit SAR ADC with non-binary multiple-LSB-redundant and non-integer-and-split-capacitor DAC | |
| WO2013015672A1 (en) | Low power high resolution analogue to digital converter and method thereof | |
| CN112994699B (en) | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method | |
| CN116567446A (en) | Single slope analog-to-digital converter, readout circuit, image sensor and quantization method | |
| CN111435835B (en) | Switched capacitor circuit and analog-to-digital conversion device | |
| CN109792499B (en) | Analog-to-digital conversion circuit, image sensor, and analog-to-digital conversion method | |
| CN112398472B (en) | Error quantization 10-bit monoclinic ADC for image sensor | |
| CN102281069A (en) | Analog-to-digital conversion circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |