CN104600042A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN104600042A CN104600042A CN201410826987.2A CN201410826987A CN104600042A CN 104600042 A CN104600042 A CN 104600042A CN 201410826987 A CN201410826987 A CN 201410826987A CN 104600042 A CN104600042 A CN 104600042A
- Authority
- CN
- China
- Prior art keywords
- chip
- semiconductor device
- insulating barrier
- conducting layer
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor device. The semiconductor device comprises a conductor frame composed of at least one chip and at least three pins, at least one first chip positioned on the chip seat, a chip combining material positioned between the first chip and the chip seat, a conductor for connecting the first chip with the pins, a first insulation layer which is positioned below the conductor frame and above the first chip, a heat conducting layer positioned below the first insulation layer, and a packaging material for packaging the conductor frame, the first chip, the conductor, the first insulation layer and the heat conducting layer; the lower surface of the heat conducting layer exposes from the outside; the pins extend out from the packaging materials. According to the semiconductor, the first insulating layer and the heat conducting layer are added below the conductor frame; in addition, the lower surface of the heat conducting layer exposes from the outside after packaging, so that the heat generated by the semiconductor device can be timely discharged, and as a result, the performance of the semiconductor device can be improved; in addition, the reliability of the semiconductor device can be improved, and the service life of the semiconductor device can be prolonged.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of semiconductor device.
Background technology
Along with the continuous progress of semiconductor technology, more and more higher to the power requirement of semiconductor device.The high power of semiconductor device must cause and produces a large amount of heats, if a large amount of heat produced can not discharge in time, will certainly affect the performance of semiconductor device, and greatly can reduce the life and reliability of semiconductor device.Therefore, the heat dissipation problem of high power semiconductor device is vital problem.The encapsulating material of existing semiconductor device has poor thermal diffusivity, and a large amount of heat that high power semiconductor device is produced can not discharge in time, has had a strong impact on the performance of semiconductor device.
Summary of the invention
The present invention completes to solve above-mentioned deficiency of the prior art, and the object of the invention is to propose a kind of semiconductor device, this semiconductor device can solve the problem of existing semiconductor device poor radiation.
For reaching this object, the present invention by the following technical solutions:
A kind of semiconductor device, comprising:
Lead frame, described lead frame comprises at least one chip carrier and at least three pins;
At least one first chip, described first chip is positioned on described chip carrier;
Chip in conjunction with material, described chip in conjunction with material between described first chip and described chip carrier;
Wire, described wire is for connecting described first chip and described pin;
First insulating barrier, described first insulating barrier is positioned under described lead frame, and is positioned at the below of described first chip;
Heat-conducting layer, described heat-conducting layer is positioned under described first insulating barrier;
Encapsulating material, described lead frame, described first chip, described wire, described first insulating barrier and described heat-conducting layer are encapsulated by described encapsulating material, and the naked leakage of the lower surface of described heat-conducting layer outside, and described pin stretches out outside described encapsulating material.
Further, described first insulating layer material is aluminium oxide, aluminium nitride or epoxy resin, and described heat-conducting layer material is copper or aluminium.
Further, described first insulating barrier is made up of multiple first collets or is one deck.
Further, described first insulating layer material be aluminium oxide or aluminium nitride time, also comprise:
Second insulating barrier, described second insulating barrier is positioned under described heat-conducting layer, and described second insulating barrier is encapsulated within described encapsulating material, and the naked leakage of lower surface of described second insulating barrier outside.
Further, described second insulating layer material is aluminium oxide or aluminium nitride.
Further, also comprise:
Printed circuit board (PCB), described printed circuit board (PCB) is welded with at least one second chip and at least one solder joint, described wire is also for connecting described second chip and described solder joint, described solder joint and described first chip, described solder joint and described pin, and described printed circuit board (PCB), described second chip and described solder joint are encapsulated within described encapsulating material.
Further, described printed circuit board (PCB) is welded with at least one electric capacity, described wire is also for connecting described second chip and described electric capacity, described electric capacity and described solder joint, and described electric capacity is encapsulated within described encapsulating material.
Semiconductor device of the present invention by increasing the first insulating barrier and heat-conducting layer under lead frame, and the naked leakage of lower surface of the rear heat-conducting layer of encapsulation outside, the heat that semiconductor device is produced can discharge in time, improve the performance of semiconductor device, and then improve the reliability of semiconductor device, extend the life-span of semiconductor device.
Accompanying drawing explanation
In order to the technical scheme of exemplary embodiment of the present is clearly described, one is done to the accompanying drawing used required for describing in embodiment below and simply introduce.Obviously, the accompanying drawing introduced is the accompanying drawing of a part of embodiment that the present invention will describe, instead of whole accompanying drawings, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structure chart of the semiconductor device that the embodiment of the present invention one provides.
Fig. 2 is the structure chart of the semiconductor device that the embodiment of the present invention two provides.
Fig. 3 is the structure chart of the semiconductor device that the embodiment of the present invention three provides.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below with reference to the accompanying drawing in the embodiment of the present invention, by embodiment, technical scheme of the present invention is intactly described.Obviously; described embodiment is a part of embodiment of the present invention, instead of whole embodiments, based on embodiments of the invention; the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all falls within protection scope of the present invention.
Embodiment one:
Fig. 1 is the structure chart of the semiconductor device that the embodiment of the present invention one provides.As shown in Figure 1, this semiconductor device comprises:
Lead frame 101, lead frame comprises chip carrier 111 and pin one 21.
In the present embodiment, chip carrier has one at least, for chip placement.Pin has three at least, for source electrode, drain and gate as the semiconductor device after encapsulation.
First chip 102, is positioned on chip carrier 111.
In the present embodiment, the first chip has one at least, is positioned on chip carrier, and each chip carrier places a chip.
Chip in conjunction with material 103, between the first chip 102 and chip carrier 101.
In the present embodiment, the first chip is fixed on chip carrier in conjunction with material by chip.Chip can be conducting resinl or solder(ing) paste in conjunction with material.
Wire 104, for connecting the first chip 102 and pin one 21.
In the present embodiment, wire couples together using the grid of the first chip with as the pin of the grid of the semiconductor device after encapsulation; Couple together using the source electrode of the first chip with as the pin of the source electrode of the semiconductor device after encapsulation.When the quantity of chip is no less than two, wire is also for coupling together different chips.
First insulating barrier 105, is positioned under lead frame 101, and is positioned at the below of the first chip 102.
In the present embodiment, the material of the first insulating barrier can be aluminium oxide, aluminium nitride or epoxy resin.First insulating barrier is made up of multiple first collets, forms multiple small boss.This small boss can be prepared from by carrying out once pre-injection moulding before injection mo(u)lding.
Heat-conducting layer 106, is positioned under the first insulating barrier 105.
In the present embodiment, heat-conducting layer material can be copper or aluminium.
Encapsulating material 107, lead frame 101, first chip 102, wire 104, first insulating barrier 105 and heat-conducting layer 106 are encapsulated, and the naked leakage of the lower surface of heat-conducting layer 106 outside, pin one 21 stretches out outside encapsulating material.
In the present embodiment, encapsulating material can be epoxy resin.
Preferably, this semiconductor device also comprises:
Printed circuit board (PCB) 108, printed circuit board (PCB) 108 is welded with at least one second chip 118 and at least one solder joint 128.
In the present embodiment, use printed circuit board (PCB) can by multiple integrated chip in this semiconductor device, and the volume of the semiconductor device of preparation can be less.
Wherein, wire 104 is also for connecting the second chip 118 and solder joint 128, solder joint 128 and the first chip 102, solder joint 128 and pin one 21, and printed circuit board (PCB) 108, second chip 118 and solder joint 128 are encapsulated within encapsulating material 107.
Preferably, printed circuit board (PCB) 108 is welded with at least one electric capacity 138.
In the present embodiment, wire 104 is also for connecting the second chip 118 and electric capacity 138, electric capacity 138 and solder joint 128, and electric capacity 138 is encapsulated within encapsulating material 107.
The semiconductor device that the embodiment of the present invention one provides by increasing the first insulating barrier and heat-conducting layer under lead frame, and the naked leakage of lower surface of the rear heat-conducting layer of encapsulation outside, the heat that semiconductor device is produced can discharge in time, improve the performance of semiconductor device, and then improve the reliability of semiconductor device, extend the life-span of semiconductor device, and lead frame and heat-conducting layer insulate by the first insulating barrier, and then lead frame and the external radiator of heat-conducting layer are insulated, do not affect normal use, namely this semiconductor device is while guaranteeing that thermal diffusivity is good, achieve electric insulation again.
Embodiment two:
Fig. 2 is the structure chart of the semiconductor device that the embodiment of the present invention two provides.As shown in Figure 2, compared with the semiconductor device provided with the embodiment of the present invention one, the first insulating barrier 105 of the semiconductor device that the embodiment of the present invention two provides is the structure of complete one deck.
Compared with the semiconductor device provided with the embodiment of the present invention one, the semiconductor device that the embodiment of the present invention two provides is by being prepared into complete one deck by the first insulating barrier, the contact area of the first insulating barrier and lead frame is increased, improves the heat dispersion of semiconductor device.
Embodiment three:
Fig. 3 is the structure chart of the semiconductor device that the embodiment of the present invention three provides.As shown in Figure 3, compared with the semiconductor device provided with the embodiment of the present invention two, the material of the first insulating barrier 105 of the semiconductor device that the embodiment of the present invention three provides be aluminium oxide or aluminium nitride time, this semiconductor device also comprises:
Second insulating barrier 109, is positioned under heat-conducting layer 106, is encapsulated within encapsulating material 107, and the naked leakage of lower surface of the second insulating barrier 109 outside.
In the present embodiment, the material of the second insulating barrier can be aluminium oxide or aluminium nitride.
Compared with the embodiment of the present invention two, the semiconductor device that the embodiment of the present invention three provides, by introducing the second insulating barrier below heat-conducting layer, adds the insulation effect of semiconductor device.
The know-why that above are only preferred embodiment of the present invention and use.The invention is not restricted to specific embodiment described here, the various significant changes can carried out for a person skilled in the art, readjust and substitute all can not depart from protection scope of the present invention.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by the scope of claim.
Claims (7)
1. a semiconductor device, is characterized in that, comprising:
Lead frame, described lead frame comprises at least one chip carrier and at least three pins;
At least one first chip, described first chip is positioned on described chip carrier;
Chip in conjunction with material, described chip in conjunction with material between described first chip and described chip carrier;
Wire, described wire is for connecting described first chip and described pin;
First insulating barrier, described first insulating barrier is positioned under described lead frame, and is positioned at the below of described first chip;
Heat-conducting layer, described heat-conducting layer is positioned under described first insulating barrier;
Encapsulating material, described lead frame, described first chip, described wire, described first insulating barrier and described heat-conducting layer are encapsulated by described encapsulating material, and the naked leakage of the lower surface of described heat-conducting layer outside, and described pin stretches out outside described encapsulating material.
2. semiconductor device according to claim 1, is characterized in that, described first insulating layer material is aluminium oxide, aluminium nitride or epoxy resin, and described heat-conducting layer material is copper or aluminium.
3. semiconductor device according to claim 2, is characterized in that, described first insulating barrier is made up of multiple first collets or is one deck.
4. semiconductor device according to claim 3, is characterized in that, described first insulating layer material be aluminium oxide or aluminium nitride time, also comprise:
Second insulating barrier, described second insulating barrier is positioned under described heat-conducting layer, and described second insulating barrier is encapsulated within described encapsulating material, and the naked leakage of lower surface of described second insulating barrier outside.
5. semiconductor device according to claim 4, is characterized in that, described second insulating layer material is aluminium oxide or aluminium nitride.
6., according to the arbitrary described semiconductor device of claim 1-5, it is characterized in that, also comprise:
Printed circuit board (PCB), described printed circuit board (PCB) is welded with at least one second chip and at least one solder joint, described wire is also for connecting described second chip and described solder joint, described solder joint and described first chip, described solder joint and described pin, and described printed circuit board (PCB), described second chip and described solder joint are encapsulated within described encapsulating material.
7. semiconductor device according to claim 6, it is characterized in that, described printed circuit board (PCB) is welded with at least one electric capacity, described wire is also for connecting described second chip and described electric capacity, described electric capacity and described solder joint, and described electric capacity is encapsulated within described encapsulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410826987.2A CN104600042A (en) | 2014-12-25 | 2014-12-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410826987.2A CN104600042A (en) | 2014-12-25 | 2014-12-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104600042A true CN104600042A (en) | 2015-05-06 |
Family
ID=53125720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410826987.2A Pending CN104600042A (en) | 2014-12-25 | 2014-12-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104600042A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116759397A (en) * | 2023-08-16 | 2023-09-15 | 长电集成电路(绍兴)有限公司 | Chip packaging structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100181628A1 (en) * | 2009-01-22 | 2010-07-22 | Renesas Technology Corp. | Semiconductor device |
| CN202487568U (en) * | 2011-12-28 | 2012-10-10 | 三垦电气株式会社 | Semiconductor module |
| CN202816907U (en) * | 2012-08-31 | 2013-03-20 | 杰群电子科技（东莞）有限公司 | Semiconductor chip |
-
2014
- 2014-12-25 CN CN201410826987.2A patent/CN104600042A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100181628A1 (en) * | 2009-01-22 | 2010-07-22 | Renesas Technology Corp. | Semiconductor device |
| CN202487568U (en) * | 2011-12-28 | 2012-10-10 | 三垦电气株式会社 | Semiconductor module |
| CN202816907U (en) * | 2012-08-31 | 2013-03-20 | 杰群电子科技（东莞）有限公司 | Semiconductor chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116759397A (en) * | 2023-08-16 | 2023-09-15 | 长电集成电路(绍兴)有限公司 | Chip packaging structure and preparation method thereof |
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| EXSB | Decision made by sipo to initiate substantive examination | ||
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| RJ01 | Rejection of invention patent application after publication | ||
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Application publication date: 20150506 |