CN104599987A - Semiconductor wafer-level packaging technique - Google Patents
Semiconductor wafer-level packaging technique Download PDFInfo
- Publication number
- CN104599987A CN104599987A CN201410800045.7A CN201410800045A CN104599987A CN 104599987 A CN104599987 A CN 104599987A CN 201410800045 A CN201410800045 A CN 201410800045A CN 104599987 A CN104599987 A CN 104599987A
- Authority
- CN
- China
- Prior art keywords
- welding position
- semiconductor wafer
- level packaging
- wiring layer
- dry film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention relates to a semiconductor wafer-level packaging technique. The semiconductor wafer-level packaging technique comprises the steps: forming a resin layer at a non-welding position on a re-wiring layer; filling welding flux at the welding position of the re-wiring layer; implanting a welded ball at the welding position. The semiconductor wafer-level packaging technique of the invention can be applied to prevent crack between the welded ball and the re-wiring layer, thereby avoiding the failure of a semiconductor device.
Description
Technical field
The present invention relates to a kind of encapsulation technology of semiconductor, particularly a kind of semiconductor wafer level packaging technology.
Background technology
For realizing the mechanical high reliability of wafer level packaging at large size chip, more product starts the structure adopting double layer of metal and two layers of dielectric layer to connect, thus connection metal solder ball terminals and chip surface electrode.
Fig. 1 is existing semiconductor device wafer-level package structure.Semiconductor chip 1 has electrode 2, dielectric layer 3,4 is formed by coating photoetching process, the mode of electrolytics plating forms wiring layer 5 and layers of copper electrode 6 again, is finally connected by welding to be formed with metal solder ball terminals 7, forms the semiconductor device wafer-level package structure shown in Fig. 1.
But, although this semiconductor device chip scale package structure have employed the structure of two layers of dielectric layer, add Mechanical Reliability to a certain extent, but the intermetallic compound that its layers of copper electrode and metal welding bulb are formed easily cracks because of stressed, causes component failure.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
A main purpose of the present invention is to provide a kind of new semiconductor wafer level packaging technology, can prevent soldered ball and form crackle between wiring layer again, thus avoiding the inefficacy of semiconductor device.
According to an aspect of the present invention, a kind of semiconductor wafer level packaging technology, comprising:
Non-solder position on wiring layer again forms resin bed;
Solder is filled in the welding position of wiring layer again;
Soldered ball is implanted in described welding position.
Adopt semiconductor wafer level packaging technology of the present invention, make the performance of semiconductor device more reliable and more stable.
Accompanying drawing explanation
Below with reference to the accompanying drawings illustrate embodiments of the invention, above and other objects, features and advantages of the present invention can be understood more easily.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characteristic or parts will adopt same or similar Reference numeral to represent.
Fig. 1 is the schematic diagram of existing semiconductor wafer class encapsulation structure;
Fig. 2 is the flow chart of a kind of execution mode of semiconductor wafer level packaging technology of the present invention;
Fig. 3 is the structure chart of a kind of execution mode of the semiconductor wafer class encapsulation structure that semiconductor wafer level packaging technology processing according to the present invention generates.
Embodiment
With reference to the accompanying drawings embodiments of the invention are described.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.
Shown in Figure 2, be the flow chart of a kind of execution mode of semiconductor wafer level packaging technology of the present invention.
In the present embodiment, semiconductor wafer level packaging technology comprises the steps:
S10: the non-solder position on wiring layer again forms resin bed;
S20: fill solder in the welding position of wiring layer again;
S30: implant soldered ball in welding position.
Owing to having resin bed around soldered ball, make soldered ball and the connection again between wiring layer more solid and reliable, reduce soldered ball and between wiring layer, form the possibility in crack again.
As a kind of execution mode, step S10 wherein can specifically comprise:
S11: paste dry film at the upper surface of wiring layer again;
S12: graph exposure development is carried out to dry film and forms dry film figure;
S13: carry out resin printing and form resin bed on wiring layer again, and resin bed covers dry film figure;
S14: predetermined value is reached to the thinning residual altitude of dry film figure that makes of resin bed;
S15: peel off remaining dry film and make stripping place formation welding position.
As a kind of preferred version, after the step s 15, semiconductor wafer level packaging technology of the present invention can also comprise:
S16 cleans described welding position.Such as, heating and/or Ion Cleaning method can be adopted to clean described welding position.When adopting particle cleaning, nitrogen (N2) can be adopted to clean.
In one embodiment, step S30 can specifically comprise:
S31: soldered ball is placed on solder;
And,
S32: adopt Reflow Soldering that soldered ball is fixed on welding position.
Shown in Figure 3, be the structure chart of a kind of execution mode of the semiconductor wafer class encapsulation structure of semiconductor wafer level packaging technology processing generation according to the present invention.
This semiconductor wafer class encapsulation structure comprises chip 101, pad 102 from bottom to top, and is formed in passivation layer 103 on pad, splash-proofing sputtering metal layer 104 and wiring layer 105 again.Wiring layer 105 is again formed with resin bed 106.In addition, in the weld part formed on the resin layer, soldered ball 107 and wiring layer is again had to be welded and fixed.
Adopt semiconductor wafer level packaging technology of the present invention, soldered ball can be prevented and form crackle between wiring layer again, thus avoiding the inefficacy of semiconductor device.
In equipment of the present invention and method, obviously, each parts or each step reconfigure after can decomposing, combine and/or decomposing.These decompose and/or reconfigure and should be considered as equivalents of the present invention.Also it is pointed out that the step performing above-mentioned series of processes can order naturally following the instructions perform in chronological order, but do not need necessarily to perform according to time sequencing.Some step can walk abreast or perform independently of one another.Simultaneously, above in the description of the specific embodiment of the invention, the feature described for a kind of execution mode and/or illustrate can use in one or more other execution mode in same or similar mode, combined with the feature in other execution mode, or substitute the feature in other execution mode.
Should emphasize, term " comprises/comprises " existence referring to feature, key element, step or assembly when using herein, but does not get rid of the existence or additional of one or more further feature, key element, step or assembly.
Although described the present invention and advantage thereof in detail, be to be understood that and can have carried out various change when not exceeding the spirit and scope of the present invention limited by appended claim, substituting and conversion.And the scope of the application is not limited only to the specific embodiment of process, equipment, means, method and step described by specification.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use perform the function substantially identical with corresponding embodiment described herein or obtain and its substantially identical result, existing and that will be developed in the future process, equipment, means, method or step according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (5)
1. a semiconductor wafer level packaging technology, is characterized in that, comprising:
Non-solder position on wiring layer again forms resin bed;
Solder is filled in the welding position of wiring layer again;
Soldered ball is implanted in described welding position.
2. semiconductor wafer level packaging technology according to claim 1, is characterized in that, described, and " the non-solder position on wiring layer again forms resin bed " specifically comprises:
Dry film is pasted at the upper surface of wiring layer again;
Graph exposure development is carried out to described dry film and forms dry film figure;
Described wiring layer again carries out resin printing and forms resin bed, and described resin bed covers described dry film figure;
Predetermined value is reached to the thinning residual altitude of described dry film figure that makes of described resin bed;
Peel off remaining described dry film and make stripping place formation welding position.
3. semiconductor wafer level packaging technology according to claim 2, is characterized in that, after described " peel off remaining described dry film and make stripping place formation welding position ", also comprises:
Described welding position is cleaned.
4. semiconductor wafer level packaging technology according to claim 3, is characterized in that, described " cleaning described welding position " specifically comprises:
Heating and/or Ion Cleaning method is adopted to clean described welding position.
5. the semiconductor wafer level packaging technology according to claim 1-4 any one, is characterized in that, described " implanting soldered ball in described welding position " specifically comprises:
Soldered ball is placed on described solder;
And,
Adopt Reflow Soldering that described soldered ball is fixed on described welding position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410800045.7A CN104599987A (en) | 2014-12-19 | 2014-12-19 | Semiconductor wafer-level packaging technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410800045.7A CN104599987A (en) | 2014-12-19 | 2014-12-19 | Semiconductor wafer-level packaging technique |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104599987A true CN104599987A (en) | 2015-05-06 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410800045.7A Pending CN104599987A (en) | 2014-12-19 | 2014-12-19 | Semiconductor wafer-level packaging technique |
Country Status (1)
| Country | Link |
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| CN (1) | CN104599987A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1929124A (en) * | 2005-09-06 | 2007-03-14 | 株式会社瑞萨科技 | Semiconductor device and manufacturing method thereof |
| CN101170072A (en) * | 2006-10-24 | 2008-04-30 | 新光电气工业株式会社 | Semiconductor device and manufacturing method thereof |
| CN102157477A (en) * | 2011-03-23 | 2011-08-17 | 南通富士通微电子股份有限公司 | Method for manufacturing semiconductor device |
| CN103858527A (en) * | 2011-10-11 | 2014-06-11 | 日立化成株式会社 | Structure containing conductor circuit, method for manufacturing same, and heat-curable resin composition |
-
2014
- 2014-12-19 CN CN201410800045.7A patent/CN104599987A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1929124A (en) * | 2005-09-06 | 2007-03-14 | 株式会社瑞萨科技 | Semiconductor device and manufacturing method thereof |
| CN101170072A (en) * | 2006-10-24 | 2008-04-30 | 新光电气工业株式会社 | Semiconductor device and manufacturing method thereof |
| CN102157477A (en) * | 2011-03-23 | 2011-08-17 | 南通富士通微电子股份有限公司 | Method for manufacturing semiconductor device |
| CN103858527A (en) * | 2011-10-11 | 2014-06-11 | 日立化成株式会社 | Structure containing conductor circuit, method for manufacturing same, and heat-curable resin composition |
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| C06 | Publication | ||
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| CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150506 |