Summary of the invention
The invention provides a kind of super-radiance light emitting diode temperature-control circuit, to solve in laser instrument temperature control field, traditional TEC opertaing device cannot meet the needs of laser instrument to temperature susceplibility.
The present invention, for solving the problem and a kind of super-radiance light emitting diode temperature-control circuit provided, comprising:
Temperature survey amplifier module, PID compensate amplification module, thermal module, voltage module, oscillator module, parameter module, Pulse width modulation module and field effect control module;
Wherein, described temperature survey amplifier module and described PID are compensated amplification module and are connected by corresponding pin, to realize the control of described temperature survey amplifier module to PID compensation amplification module;
Described temperature survey amplifier module receives the temperature reference value of described thermal module setting and the measured temperature of collection by corresponding pin;
Described temperature survey amplifier module is powered to described voltage module by corresponding pin;
Described temperature survey amplifier module regulates described Pulse width modulation module control signal by corresponding pin;
Described parameter module is connected with described oscillator module, controls described oscillator;
Described Pulse width modulation module receives described PID by corresponding pin and compensates amplification module, temperature survey amplifier module and oscillator module control signal, exports and controls described field effect control module;
Described field effect control module receives the control signal of described Pulse width modulation module by corresponding pin, export external output to;
Described voltage module is powered to described thermal module by corresponding pin.
Further, described temperature survey amplifier module is ADN8830 chip.
Further, PID compensation amplification module comprises the first resistance, the second resistance, the 3rd resistance, the first electric capacity, the second electric capacity and the 3rd electric capacity;
Wherein, the first end of described first resistance is connected with the first end of described first electric capacity and described ADN8830 chip the 12 pin, second end of described first resistance is connected with the second end of described second resistance and described ADN8830 chip the tenth tripod, and the first end of described second resistance and the second end of described first electric capacity and the first end of described 3rd resistance, the first end of described second electric capacity are connected;
Second end of described 3rd resistance is connected with the first end of described 3rd electric capacity, and the second end of described 3rd electric capacity is connected with the second end of described second electric capacity and described ADN8830 chip the 14 pin.
Further, described thermal module comprises the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 4th electric capacity, the first diode, the second diode, the first triode, the second triode and first interface composition;
Wherein, first end and the described ADN8830 chip crus secunda of the first end of described first interface and the first end of described 4th electric capacity, described 4th resistance are connected, the second end ground connection of described first interface, the second end ground connection of described 4th electric capacity;
The first end ground connection of described 5th resistance, first end and described ADN8830 chip the 4th pin of the second end and described 6th resistance are connected, and the second end of described 6th resistance is connected with the second end of described 4th resistance;
The first end of described 7th resistance is connected with direct supply, second end is connected with described first diode cathode, described first diode cathode is connected with described first transistor collector, and described first transistor emitter ground connection, base stage are connected with described ADN8830 chip the 5th pin;
The first end of described 8th resistance is connected with direct supply, second end is connected with described second diode cathode, described second diode cathode is connected with described second transistor collector, and described second transistor emitter ground connection, base stage are connected with described ADN8830 chip first pin.
Further, described voltage module comprises benchmark power supply unit, without driving power supply unit, maximum voltage power supply unit and output voltage unit;
Wherein, described benchmark power supply unit is connected with the second end of described 4th resistance the secondth end and described 6th resistance by described ADN8830 chip the 7th pin;
Described without driving power supply unit to comprise the 5th electric capacity, described without driving power supply unit to be connected by the first end of described ADN8830 chip octal and described 5th electric capacity and direct current supply, the second end ground connection of described 5th electric capacity;
Described maximum voltage power supply unit is by described ADN8830 chip the 15 pin ground connection;
Described output voltage unit is connected with output monitoring equipment by described ADN8830 chip the 16 pin.
Further, described parameter module comprises the 9th resistance, the tenth resistance, the 11 resistance, the 6th electric capacity and the 7th electric capacity;
Wherein, the first end of described 9th resistance and the first end of described 6th electric capacity and described ADN8830 chip the 30 pin are connected to the ground; Second end of described 9th resistance is connected with the first end of described ADN8830 chip the 29 pin and described tenth resistance with the second end of described 6th electric capacity, and the second end of described tenth resistance is connected with described ADN8830 chip the 7th pin;
The first end of described 7th electric capacity is connected with described ADN8830 chip the 27 pin, second end is connected with the first end of described 11 resistance, described ADN8830 chip the 25 pin and ground, and the second end of described 11 resistance is connected with described ADN8830 chip the 26 pin.
Further, described Pulse width modulation module and oscillator module are embedded in described ADN8830 chip.
Further, described field effect control module comprises field effect driver element and field effect bridge;
Wherein, described field effect driver element comprises the first driving chip, the second driving chip, the 12 resistance, the 13 resistance, the 14 resistance, the 15 resistance, the 16 resistance, the 17 resistance, the 18 resistance, the 19 resistance, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, the 11 electric capacity and the 12 electric capacity;
Described tenth electric capacity first end is connected with described ADN8830 chip the 20 pin and direct supply, described tenth electric capacity second pin ground connection;
The first end of described 12 resistance, the first end of described 13 resistance are connected with described ADN8830 chip the 22 pin, second end of described 12 resistance is connected with the 7th pin of described first driving chip, second end of described 13 resistance is connected with the second pin of described first driving chip, described first driving chip the 3rd pin ground connection;
The first end of described 14 resistance is connected with the first end of described ADN8830 chip the 21 pin and described 15 resistance, second end of described 14 resistance is connected with the 3rd pin of described first driving chip, second end of described 15 resistance is connected with described first driving chip the 5th pin, described 8th electric capacity first end is connected with the first end of described 9th electric capacity and ground connection, and the second end of described 8th electric capacity is connected with the second end of described 9th electric capacity and is connected with direct supply and described first driving chip the 6th pin;
The first end of described 16 resistance is connected with the first end of described 17 resistance and described ADN8830 chip the 11 pin, second end of described 16 resistance is connected with described second driving chip the 4th pin, and described 17 resistance second end is connected with described second driving chip the 5th pin;
Described 18 resistance first end is connected with described 19 resistance first end and described ADN8830 chip the tenth pin, described 18 resistance second end is connected with described second driving chip the 7th pin, described 19 resistance second end is connected with described second driving chip second pin, described 11 electric capacity first end is connected with described 12 electric capacity first end and ground connection, and described 11 electric capacity second end is connected with described 12 electric capacity second end and is connected with direct supply and described second driving chip the 6th pin.
Further, described field effect bridge comprises the 13 electric capacity, the 14 electric capacity, the 15 electric capacity, the 16 electric capacity, the 17 electric capacity, the 20 resistance, the 21 resistance, the 22 resistance, the 23 resistance, the 24 resistance, the 25 resistance, the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the first inductance and the second interface composition;
Wherein, described first field effect transistor, the 4th field effect transistor are P type field effect transistor, and the second field effect transistor, the 3rd field effect transistor are N-type field effect transistor;
Described first field effect transistor drain electrode is connected with the 13 electric capacity first end and direct supply, and grid is connected with described first driving chip the 5th pin, and source electrode drains with described first inductance first end and described second field effect transistor and is connected, described 13 electric capacity second end ground connection, described first inductance second end and described 14 electric capacity first end, described 20 resistance first end and described second interface first end are connected, described 14 electric capacity second end ground connection, described 20 resistance second end is connected with described 21 resistance first end and the 24 resistance first end, described 21 resistance second end ground connection, described 24 resistance second end is connected with described ADN8830 chip the 19 pin, described second fet gate is connected with described first driving chip the 7th pin, source ground,
Described 3rd field effect transistor grounded drain, grid is connected with described second driving chip the 7th pin, and source electrode drains with described 15 electric capacity first end, described 22 resistance first end, described second interface second end and described 4th field effect transistor and is connected; Described 15 electric capacity second end ground connection, described 22 resistance second end and described 23 resistance first end and the 25 resistance first end, the 17 electric capacity first end are connected, described 23 resistance second end ground connection, described 25 resistance second end is connected with described ADN8830 chip the 9th pin, described second fet gate is connected with described second driving chip the 5th pin and described 17 electric capacity second end, source electrode is connected with described 16 electric capacity first end and connects direct supply, described 16 electric capacity second end ground connection.
Further, described first driving chip, the second driving chip are IR4427, and described first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor are IRF7343.
The present invention proposes a kind of super-radiance light emitting diode temperature-control circuit, by on the basis of existing TEC controller ADN8830, add field effect control module, adopt IR4427 field-effect amplifier part and IRF7343 field effect transistor, and then improve range of control and the degree of accuracy of voltage and electric current.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not entire infrastructure.
Embodiment one
Fig. 1 is a kind of super-radiance light emitting diode temperature-control circuit construction module schematic diagram that the embodiment of the present invention provides.This circuit comprises temperature survey amplifier module 110, PID compensates amplification module 120, thermal module 130, voltage module 140, parameter module 150, oscillator module 160, Pulse width modulation module 170 and field effect control module 180;
Wherein, described temperature survey amplifier module 110 and described PID are compensated amplification module 120 and are connected by corresponding pin, to realize the control that described temperature survey amplifier module 110 couples of PID compensate amplification module 120;
Described temperature survey amplifier module 110 receives the temperature reference value of described thermal module 130 setting and the measured temperature of collection by corresponding pin;
Described temperature survey amplifier module 110 is powered to described voltage module 140 by corresponding pin;
Described temperature survey amplifier module 110 regulates described Pulse width modulation module 170 control signal;
Described parameter module 150 is connected with described oscillator module 160, controls described oscillator module 160;
Described Pulse width modulation module 170 receives described PID by corresponding pin and compensates amplification module 120, temperature survey amplifier module 110 and oscillator module 160 control signal, exports and controls described field effect control module 180;
Described field effect control module 180 receives the control signal of described Pulse width modulation module 170 by corresponding pin, exports external output to;
Described voltage module 140 is powered to described thermal module 130 by corresponding pin.
Fig. 2 is a kind of super-radiance light emitting diode temperature-control circuit schematic diagram that the embodiment of the present invention provides.
Further, described temperature survey amplifier module 110 is ADN8830 chip.
Further, PID compensation amplification module comprises the first resistance R1, the second resistance R2, the 3rd resistance R3, the first electric capacity C1, the second electric capacity C2 and the 3rd electric capacity C3;
Wherein, the first end of described first resistance R1 is connected with the first end of described first electric capacity C1 and described ADN8830 chip the 12 pin, second end of described first resistance R1 is connected with second end of described second resistance R2 and described ADN8830 chip the tenth tripod, and the first end of described second resistance R2 and second end of described first electric capacity C1 and the first end of described 3rd resistance R3, the first end of described second electric capacity C2 are connected;
Second end of described 3rd resistance R3 is connected with the first end of described 3rd electric capacity C3, and second end of described 3rd electric capacity C3 is connected with second end of described second electric capacity C2 and described ADN8830 chip the 14 pin.
Wherein, described first resistance R1, the second resistance R2, the 3rd resistance R3, the first electric capacity C1, the second electric capacity C2 and the 3rd electric capacity C3 form integrating amplification circuit, and be connected with corresponding pin the effect played and compensate and amplify.
Further, described thermal module 130 comprises the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 4th electric capacity C4, the first diode D1, the second diode D2, the first triode Q1, the second triode Q2 and first interface H1 form;
Wherein, first end and the described ADN8830 chip crus secunda of the first end of described first interface H1 and the first end of described 4th electric capacity C4, described 4th resistance R4 are connected, the second end ground connection of described first interface H1, the second end ground connection of described 4th electric capacity C4; The external thermistor of described first interface H1, for by extraneous collecting temperature signal transmission to described ADN8830 chip, the ground wire of second end of the 4th electric capacity C4 is signal ground;
The first end ground connection of described 5th resistance R5, first end and described ADN8830 chip the 4th pin of the second end and described 6th resistance R6 are connected, and second end of described 6th resistance R6 is connected with second end of described 4th resistance R4; ADN8830 chip the 4th pin is standard temperature design temperature pin, for established standards temperature, and the first termination signal ground of described 5th resistance R5;
The first end of described 7th resistance R7 is connected with direct supply, second end is connected with described first diode D1 positive pole, described first diode D1 negative pole is connected with described first triode Q1 collector, described first triode Q1 grounded emitter, base stage are connected with described ADN8830 chip the 5th pin, and the first triode Q1 launches with connecing power supply; For display circuit duty, when state of finishing the work is debugged, described first diode D2 is bright.
The first end of described 8th resistance R8 is connected with direct supply, second end is connected with described second diode D2 positive pole, described second diode D2 negative pole is connected with described second triode Q2 collector, described second triode Q2 grounded emitter, base stage are connected with described ADN8830 chip first pin, and the second triode Q2 launches with connecing power supply.For display circuit duty, when duty is abnormal, described second diode D2 is bright.
Further, described voltage module 140 comprises benchmark power supply unit, without driving power supply unit, maximum voltage power supply unit and output voltage unit;
Wherein, described benchmark power supply unit is connected with second end of described 4th resistance R4 second end and described 6th resistance R6 by described ADN8830 chip the 7th pin; Power to described first interface H1 circuit for reference voltage.
Described without driving power supply unit to comprise the 5th electric capacity C5, described without driving power supply unit to be connected by the first end of described ADN8830 chip octal and described 5th electric capacity C5 and direct current supply, the second end ground connection of described 5th electric capacity C5; This ground is signal ground;
Described maximum voltage power supply unit is by described ADN8830 chip the 15 pin ground connection, and this ground is signal ground;
Described output voltage unit is connected with output monitoring equipment by described ADN8830 chip the 16 pin.
Further, described parameter module comprises the 9th resistance R9, the tenth resistance R10, the 11 resistance R11, the 6th electric capacity C6 and the 7th electric capacity C7;
Wherein, the first end of described 9th resistance R9 and the first end of described 6th electric capacity C6 and described ADN8830 chip the 30 pin are connected to the ground, and this ground is signal ground; Second end of described 9th resistance R9 is connected with the first end of described ADN8830 chip the 29 pin and described tenth resistance R10 with second end of described 6th electric capacity C6, and second end of described tenth resistance R10 is connected with described ADN8830 chip the 7th pin; Wherein, second end of described tenth resistance R10 is for receiving power supply, and described 9th resistance R9, described 6th electric capacity C6 are for preparing output phase place;
The first end of described 7th electric capacity C7 is connected with described ADN8830 chip the 27 pin, second end is connected with the first end of described 11 resistance R11, described ADN8830 chip the 25 pin and ground, this ground is signal ground, and second end of described 11 resistance R11 is connected with described ADN8830 chip the 26 pin.Wherein, described ADN8830 chip the 25 pin, the 26 pin, the 27 pin for preparing initial value, the frequency of output signal;
Further, described Pulse width modulation module 170 and oscillator module 160 are embedded in described ADN8830 chip.
Further, described field effect control module 180 comprises field effect driver element and field effect bridge;
Wherein, described field effect driver element comprises the first driving chip IR1, the second driving chip IR2, the 12 resistance R12, the 13 resistance R13, the 14 resistance R14, the 15 resistance R15, the 16 resistance R16, the 17 resistance R17, the 18 resistance R18, the 19 resistance R19, the 8th electric capacity C8, the 9th electric capacity C9, the tenth electric capacity C10, the 11 electric capacity C11 and the 12 electric capacity C12;
Described tenth electric capacity C10 first end is connected with described ADN8830 chip the 20 pin and direct supply, between this direct supply and Power supply, string has resistance for improving fan-out capability, described tenth electric capacity C10 second pin ground connection, this ground is power supply ground, is installed with resistance between this power supply ground and signal ground;
The first end of described 12 resistance R12, the first end of described 13 resistance R13 are connected with described ADN8830 chip the 22 pin, second end of described 12 resistance R12 is connected with the 7th pin of described first driving chip IR1, second end of described 13 resistance R13 is connected with second pin of described first driving chip IR1, described first driving chip IR1 the 3rd pin ground connection;
Wherein said first driving chip IR1 is for improving signal to increase driving force, and described 12 resistance R12 is used for feedback;
The first end of described 14 resistance R14 is connected with the first end of described ADN8830 chip the 21 pin and described 15 resistance R15, second end of described 14 resistance R14 is connected with the 3rd pin of described first driving chip IR1, second end of described 15 resistance R15 is connected with described first driving chip IR1 the 5th pin, described 8th electric capacity C8 first end is connected with the first end of described 9th electric capacity C9 and ground connection, this ground is power supply ground, second end of described 8th electric capacity C8 is connected with second end of described 9th electric capacity C9 and is connected with direct supply and described first driving chip IR1 the 6th pin, this power supply is+12V,
Wherein, described 15 resistance R15 is used for feedback, and described 8th electric capacity C8 and described 9th electric capacity C9 is used for filtering;
The first end of described 16 resistance R16 is connected with the first end of described 17 resistance R17 and described ADN8830 chip the 11 pin, second end of described 16 resistance R16 is connected with described second driving chip IR2 the 4th pin, and described 17 resistance R17 second end is connected with described second driving chip IR2 the 5th pin;
Described 18 resistance R18 first end is connected with described 19 resistance R19 first end and described ADN8830 chip the tenth pin, described 18 resistance R18 second end is connected with described second driving chip IR2 the 7th pin, described 19 resistance R19 second end is connected with described second driving chip IR2 second pin, described 11 electric capacity C11 first end is connected with described 12 electric capacity C12 first end and ground connection, described 11 electric capacity C11 second end is connected with described 12 electric capacity C12 second end and is connected with direct supply and described second driving chip IR2 the 6th pin, this power supply is+12V.
Wherein, described 18 resistance R18, the 19 resistance R19 are used for feedback, and described 11 electric capacity C11, the 12 electric capacity C12 are used for filtering.
Further, described field effect bridge comprises the 13 electric capacity C13, the 14 electric capacity C14, the 15 electric capacity C15, the 16 electric capacity C16, the 17 electric capacity C17, the 20 resistance R20, the 21 resistance R21, the 22 resistance R22, the 23 resistance R23, the 24 resistance R24, the 25 resistance R25, the first field effect transistor Q3, the second field effect transistor Q4, the 3rd field effect transistor Q5, the 4th field effect transistor Q6, the first inductance L 1 and the second interface H2 and forms;
Wherein, described first field effect transistor Q3, the 4th field effect transistor Q6 are P type field effect transistor, and the second field effect transistor Q4, the 3rd field effect transistor Q5 are N-type field effect transistor;
Described first field effect transistor Q3 drain electrode is connected with the 13 electric capacity C13 first end and direct supply, this power supply is+12V, grid is connected with described first driving chip IR1 the 5th pin, and source electrode drains with described first inductance L 1 first end and described second field effect transistor Q4 and is connected, described 13 electric capacity C13 second end ground connection, this ground is power supply ground, described first inductance L 1 second end and described 14 electric capacity C14 first end, described 20 resistance R20 first end and described second interface H2 first end are connected, described 14 electric capacity C14 second end ground connection, this ground is power supply ground, described 20 resistance R20 second end is connected with described 21 resistance R21 first end and the 24 resistance R24 first end, described 21 resistance R21 second end ground connection, this ground is power supply ground, described 24 resistance R24 second end is connected with described ADN8830 chip the 19 pin, described second field effect transistor Q3 grid is connected with described first driving chip IR1 the 7th pin, source ground, this ground is power supply ground.
Described 3rd field effect transistor Q5 grounded drain, grid is connected with described second driving chip IR2 the 7th pin, and source electrode drains with described 15 electric capacity C15 first end, described 22 resistance R22 first end, described second interface H2 second end and described 4th field effect transistor Q6 and is connected, described 15 electric capacity C15 second end ground connection, this ground is power supply ground, described 22 resistance R22 second end and described 23 resistance R23 first end and the 25 resistance R25 first end, 17 electric capacity C17 first end is connected, described 23 resistance R23 second end ground connection, this ground is power supply ground, described 25 resistance R25 second end is connected with described ADN8830 chip the 9th pin, described second field effect transistor Q4 grid is connected with described second driving chip H2 the 5th pin and described 17 electric capacity C17 second end, source electrode is connected with described 16 electric capacity C16 first end and connects direct supply, , this direct supply is+12V, described 16 electric capacity C16 second end ground connection, this ground is power supply ground.
Further, described first driving chip IR1, the second driving chip IR2 are IR4427, and described first field effect transistor Q3, the second field effect transistor Q4, the 3rd field effect transistor Q5, the 4th field effect transistor Q6 are IRF7343.
Wherein, during super-radiance light emitting diode temperature-control circuit work of the present invention, described first field effect transistor Q3, the 3rd field effect transistor Q5 are in same duty; Described second field effect transistor Q4, the 4th field effect transistor Q6 are in same duty.
Be only the preferred embodiment of the embodiment of the present invention described in upper, be not limited to the embodiment of the present invention, to those skilled in the art, the embodiment of the present invention can have various change and change.Any amendment done within all spirit in the embodiment of the present invention and principle, equivalent replacement, improvement etc., within the protection domain that all should be included in the embodiment of the present invention.