CN104579650A - Method and device for modular exponentiation operation - Google Patents
Method and device for modular exponentiation operation Download PDFInfo
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Abstract
The invention discloses a method and device for modular exponentiation operation. The method comprises the following steps: a controller selects data flow to be processed and stores the data flow in a first storer; a modular exponentiation operational unit reads data bit in the first storer; when the value of the data bit is 1, a first operation is performed, and the result of the first operation is stored in a second storer; when the value of the data bit is 0, second operation is performed, and the result of second operation is stored in the second storer. By adoption of the method and the device, the power consumption of the modular exponentiation operation device can be effectively reduced.
Description
Technical field
The present invention relates to field of data encryption, particularly a kind of method and apparatus of Montgomery Algorithm.
Background technology
Along with the extensive use of smart card, the application of security algorithm is more and more extensive.RSA public key encryption algorithm is the most influential current public key encryption algorithm, and the fail safe of RSA counts the difficulty of decomposing based on large.
The core calculations of RSA Algorithm is Montgomery Algorithm.In existing Montgomery Algorithm device, be generally jointly realize Montgomery Algorithm by controller and arithmetic unit, wherein arithmetic unit adopts hardware implementing.The implementation procedure of Montgomery Algorithm can be described below: controller is chosen needs binary data stream to be processed, whether the value judging first data bit of binary data stream is 1, if the value of first data bit is 1, then controller scheduling computation device first carries out computing module-square, then carries out modular multiplication; If the value of first data bit is 0, then controller scheduling computation device carries out computing module-square; Described computing module-square or modular multiplication complete after, then adopt such scheme to judge and arithmetic operation the value of other data bit successively, thus realize Montgomery Algorithm.
Can learn from such scheme, controller needs to judge the value of each data bit in binary data stream, and according to the value of this data bit, scheduling computation device starts corresponding computing, the realization of whole Montgomery Algorithm needs controller to participate in a large amount of traffic controls, causes the power consumption of Montgomery Algorithm device larger.
Summary of the invention
The problem that the embodiment of the present invention solves is in Montgomery Algorithm process, the problem that Montgomery Algorithm device power consumption is larger.
For solving the problem, the embodiment of the present invention provides a kind of implementation method of modulus-power algorithm, comprising: controller is selected to need data flow to be processed, and is stored in first memory by described data flow; Montgomery Algorithm device reads the data bit in first memory successively, when the value of described data bit is 1, carries out the first computing, and the result of the first computing is stored into second memory; When the value of described data bit is 0, carry out the second computing, and the result of the second computing is stored into second memory.
Optionally, carry out the first computing described in comprise: carry out computing module-square to described data bit, and carry out modular multiplication to the result of described computing module-square.
Optionally, carry out the second computing described in comprise: carry out computing module-square to described data bit.
Optionally, carry out the second computing and also comprise described in: the result of described data bit being carried out to described computing module-square carries out redundant operation, and using the result of the result of described computing module-square as described second computing.
Optionally, the duration performing described redundant operation is equal with the duration performing described modular multiplication.
Optionally, described redundant operation is modular multiplication.
Optionally, the duration performing once described computing module-square is equal with the duration performing once described modular multiplication.
Optionally, described in carry out the first computing, also comprise: between described computing module-square and described modular multiplication, waiting time is set.
Optionally, described waiting time is equal with the duration that described Montgomery Algorithm device obtains shared by each data bit.
For solving the problem, the embodiment of the present invention additionally provides a kind of Montgomery Algorithm device, comprising: control unit, needs data flow to be processed, and described data flow is stored into first memory for selecting; Montgomery Algorithm unit, for obtaining the data bit in first memory successively, and judges the value of described data bit, when the value of described data bit is 1, carries out the first computing, and the result of the first computing is stored into second memory; When the value of described data bit is 0, carry out the second computing, and the result of the second computing is stored into second memory.
Optionally, described Montgomery Algorithm unit comprises: the first multiplier, and described first multiplier is used for carrying out the first computing, comprising: carry out computing module-square to described data bit, and carries out modular multiplication to the result of described computing module-square.
Optionally, described Montgomery Algorithm unit comprises: the second multiplier, and described second multiplier is used for carrying out the second computing, comprising: carry out computing module-square to described data bit.
Optionally, described Montgomery Algorithm unit also comprises: first arithmetic device, and described first arithmetic device is used for carrying out redundant operation to the operation result of described second multiplier, and using the result of the operation result of described second multiplier as described second computing.
Optionally, to perform the duration of described redundant operation equal with the duration that described first multiplier performs described modular multiplication for described first arithmetic device.
Optionally, described first arithmetic device is the 3rd multiplier, for carrying out modular multiplication to the result of described computing module-square.
Optionally, the described first multiplier duration that performs once described computing module-square is equal with the duration that described first multiplier performs once described modular multiplication.
Optionally, be set between the described computing module-square and described modular multiplication of described first multiplier waiting time.
Optionally, described waiting time is equal with the duration that Montgomery Algorithm unit obtains shared by each data bit.
Compared with prior art, the technical scheme of the embodiment of the present invention has the following advantages:
For a pending data flow, controller only needs scheduling once, data flow to be processed for described need is stored in first memory, adopt Montgomery Algorithm device to complete and Montgomery Algorithm is carried out to each data bit in first memory, and do not need controller to dispatch each data bit, therefore can reduce the number of times that controller participates in scheduling, thus the power consumption of Montgomery Algorithm device can be reduced.
Further, when the value of data bit is 0, by increasing the modular multiplication that does not affect the redundancy of operation result, it is completely the same that computing when computing execution duration when making the value of data bit be 0 and the value of data bit are 1 performs duration, data operation flow process realizes full symmetric, effectively can prevent power consumption analysis.
In addition, when the value of data bit is 1, between computing module-square and modular multiplication, add waiting time, waiting time is equal with the duration obtained shared by each data bit.Because above-mentioned waiting time is equal with the duration obtained shared by each data bit, and waiting time is much smaller than the operation duration of modular multiplication, Montgomery Algorithm for data flow just can regard the modular multiplication that the succession of intervals time is equal as, therefore, it is possible to effectively prevent power consumption analysis.
Accompanying drawing explanation
Fig. 1 is the Montgomery Algorithm flow chart in the embodiment of the present invention one;
Fig. 2 is the Montgomery Algorithm flow chart in the embodiment of the present invention two;
Fig. 3 is the Montgomery Algorithm flow chart in the embodiment of the present invention three;
Fig. 4 is the Montgomery Algorithm apparatus structure schematic diagram in the embodiment of the present invention four.
Embodiment
In existing Montgomery Algorithm device, be generally jointly realize Montgomery Algorithm by controller and arithmetic unit, wherein arithmetic unit adopts hardware implementing.The process realizing Montgomery Algorithm can be described below: controller is chosen needs binary data stream to be processed, whether the value judging first data bit of binary data stream is 1, if the value of first data bit is 1, then controller scheduling computation device first carries out computing module-square, then carries out modular multiplication; If the value of first data bit is 0, then controller scheduling computation device carries out computing module-square; Described computing module-square or modular multiplication complete after, then adopt said method to judge and arithmetic operation the value of other data bit successively, thus realize Montgomery Algorithm.Can learn from such scheme, controller needs to judge the value of each data bit in binary data stream, and according to the value of this data bit, scheduling computation device starts corresponding computing, the realization of whole Montgomery Algorithm needs controller to participate in a large amount of traffic controls, causes the power consumption of Montgomery Algorithm device larger.
For a pending data flow, controller only needs scheduling once, data flow to be processed for described need is stored in first memory, adopt Montgomery Algorithm device to complete and Montgomery Algorithm is carried out to each data bit in first memory, and do not need controller to dispatch each data bit, therefore can reduce the number of times that controller participates in scheduling, thus the power consumption of Montgomery Algorithm device can be reduced.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Embodiment one
Present embodiments provide a kind of Montgomery Algorithm method, with reference to Fig. 1, be described in detail below by way of concrete steps.
Step S101, controller is selected to need data flow to be processed, and described data flow is stored in first memory.
In concrete enforcement, need data flow to be processed can be binary bit stream, first memory can be register, and needing data flow to be processed for storing, also can be the memory of other types.
Step S102, Montgomery Algorithm device obtains the data bit in first memory successively, when the value of described data bit is 1, carries out the first computing, and the result of the first computing is stored into second memory; When the value of described data bit is 0, carry out the second computing, and the result of the second computing is stored into second memory.
In concrete enforcement, the first computing can comprise following computing: carry out computing module-square to data bit, and carries out modular multiplication to the result of computing module-square, and the second computing can comprise following computing: carry out computing module-square to data bit.No matter be execution first computing or the second computing, the result after computing can be saved in second memory.
In concrete enforcement, second memory can be register, also can be RAM.In the present embodiment, owing to there will be more Large-number operation in the implementation procedure of Montgomery Algorithm, need larger memory space to store the result of calculating, RAM therefore can be selected as second memory.
In concrete enforcement, Montgomery Algorithm device judges the value of the data bit in data flow successively and performs Montgomery Algorithm, and the result of each data bit computing is stored into successively in second memory.After the data bit in data flow all completes judgement and execution Montgomery Algorithm, controller can select new data flow, and repeats above-mentioned flow process, until data processing is complete.
Adopt the scheme of the present embodiment, for a pending data flow, controller only needs scheduling once, data flow to be processed for described need is stored in first memory, adopt Montgomery Algorithm device to complete and Montgomery Algorithm is carried out to each data bit in first memory, and do not need controller to dispatch each data bit, therefore can reduce the number of times that controller participates in scheduling, thus the power consumption of Montgomery Algorithm device can be reduced.
In concrete enforcement, further expansion can also be done to such scheme, be described in detail below by way of specific embodiment.
Embodiment two
Present embodiments provide a kind of Montgomery Algorithm method, with reference to Fig. 2, be described in detail below by way of concrete steps.
Step S201, controller is selected to need data flow to be processed, and described data flow is stored in first memory.
In concrete enforcement, first memory can store needs data flow to be processed.The length of data flow is N, and the length of a data flow can be 32 data bit, also can be the integral multiple of 32.
Step S202, carries out Initialize installation to the counter preset in Montgomery Algorithm device.
Montgomery Algorithm device can read the data bit in described first memory successively.In concrete enforcement, can a counter be set in Montgomery Algorithm device, be judged the number of the data bit that Montgomery Algorithm device is current read by the value of counter.The length of counter is identical with needing the length of data flow to be processed, and the value of initialization counter is 1.
Step S203, Montgomery Algorithm device reads the data bit in first memory.
Step S204, judges whether the value of data bit is 1, if 1, then performs step S205; If 0, then perform step S207.
Step S205, carries out computing module-square to current data position.
Step S206, carries out modular multiplication to the operation result of step S205, and the result of modular multiplication is stored into second memory.
Step S207, carries out computing module-square to current data position, and the result of computing module-square is stored into second memory.
Step S208, carries out redundant operation to the operation result of step S207.
In concrete enforcement, in order to make the result of redundant operation not affect Montgomery Algorithm, the result of redundant operation is not stored in second memory, the result of redundant operation can be abandoned yet.
In concrete enforcement, the duration of an execution redundant operation can be made equal with the duration performing a modular multiplication, thus make the power consumption of an execution redundant operation equal with the power consumption performing a modular multiplication, prevent power consumption analysis.
In the present embodiment, redundant operation can adopt the compute mode identical with step S206, modular multiplication is carried out to the result of step S207 computing, thus it is equal with the duration performed shared by step S205 and step S206 to make to perform duration shared by step S207 and step S208, and then make the power consumption performing step S207 and step S208 equal with the power consumption performing step S205 and step S206, the therefore extraneous value that cannot be obtained current data position by power consumption analysis.
Step S209, after the first data bit computing completes, Montgomery Algorithm device reads next data bit, and the value of calculator is corresponding adds 1.
Step S210, if there is next data bit, then repeats step S202 to step S209; If there is not next data bit, then process ends.
This step is by judging whether the value of calculator is N+1, judges whether described data bit is last data bit, if last data bit, then process ends; If not last data bit, then Montgomery Algorithm is carried out to next data bit.
Adopt the scheme of the present embodiment, when the value of data bit is 0, by increasing the redundant operation that does not affect operation result, and the duration performing a redundant operation is equal with the duration performing a modular multiplication, the computing when value that computing when the value of data bit can be made like this to be 0 performs duration and power consumption and data bit is 1 perform duration and power consumption completely the same, data operation flow process realizes full symmetric, effectively can prevent power consumption analysis.
Be understandable that, redundant operation has more than and is confined to modular multiplication, and other can make computing that computing duration is equal with the duration of modular multiplication can as redundant operation.In addition, also redundant operation can added when the value of data bit is 1, if the redundant operation number added is M, the redundancy number that the value that the redundancy number then added when the value of data bit is 0 equals data bit adds when being 1 adds 1, i.e. M+1, because when the value of data bit is 1, compared with when the value being with numerical digit is 0, Montgomery Algorithm device has done a modular multiplication more.The value of such as data bit adds a redundancy when being 1, then add two redundancies when the value of data bit is 0, can realize data operation flow process full symmetric equally, effectively can prevent power consumption analysis.
Embodiment three
Present embodiments provide a kind of Montgomery Algorithm method, with reference to Fig. 3, be described in detail below by way of concrete steps.
Step S301, controller is selected to need data flow to be processed, and described data flow is stored in first memory.
Step S302, carries out Initialize installation to the counter preset in Montgomery Algorithm device.
Montgomery Algorithm device can read the data bit in described first memory successively.In concrete enforcement, can a counter be set in Montgomery Algorithm device, be judged the number of the data bit that Montgomery Algorithm device is current read by the value of counter.The length of counter is identical with needing the length of data flow to be processed, and the value of initialization counter is 1.
Step S303, Montgomery Algorithm device reads the data bit in first memory.
Step S304, judges whether the value of the first data bit is 1, if 1, then performs step S305; If 0, then perform step S307.
Step S305, carries out computing module-square to current data position, after computing module-square completes, waits for preset duration.
In concrete enforcement, described default waiting time t2 can be made equal with the duration t3 of Montgomery Algorithm device read data bit.
Step S306, carries out modular multiplication to the operation result of step S305, and the result of modular multiplication is stored into second memory.
Step S307, carries out computing module-square to current data position, and the result of computing module-square is stored into second memory.
Step S308, after the first data bit computing completes, Montgomery Algorithm device reads next data bit.
Step S309, if there is next data bit, then repeats step S302 to step S308; If there is not next data bit, then process ends.
This step is by judging whether the value of calculator is N+1, judges whether described data bit is last data bit, if last data bit, then process ends; If not last data bit, then Montgomery Algorithm is carried out to next data bit.
Such as, shared by computing module-square and modular multiplication, duration is t1, and when the value of data bit is 1, arrange waiting time t2 between computing module-square and modular multiplication, the duration t3 that waiting time t2 and Montgomery Algorithm device obtain shared by each data bit is equal.
For two adjacent data bit b1 and b2, wherein, the value of data bit b1 is 0, the value of data bit b2 is 1, and the first read data bit b1 of Montgomery Algorithm device, because the value of data bit b1 is 0, so data bit b1 only needs to carry out computing module-square, duration shared by computing module-square is t1.Can learn from said process, data bit b1 is t1+t3 from being read to the shared time that is finished.
After data bit b1 computing completes, Montgomery Algorithm device read data bit b2, value due to data bit b2 is 1, and Montgomery Algorithm device needs first to carry out computing module-square to data bit b2, then carries out modular multiplication, therefore the operating process of data bit b2 can be divided into two parts: (1) Montgomery Algorithm device read data bit b2, shared duration is t3, and carry out computing module-square to data bit b2, duration shared by computing module-square is t1, therefore, executing duration shared by computing module-square is t1+t3; (2) computing module-square waits for preset duration t2 after completing, and when the stand-by period reaches duration t2, Montgomery Algorithm device performs modular multiplication, and duration shared by modular multiplication is t1, and therefore, the time shared by modular multiplication that executes is t2+t1.Due to t2=t3, then t1+t3=t2+t1.Can learn from above-mentioned calculating process, the calculating process of data bit b2 divides two parts to carry out, and each step shared time is all equal with the time shared by execution data bit b1, then the calculating process of data bit b2 can regard the calculating process of 2 data bit b1 as.
Because above-mentioned waiting time is equal with the duration obtained shared by each data bit, the Montgomery Algorithm for data flow just can regard the modular multiplication that the succession of intervals time is equal as, therefore, it is possible to effectively prevent power consumption analysis.
Embodiment four
Present embodiments provide a kind of Montgomery Algorithm device, with reference to figure 4, described Montgomery Algorithm device comprises: control unit 401, Montgomery Algorithm unit 402, wherein:
Control unit 401, needs data flow to be processed for selecting, and described data flow is stored into first memory;
Montgomery Algorithm unit 402, for obtaining the data bit in first memory successively, and judges the value of described data bit, when the value of described data bit is 1, carries out the first computing, and the result of the first computing is stored into second memory; When the value of described data bit is 0, carry out the second computing, and the result of the second computing is stored into second memory.
In concrete enforcement, Montgomery Algorithm unit 402 comprises: the first multiplier 4021, and for carrying out the first computing, described first computing comprises: carry out computing module-square to described data bit, and carries out modular multiplication to the result of described computing module-square.
In concrete enforcement, Montgomery Algorithm unit 402 comprises: the second multiplier 4022, and for carrying out the second computing, described second computing comprises: carry out computing module-square to described data bit.
In concrete enforcement, Montgomery Algorithm unit 402 also comprises: first arithmetic device 4023, the result that described first arithmetic device is used for carrying out described data bit described computing module-square carries out redundant operation, and using the result of the result of described computing module-square as described second computing.The duration that described first arithmetic device performs described redundant operation is equal with the duration that described first multiplier performs described modular multiplication, and the power consumption that described first arithmetic device performs described redundant operation is equal with the power consumption that described first multiplier performs described modular multiplication.
In concrete enforcement, described first arithmetic device 4023 can be the 3rd multiplier, for carrying out modular multiplication to the result of described computing module-square.
In concrete enforcement, the duration that described first multiplier 4021 performs once described computing module-square is equal with the duration that described first multiplier 4021 performs once described modular multiplication.
In concrete enforcement, between the computing module-square and modular multiplication of described first multiplier 4021, arrange waiting time, waiting time is equal with the duration that Montgomery Algorithm unit obtains shared by each data bit.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (18)
1. a Montgomery Algorithm method, is characterized in that, comprising:
Controller is selected to need data flow to be processed, and is stored in first memory by described data flow;
Montgomery Algorithm device reads the data bit in first memory successively, when the value of described data bit is 1, carries out the first computing, and the result of the first computing is stored into second memory; When the value of described data bit is 0, carry out the second computing, and the result of the second computing is stored into second memory.
2. Montgomery Algorithm method as claimed in claim 1, is characterized in that, described in carry out the first computing and comprise: computing module-square is carried out to described data bit, and modular multiplication is carried out to the result of described computing module-square.
3. Montgomery Algorithm method as claimed in claim 1, is characterized in that, described in carry out the second computing and comprise: computing module-square is carried out to described data bit.
4. Montgomery Algorithm method as claimed in claim 3, it is characterized in that, describedly carry out the second computing and also comprise: the result of described data bit being carried out to described computing module-square carries out redundant operation, and using the result of the result of described computing module-square as described second computing.
5. Montgomery Algorithm method as claimed in claim 4, is characterized in that, the duration performing described redundant operation is equal with the duration performing described modular multiplication.
6. Montgomery Algorithm method as claimed in claim 5, it is characterized in that, described redundant operation is modular multiplication.
7. Montgomery Algorithm method as claimed in claim 2, is characterized in that, the duration performing once described computing module-square is equal with the duration performing once described modular multiplication.
8. Montgomery Algorithm method as claimed in claim 2, is characterized in that, described in carry out the first computing, also comprise: between described computing module-square and described modular multiplication, waiting time is set.
9. Montgomery Algorithm method as claimed in claim 8, it is characterized in that, described waiting time is equal with the duration that described Montgomery Algorithm device obtains shared by each data bit.
10. a Montgomery Algorithm device, is characterized in that, comprising:
Control unit, needs data flow to be processed for selecting, and described data flow is stored into first memory; Montgomery Algorithm unit, for obtaining the data bit in first memory successively, and judges the value of described data bit, when the value of described data bit is 1, carries out the first computing, and the result of the first computing is stored into second memory; When the value of described data bit is 0, carry out the second computing, and the result of the second computing is stored into second memory.
11. Montgomery Algorithm devices as claimed in claim 10, it is characterized in that, described Montgomery Algorithm unit comprises: the first multiplier, described first multiplier is used for carrying out the first computing, comprise: computing module-square is carried out to described data bit, and modular multiplication is carried out to the result of described computing module-square.
12. Montgomery Algorithm devices as claimed in claim 10, it is characterized in that, described Montgomery Algorithm unit comprises: the second multiplier, and described second multiplier is used for carrying out the second computing, comprising: carry out computing module-square to described data bit.
13. Montgomery Algorithm devices as claimed in claim 12, it is characterized in that, described Montgomery Algorithm unit also comprises: first arithmetic device, described first arithmetic device is used for carrying out redundant operation to the operation result of described second multiplier, and using the result of the operation result of described second multiplier as described second computing.
14. Montgomery Algorithm devices as claimed in claim 13, is characterized in that, the duration that described first arithmetic device performs described redundant operation is equal with the duration that described first multiplier performs described modular multiplication.
15. Montgomery Algorithm devices as claimed in claim 14, is characterized in that, described first arithmetic device is the 3rd multiplier, for carrying out modular multiplication to the result of described computing module-square.
16. Montgomery Algorithm devices as claimed in claim 11, is characterized in that, the duration that described first multiplier performs once described computing module-square is equal with the duration that described first multiplier performs once described modular multiplication.
17. Montgomery Algorithm devices as claimed in claim 11, is characterized in that, between the described computing module-square and described modular multiplication of described first multiplier, arrange waiting time.
18. Montgomery Algorithm devices as claimed in claim 17, it is characterized in that, described waiting time is equal with the duration that Montgomery Algorithm unit obtains shared by each data bit.
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| CN1835207A (en) * | 2005-03-17 | 2006-09-20 | 联想(北京)有限公司 | Method of preventing energy analysis attack to RSA algorithm |
| CN101196964A (en) * | 2006-12-07 | 2008-06-11 | 上海安创信息科技有限公司 | Anti-bypass attack algorithm and chip thereof |
| CN101834723A (en) * | 2009-03-10 | 2010-09-15 | 上海爱信诺航芯电子科技有限公司 | RSA (Rivest-Shamirh-Adleman) algorithm and IP core |
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| CN1835207A (en) * | 2005-03-17 | 2006-09-20 | 联想(北京)有限公司 | Method of preventing energy analysis attack to RSA algorithm |
| CN101196964A (en) * | 2006-12-07 | 2008-06-11 | 上海安创信息科技有限公司 | Anti-bypass attack algorithm and chip thereof |
| CN101834723A (en) * | 2009-03-10 | 2010-09-15 | 上海爱信诺航芯电子科技有限公司 | RSA (Rivest-Shamirh-Adleman) algorithm and IP core |
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