CN104579650B - The method and apparatus of Montgomery Algorithm - Google Patents
The method and apparatus of Montgomery Algorithm Download PDFInfo
- Publication number
- CN104579650B CN104579650B CN201310517942.2A CN201310517942A CN104579650B CN 104579650 B CN104579650 B CN 104579650B CN 201310517942 A CN201310517942 A CN 201310517942A CN 104579650 B CN104579650 B CN 104579650B
- Authority
- CN
- China
- Prior art keywords
- data bit
- square
- montgomery algorithm
- memory
- computing module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Complex Calculations (AREA)
Abstract
A kind of method and apparatus of Montgomery Algorithm, the method for the Montgomery Algorithm include：Controller selects data flow to be treated, and will be in data flow storage to first memory；Montgomery Algorithm device is successively read the data bit in first memory, when the value of the data bit is 1, carries out the first operation, and the result of the first operation is stored to second memory；When the value of the data bit is 0, the second operation is carried out, and the result of the second operation is stored to second memory.Using the method and device, the power consumption of Montgomery Algorithm device can be effectively reduced.
Description
Technical field
The present invention relates to field of data encryption, more particularly to a kind of method and apparatus of Montgomery Algorithm.
Background technology
With the extensive use of smart card, the application of security algorithm is more and more extensive.RSA public key encryption algorithms be at present most
Influential public key encryption algorithm, the safety of RSA is based on the difficulty of big number decomposition.
The core calculations of RSA Algorithm are Montgomery Algorithm.In existing Montgomery Algorithm device, generally by controller and fortune
It calculates device and realizes that Montgomery Algorithm, wherein arithmetic unit use hardware realization jointly.The realization process of Montgomery Algorithm can be described as follows：Control
Device chooses binary data stream to be treated, judges whether the value of first data bit of binary data stream is 1, if the
The value of one data bit is 1, then controller scheduling computation device first carries out computing module-square, then carries out modular multiplication；If first
The value of a data bit is 0, then controller scheduling computation device carries out computing module-square；The computing module-square or modular multiplication execute
After the completion, then using the above scheme judgement and arithmetic operation are carried out to the value of other data bit successively, to realize Montgomery Algorithm.
From in said program it is known that controller needs to carry out the value of each data bit in binary data stream
Judge, and according to the value of the data bit, scheduling computation device starts corresponding operation, and the realization of entire Montgomery Algorithm needs controller
A large amount of traffic control is participated in, causes the power consumption of Montgomery Algorithm device larger.
Invention content
The embodiment of the present invention solves the problems, such as it is the larger problem of Montgomery Algorithm device power consumption during Montgomery Algorithm.
To solve the above problems, the embodiment of the present invention provides a kind of implementation method of modulus-power algorithm, including：Controller selects
Data flow to be treated, and will be in data flow storage to first memory；Montgomery Algorithm device is successively read the first storage
Data bit in device carries out the first operation, and the result of the first operation is stored to second when the value of the data bit is 1
Memory；When the value of the data bit is 0, the second operation is carried out, and the result of the second operation is stored to second memory.
Optionally, the first operation of the progress includes：Computing module-square is carried out to the data bit, and to the mould square
The result of operation carries out modular multiplication.
Optionally, the second operation of the progress includes：Computing module-square is carried out to the data bit.
Optionally, the second operation of the progress further includes：To the data bit carry out the result of the computing module-square into
Row redundant operation, and using the result of the computing module-square as the result of second operation.
Optionally, the duration for executing the redundant operation is equal with the duration of modular multiplication is executed.
Optionally, the redundant operation is modular multiplication.
Optionally, the duration for executing the primary computing module-square is equal with the primary duration of the modular multiplication is executed.
Optionally, the first operation of the progress further includes：It is arranged between the computing module-square and the modular multiplication
Waiting time.
Optionally, the waiting time is equal with the Montgomery Algorithm device each occupied duration of data bit of acquisition.
To solve the above problems, the embodiment of the present invention additionally provides a kind of Montgomery Algorithm device, including：Control unit is used
It is stored to first memory in selection data flow to be treated, and by the data flow；Montgomery Algorithm unit, for obtaining successively
The data bit in first memory is taken, and the value of the data bit is judged, when the value of the data bit is 1, is carried out
First operation, and the result of the first operation is stored to second memory；When the value of the data bit is 0, the second fortune is carried out
It calculates, and the result of the second operation is stored to second memory.
Optionally, the Montgomery Algorithm unit includes：First multiplier, first multiplier is for carrying out the first fortune
It calculates, including：Computing module-square is carried out to the data bit, and modular multiplication is carried out to the result of the computing module-square.
Optionally, the Montgomery Algorithm unit includes：Second multiplier, second multiplier is for carrying out the second fortune
It calculates, including：Computing module-square is carried out to the data bit.
Optionally, the Montgomery Algorithm unit further includes：First arithmetic device, the first arithmetic device are used for described second
The operation result of multiplier carries out redundant operation, and using the operation result of second multiplier as the knot of second operation
Fruit.
Optionally, the first arithmetic device executes the duration of the redundant operation and first multiplier executes the mould
The duration of multiplication is equal.
Optionally, the first arithmetic device is third multiplier, and modular multiplication is carried out for the result to the computing module-square
Operation.
Optionally, first multiplier executes the duration of the primary computing module-square and first multiplier executes
The duration of the primary modular multiplication is equal.
Optionally, when waiting is set between the computing module-square and the modular multiplication of first multiplier
It is long.
Optionally, the waiting time is equal with the Montgomery Algorithm unit each occupied duration of data bit of acquisition.
Compared with prior art, the technical solution of the embodiment of the present invention has the following advantages：
For a pending data flow, controller only needs scheduling primary, and the data flow to be treated is deposited
It stores up in first memory, completes to carry out Montgomery Algorithm to each data bit in first memory using Montgomery Algorithm device, and
It does not need controller to be scheduled each data bit, therefore the number that controller participates in scheduling can be reduced, so as to
To reduce the power consumption of Montgomery Algorithm device.
Further, when the value of data bit is 0, by increasing the modular multiplication of a redundancy for not influencing operation result,
So that the operation execution duration when value of the operation execution duration and data bit when the value of data bit is 0 is 1 is completely the same, data
The realization of operation flow is full symmetric, can effectively prevent power consumption analysis.
In addition, when the value of data bit is 1, it is added waiting time between computing module-square and modular multiplication, when waiting
It is long equal with each occupied duration of data bit is obtained.When due to above-mentioned waiting time and the occupied each data bit of acquisition
Length is equal, and waiting time is much smaller than the operation duration of modular multiplication, can regard one as the Montgomery Algorithm of data flow
Consecutive interval time equal modular multiplication, therefore can effectively prevent power consumption analysis.
Description of the drawings
Fig. 1 is the Montgomery Algorithm flow chart in the embodiment of the present invention one；
Fig. 2 is the Montgomery Algorithm flow chart in the embodiment of the present invention two；
Fig. 3 is the Montgomery Algorithm flow chart in the embodiment of the present invention three；
Fig. 4 is the Montgomery Algorithm apparatus structure schematic diagram in the embodiment of the present invention four.
Specific implementation mode
In existing Montgomery Algorithm device, Montgomery Algorithm is realized jointly generally by controller and arithmetic unit, wherein transporting
It calculates device and uses hardware realization.Realize that the process of Montgomery Algorithm can be described as follows：Controller chooses binary data to be treated
Stream, judges whether the value of first data bit of binary data stream is 1, if the value of first data bit is 1, controller
Scheduling computation device first carries out computing module-square, then carries out modular multiplication；If the value of first data bit is 0, controller tune
It spends arithmetic unit and carries out computing module-square；After the completion of the computing module-square or modular multiplication execute, then successively using the above method
Judgement and arithmetic operation are carried out to the value of other data bit, to realize Montgomery Algorithm.It is known that control from said program
Device needs the value to each data bit in binary data stream to judge, and according to the value of the data bit, scheduling computation
Device starts corresponding operation, and the realization of entire Montgomery Algorithm needs controller to participate in a large amount of traffic control, leads to Montgomery Algorithm
The power consumption of device is larger.
For a pending data flow, controller only needs scheduling primary, and the data flow to be treated is deposited
It stores up in first memory, completes to carry out Montgomery Algorithm to each data bit in first memory using Montgomery Algorithm device, and
It does not need controller to be scheduled each data bit, therefore the number that controller participates in scheduling can be reduced, so as to
To reduce the power consumption of Montgomery Algorithm device.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Embodiment one
A kind of Montgomery Algorithm method is present embodiments provided to be described in detail below by way of specific steps referring to Fig.1.
Step S101, controller select data flow to be treated, and will be in data flow storage to first memory.
In specific implementation, data flow to be treated can be binary bit stream, and first memory can be deposit
Device can also be other kinds of memory for storing data flow to be treated.
Step S102, Montgomery Algorithm device obtain the data bit in first memory successively, when the value of the data bit is 1
When, the first operation is carried out, and the result of the first operation is stored to second memory；When the value of the data bit is 0, carry out
Second operation, and the result of the second operation is stored to second memory.
In specific implementation, the first operation may include following operation：Computing module-square is carried out to data bit, and flat to mould
The result of square operation carries out modular multiplication, and the second operation may include following operation：Computing module-square is carried out to data bit.No matter
It is to execute the first operation or the second operation, the result after operation to be saved in second memory.
In specific implementation, second memory can be register, can also be RAM.In the present embodiment, due to mould power
Will appear more Large-number operation during the realization of operation, need larger memory space store calculating as a result, therefore
RAM can be selected as second memory.
In specific implementation, Montgomery Algorithm device successively judges the value of the data bit in data flow and executes mould power fortune
It calculates, and the result of each data bit arithmetic is stored in second memory successively.When the data bit in data flow is all complete
After judging and executing Montgomery Algorithm, controller can select new data flow, and repeat above-mentioned flow, until data processing is complete
Finish.
Using the scheme of the present embodiment, for a pending data flow, controller only needs scheduling primary, will be described
In data flow storage to first memory to be treated, completed to each data in first memory using Montgomery Algorithm device
Position carries out Montgomery Algorithm, is scheduled to each data bit without controller, therefore can reduce controller participation
The number of scheduling, so as to reduce the power consumption of Montgomery Algorithm device.
In specific implementation, further extension can also be made to said program, carried out below by way of specific embodiment detailed
It describes in detail bright.
Embodiment two
A kind of Montgomery Algorithm method is present embodiments provided, with reference to Fig. 2, is described in detail below by way of specific steps.
Step S201, controller select data flow to be treated, and will be in data flow storage to first memory.
In specific implementation, first memory can store data flow to be treated.The length of data flow be N, one
The length of data flow can be 32 data bit, can also be 32 integral multiple.
Step S202 carries out Initialize installation to preset counter in Montgomery Algorithm device.
Montgomery Algorithm device can be successively read the data bit in the first memory.It in specific implementation, can be in mould
One counter is set in power operation device, of the currently-read data bit of Montgomery Algorithm device is judged by the value of counter
Number.The length of counter is identical as the length of data flow to be treated, and the value of initialization counter is 1.
Step S203, Montgomery Algorithm device read the data bit in first memory.
Step S204 judges whether the value of data bit is 1, if 1, thens follow the steps S205；If 0, then follow the steps
S207。
Step S205 carries out computing module-square to current data position.
Step S206 carries out modular multiplication to the operation result of step S205, and by the result of modular multiplication storage to the
Two memories.
Step S207 carries out computing module-square to current data position, and the result of computing module-square is stored to second and is deposited
Reservoir.
Step S208 carries out redundant operation to the operation result of step S207.
In specific implementation, in order to make the result of redundant operation not influence Montgomery Algorithm, the result of redundant operation does not store
In second memory, the result of redundant operation can also be abandoned.
In specific implementation, the duration of redundant operation of execution and the when appearance for executing a modular multiplication can be made
Deng so that execute a redundant operation power consumption with execution the power consumption of modular multiplication it is equal, prevent power consumption analysis.
In the present embodiment, operation mode identical with step S206 may be used in redundant operation, to step S207 operations
Result carry out modular multiplication so that executing duration occupied by step S207 and step S208 and executing step S205 and step
The occupied durations of rapid S206 are equal, so that executing the power consumption and execution step S205 and step of step S207 and step S208
The power consumption of rapid S206 is equal, therefore the extraneous value that current data position can not be obtained by power consumption analysis.
Step S209, after the completion of the first data bit arithmetic, Montgomery Algorithm device reads next data bit, the value phase of calculator
1 should be added.
Step S210, if in the presence of a data bit, repeat step S202 to step S209；If next data are not present
Position, then terminate flow.
Whether this step is N+1 by judging the value of calculator, to judge whether the data bit is the last one data
Position, if it is the last one data bit, then terminates flow；If not the last one data bit, then next data bit is carried out
Montgomery Algorithm.
Using the scheme of the present embodiment, when the value of data bit is 0, by increasing a redundancy for not influencing operation result
Operation, and the duration for executing a redundant operation is equal with the duration of a modular multiplication is executed, and can make data in this way
The operation that operation when the value of position is 0 executes when duration and the value of power consumption and data bit are 1 executes duration and power consumption
Completely the same, the realization of data operation flow is full symmetric, can effectively prevent power consumption analysis.
It is understood that redundant operation is not limited to modular multiplication, other enable to operation duration and modular multiplication
The operation that the duration of operation is equal all can serve as redundant operation.In addition it is also possible to redundancy is added when the value of data bit is 1
Operation, if the redundant operation number being added is M, then the redundancy number being added when the value of data bit is 0 is equal to the value of data bit
The redundancy number being added when being 1 adds 1, i.e. M+1, because when the value of data bit is 1, compared with when the value that numerical digit is is 0, mould power
Arithmetic unit has done a modular multiplication more.Such as the value of data bit be 1 when be added a redundancy, then the value of data bit be 0 when add
Enter two redundancies, it is full symmetric equally to may be implemented data operation flow, can effectively prevent power consumption analysis.
Embodiment three
A kind of Montgomery Algorithm method is present embodiments provided, with reference to Fig. 3, is described in detail below by way of specific steps.
Step S301, controller select data flow to be treated, and will be in data flow storage to first memory.
Step S302 carries out Initialize installation to preset counter in Montgomery Algorithm device.
Montgomery Algorithm device can be successively read the data bit in the first memory.It in specific implementation, can be in mould
One counter is set in power operation device, of the currently-read data bit of Montgomery Algorithm device is judged by the value of counter
Number.The length of counter is identical as the length of data flow to be treated, and the value of initialization counter is 1.
Step S303, Montgomery Algorithm device read the data bit in first memory.
Step S304 judges whether the value of the first data bit is 1, if 1, thens follow the steps S305；If 0, then execute
Step S307.
Step S305 carries out computing module-square to current data position, after computing module-square is completed, when waiting for default
It is long.
In specific implementation, the duration t3 phases of the default waiting time t2 and Montgomery Algorithm device read data bit can be made
Deng.
Step S306 carries out modular multiplication to the operation result of step S305, and by the result of modular multiplication storage to the
Two memories.
Step S307 carries out computing module-square to current data position, and the result of computing module-square is stored to second and is deposited
Reservoir.
Step S308, after the completion of the first data bit arithmetic, Montgomery Algorithm device reads next data bit.
Step S309, if in the presence of a data bit, repeat step S302 to step S308；If next data are not present
Position, then terminate flow.
Whether this step is N+1 by judging the value of calculator, to judge whether the data bit is the last one data
Position, if it is the last one data bit, then terminates flow；If not the last one data bit, then next data bit is carried out
Montgomery Algorithm.
For example, duration occupied by computing module-square and modular multiplication is t1, when the value of data bit is 1, in mould square
Waiting time t2 is set between operation and modular multiplication, and waiting time t2 and each data bit of Montgomery Algorithm device acquisition are occupied
Duration t3 is equal.
For two adjacent data bit b1 and b2, wherein the value of data bit b1 is 0, and the value of data bit b2 is 1, mould power
Arithmetic unit elder generation read data bit b1, because the value of data bit b1 is 0, data bit b1 only needs to carry out computing module-square, mould
A length of t1 when occupied by square operation.From the above process it is known that data bit b1 from be read into be finished occupied when
Between be t1+t3.
After the completion of data bit b1 operations, Montgomery Algorithm device read data bit b2, since the value of data bit b2 is 1, mould power fortune
It calculates device to need first to carry out computing module-square to data bit b2, then carries out modular multiplication, therefore the operating process of data bit b2 can be with
It is divided into two parts：（1）Montgomery Algorithm device read data bit b2, a length of t3 when occupied carry out computing module-square to data bit b2,
A length of t1 when occupied by computing module-square, therefore, a length of t1+t3 when having executed occupied by computing module-square；（2）Computing module-square
Preset duration t2 is waited for after completing, when the stand-by period reaches duration t2, Montgomery Algorithm device executes modular multiplication, modular multiplication fortune
A length of t1 when calculating occupied, therefore, it is t2+t1 to have executed the time occupied by modular multiplication.Due to t2=t3, then t1+t3=t2+
t1.From above-mentioned calculating process it is known that the calculating process of data bit b2 is divided into two parts progress, the time occupied by each step with hold
Time occupied by row data bit b1 is equal, then the calculating process of data bit b2 can regard the operation of 2 data bit b1 as
Journey.
Since above-mentioned waiting time is equal with each occupied duration of data bit is obtained, for the Montgomery Algorithm of data flow
It can regard succession of intervals time equal modular multiplication as, therefore can effectively prevent power consumption analysis.
Example IV
A kind of Montgomery Algorithm device is present embodiments provided, with reference to figure 4, the Montgomery Algorithm device includes：Control unit
401, Montgomery Algorithm unit 402, wherein：
Control unit 401 is stored for selecting data flow to be treated, and by the data flow to first memory；
Montgomery Algorithm unit 402, for successively obtain first memory in data bit, and to the value of the data bit into
Row judges, when the value of the data bit is 1, carries out the first operation, and the result of the first operation is stored to second memory；
When the value of the data bit is 0, the second operation is carried out, and the result of the second operation is stored to second memory.
In specific implementation, Montgomery Algorithm unit 402 includes：First multiplier 4021, it is described for carrying out the first operation
First operation includes：Computing module-square is carried out to the data bit, and modular multiplication is carried out to the result of the computing module-square.
In specific implementation, Montgomery Algorithm unit 402 includes：Second multiplier 4022, it is described for carrying out the second operation
Second operation includes：Computing module-square is carried out to the data bit.
In specific implementation, Montgomery Algorithm unit 402 further includes：First arithmetic device 4023, the first arithmetic device are used for
To the data bit carry out the computing module-square result carry out redundant operation, and using the result of the computing module-square as
The result of second operation.The first arithmetic device executes the duration of the redundant operation and first multiplier executes institute
The duration for stating modular multiplication is equal, and the first arithmetic device executes the power consumption of the redundant operation and first multiplier executes
The power consumption of the modular multiplication is equal.
In specific implementation, the first arithmetic device 4023 can be third multiplier, for the computing module-square
Result carry out modular multiplication.
In specific implementation, first multiplier 4021 executes the duration and described first of the primary computing module-square
The duration that multiplier 4021 executes the primary modular multiplication is equal.
In specific implementation, when waiting is set between the computing module-square and modular multiplication of first multiplier 4021
Long, waiting time is equal with the Montgomery Algorithm unit each occupied duration of data bit of acquisition.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (2)
1. a kind of Montgomery Algorithm method, which is characterized in that including：
Controller selects data flow to be treated, and will be in data flow storage to first memory；
Montgomery Algorithm device is successively read the data bit in first memory, when the value of the data bit is 1, carries out the first fortune
It calculates, and the result of the first operation is stored to second memory；When the value of the data bit is 0, the second operation is carried out, and will
The result of second operation is stored to second memory；The first operation of the progress includes：Mould square fortune is carried out to the data bit
It calculates, and modular multiplication is carried out to the result of the computing module-square；When carrying out first operation, in the computing module-square
Waiting time is set between the modular multiplication, and the waiting time is obtained with the Montgomery Algorithm device shared by each data bit
Duration is equal, and the duration for executing the primary computing module-square is equal with the primary duration of the modular multiplication is executed；Institute
Stating the second operation includes：Computing module-square is carried out to the data bit.
2. a kind of Montgomery Algorithm device, which is characterized in that including：
Control unit is stored for selecting data flow to be treated, and by the data flow to first memory；Montgomery Algorithm
Unit for obtaining the data bit in first memory successively, and judges the value of the data bit, when the data bit
Value when being 1, carry out the first operation, and by the storage of the result of the first operation to second memory；When the value of the data bit is 0
When, the second operation is carried out, and the result of the second operation is stored to second memory；The Montgomery Algorithm unit includes：First
Multiplier, first multiplier are used to carry out the first operation, including：Computing module-square is carried out to the data bit, and to institute
The result for stating computing module-square carries out modular multiplication；When carrying out first operation, in the computing module-square and the mould
Waiting time is set between multiplication, and the waiting time obtains each occupied duration of data bit with the Montgomery Algorithm device
Equal, the duration for executing the primary computing module-square is equal with the primary duration of the modular multiplication is executed；Second fortune
Including：Computing module-square is carried out to the data bit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310517942.2A CN104579650B (en) | 2013-10-28 | 2013-10-28 | The method and apparatus of Montgomery Algorithm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310517942.2A CN104579650B (en) | 2013-10-28 | 2013-10-28 | The method and apparatus of Montgomery Algorithm |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104579650A CN104579650A (en) | 2015-04-29 |
| CN104579650B true CN104579650B (en) | 2018-11-06 |
Family
ID=53094936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310517942.2A Active CN104579650B (en) | 2013-10-28 | 2013-10-28 | The method and apparatus of Montgomery Algorithm |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104579650B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1835207A (en) * | 2005-03-17 | 2006-09-20 | 联想(北京)有限公司 | Method of preventing energy analysis attack to RSA algorithm |
| CN101196964A (en) * | 2006-12-07 | 2008-06-11 | 上海安创信息科技有限公司 | Anti-bypass attack algorithm and chip thereof |
| CN101834723A (en) * | 2009-03-10 | 2010-09-15 | 上海爱信诺航芯电子科技有限公司 | RSA (Rivest-Shamirh-Adleman) algorithm and IP core |
-
2013
- 2013-10-28 CN CN201310517942.2A patent/CN104579650B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1835207A (en) * | 2005-03-17 | 2006-09-20 | 联想(北京)有限公司 | Method of preventing energy analysis attack to RSA algorithm |
| CN101196964A (en) * | 2006-12-07 | 2008-06-11 | 上海安创信息科技有限公司 | Anti-bypass attack algorithm and chip thereof |
| CN101834723A (en) * | 2009-03-10 | 2010-09-15 | 上海爱信诺航芯电子科技有限公司 | RSA (Rivest-Shamirh-Adleman) algorithm and IP core |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104579650A (en) | 2015-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6890615B2 (en) | Accelerator for deep neural networks | |
| CN103942181B (en) | Method, device for generating the configuration information of dynamic reconfigurable processor | |
| CN106415526B (en) | Fft processor and operation method | |
| CN104268018B (en) | Job scheduling method and job scheduler in a kind of Hadoop clusters | |
| JP2005527010A (en) | Method and apparatus for reducing power consumption of processing integrated circuits | |
| CN103970720A (en) | Embedded reconfigurable system based on large-scale coarse granularity and processing method of system | |
| CN101366003A (en) | Microloop computer instructions | |
| CN110738316A (en) | Operation method and device based on neural network and electronic equipment | |
| Singh et al. | Resource and throughput aware execution trace analysis for efficient run-time mapping on MPSoCs | |
| CN108205704A (en) | A kind of neural network chip | |
| CN104679663A (en) | Soft-partitioning of a register file cache | |
| Alekseeva et al. | Parallel multi‐core hyper‐heuristic GRASP to solve permutation flow‐shop problem | |
| Hu | Heuristics for solving continuous berth allocation problem considering periodic balancing utilization of cranes | |
| CN108319559A (en) | Data processing equipment for controlling vector memory access and method | |
| CN106325812B (en) | It is a kind of for the processing method and processing device for multiplying accumulating operation | |
| CN104364755B (en) | Accelerate the method and apparatus calculated for the parallel computation by intermediate strata operation | |
| CN104579651B (en) | The method and apparatus of elliptic curve cipher point multiplication operation | |
| CN104579763B (en) | A kind of network capacity extension method and apparatus | |
| CN104579650B (en) | The method and apparatus of Montgomery Algorithm | |
| RU2294561C2 (en) | Device for hardware realization of probability genetic algorithms | |
| CN103713944B (en) | A kind of processing method of Kernel-level thread, device and system | |
| CN108647007A (en) | Arithmetic system and chip | |
| CN102231624B (en) | Vector processor-oriented floating point complex number block finite impulse response (FIR) vectorization realization method | |
| CN103365821A (en) | Address generator of heterogeneous multi-core processor | |
| CN103493039A (en) | Data processing method and related device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |