CN104503730A - Instruction-based large-number point addition and point multiplication operation circuit and realization method - Google Patents
Instruction-based large-number point addition and point multiplication operation circuit and realization method Download PDFInfo
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Abstract
The invention discloses an instruction-based large-number point addition and point multiplication operation circuit, which comprises a basic operation circuit of a finite field operation layer, an operation command operation code register, an operand address register and an operation result address register, wherein the basic operation circuit carries out basic operation on an operand corresponding to an operand address stored in the operand address register according to an operation command operation code and an operation sequence stored in the operation command operation code register, and stores an operation result into an operation result address stored in the operation result address register. The invention also provides a realization method of the instruction-based large-number point addition and point multiplication operation circuit. The problem of the ordered calling of the finite field operation layer in a point addition and point multiplication operation process is solved, and the instruction-based large-number point addition and point multiplication operation circuit is simple in structure, is configurable in operation sequence and is convenient in upgrading an algorithm.
Description
Technical field
The present invention relates to microelectronics technology, particularly relate to that a kind of large several points based on instruction add, point doubling circuit and implementation method.
Background technology
At present based on the asymmetric cryptographic algorithm ECC(Elliptic Curve Cryptography of elliptic curves discrete logarithm problem in Galois field) be acknowledged as the public-key cryptosystem of most higher bit intensity, be widely used in the fields such as fast encrypt, key change, authentication, digital signature, secret communication.
SM2 ellipse curve public key cipher algorithm is as the one in ECC algorithm, and Cipher Strength is 256, and security is high, storage space is little, can complete signature fast, key change and encryption application.
The arithmetic logic that SM2 is relevant can be considered as independently unit and design, and adopts the dividing mode of stratification can be divided into finite field operations layer and elliptic curve operations layer.The major function of finite field operations layer is to provide the number theory computing support required for SM2 algorithm, comprises that 256 big integer moulds add, mould subtracts, mould is taken advantage of, mould is inverse, mould power, to compare.Elliptic curve operations layer is formed after the various basic operations of finite field operations layer sort according to certain rule, comprise a little add, times point, dot product, coordinate conversion.
In elliptic curve cryptosystem, its main operational is dot product, and dot product can be decomposed into two kinds of fundamental operations by us: point adds and doubly point, and point adds and can adopt different coordinate systems to realize with point doubling.Conventional coordinate system is affine coordinate system and Jacobi projected coordinate system.The present invention be applicable to radix Jacobian in prime field increase the weight of projective coordinate system under ellipse curve public key cipher algorithm.Under Jacobian increases the weight of projective coordinate system, make O point represent infinity point, in Galois field Fp, the upper Point addition operation definition of E (Fp) is as follows:
（1）O+O=O；
（2） P = x, y, z∈E(F
p) || O, P+O=O+P=P；
(3) P=x, y, z ∈ E (F
p) || the inverse element P=(u of O, P
2x, u
3y, uz), u ∈ F
pand u ≠ 0, P+ (-P)=O;
(4) set up an office P
1=(x
1, y
1, z
1) ∈ E (F
p) || O, P
2=(x
2, y
2, z
2) ∈ E (F
p) || O, P
3=P
1+ P
2=(x
3, y
3, z
3) ≠ O, if P
1≠ P
2, carry out point add operation, then:
λ
1= x
1z
2 2，λ
2= x
2z
1 2，λ
3= λ
1 λ
2，λ
4= y
1z
2 3，λ
5= y
2z
1 3，λ
6= λ
4 λ
5，
λ
7=λ
1+λ
2，λ
8 =λ
4+λ
5，x
3=λ
6 2 λ
7λ
3 2，λ
9=λ
7λ
3 2 2x
3，
y
3= (λ
9λ
6 λ
8λ
3 3) /2，z
3= z
1z
2λ
3；
If P 1=P2, carry out point doubling, then:
λ
1= 3x
1 2+ az
1 4，λ
2= 4x
1y
1 2，λ
3= 8y
1 4，x
3=λ
1 2 2λ
2，y
3=λ
1 (λ
2 x
3) λ
3，z
3= 2y
1z
1。
The performance of elliptic curve cryptography can be promoted to the optimization of algorithm sequence of operations and hardware resource scheduling mode.Adding for point as Chinese CN101782845A invention and doubly put algorithm, the point having rearranged the Jacobian coordinate points of amendment adds and point doubling sequence, proposes a kind of new method realizing point add operation and point doubling; As the computing formula that Chinese CN101221491A invention utilizes elliptic curve point under Jacobian coordinate system to add, extract separate operation, structure three class pipeline circuit structure; As the computing formula that Chinese CN101262345A invention utilizes elliptic curve under Jacobian coordinate system doubly to put, extract separate operation, structure three class pipeline circuit structure.Above implementation method adopts fixing sequence of operations, Shortcomings in system upgrade and expansibility.
Summary of the invention
In order to overcome the deficiencies in the prior art, the invention provides that a kind of large several points based on instruction add, point doubling circuit and implementation method, solve point add, in point doubling process for the problem of calling in order of finite field operations layer, structure is simple, order of operation is configurable, facilitates algorithm to upgrade.
For achieving the above object, the present invention takes following technical scheme:
A kind of large several point add operation circuit based on instruction, include confinement operation layer basic operations circuit, and algorithm operation register, operand address register, operating result address register, described basic operations circuit is according to the algorithm operational code stored in algorithm operation register and order of operation, the operand corresponding to the operand address stored in operand address register carries out basic operations, and operation result is stored to the operating result address place of operating result address register storage.
Further, the order structure that operand address adopts form consistent with the addressing of address of operating result address, comprises operand place RAM selection instruction, the address ram instruction of operand place.
Further, the address ram instruction of operand place adopts the mode of indirect addressing, through address instruction parser circuitry, searches the address corresponding to present instruction.
Further, described algorithm operation register, operand address register, operating result address register are Non-pe-riodic shift register; Preferably, described basic operations circuit comprises that mould adds computing circuit, mould subtracts computing circuit and scale multiplying circuit.
A kind of large several times point processing circuit based on instruction, include confinement operation layer basic operations circuit, and algorithm operation register, operand address register, operating result address register, described basic operations circuit is according to the algorithm operational code stored in algorithm operation register and order of operation, the operand corresponding to the operand address stored in operand address register carries out basic operations, and operation result is stored to the operating result address place of operating result address register storage.
Further, the order structure that operand address adopts form consistent with the addressing of address of operating result address, comprises operand place RAM selection instruction, the address ram instruction of operand place.
Further, the address ram instruction of operand place adopts the mode of indirect addressing, through address instruction parser circuitry, searches the address corresponding to present instruction.
Further, algorithm operation register, operand address register, operating result address register are Non-pe-riodic shift register; Preferably, described basic operations circuit comprises that mould adds computing circuit, mould subtracts computing circuit and scale multiplying circuit.
Large several points based on instruction add, a point doubling circuit implementing method, comprise the steps:
(1) CPU writes performed algorithm operational code, operand address, operating result address successively to algorithm operation register, operand address register, operating result address register;
(2) addressing extract operand address register current operation operand address respective operations number, then input in basic operations circuit corresponding to algorithm operation register current execution algorithm and carry out computing, and operation result is stored to operating result address register current operation result address place;
(3) algorithm operation register, operand address register, operating result address register move to left and enter executable operations next time, judge algorithm operation register current operation command operation code whether complete zero, if, represent that elliptic curve operations completes, otherwise, repeat step (2);
(4), after elliptic curve operations completes, algorithm operation register produces this computing of look-at-me notice CPU and completes, and algorithm operation register, operand address register, operating result address register turn back to default conditions.
Preferably, basic operations circuit comprises that mould adds computing circuit, mould subtracts computing circuit and scale multiplying circuit; Described algorithm operation register comprises three command operation codes, and corresponding mould adds computing circuit respectively, mould subtracts computing circuit and scale multiplying circuit.
Beneficial effect: (1) the present invention adopts self-defining arithmetic operation code, address operand, constructs built-in command, and data operation process is carried out in steps according to instruction, avoids address conflict, simplifies the design complexities of computing circuit.
(2) in conventional arithmetic circuit method for designing, in calculating process, the order of operation in each stage is generally fixing, if after subsequent algorithm upgrading, primary circuit can not be directly applied for new algorithm, need to redesign former hardware circuit, add design cost and research and development of products cycle.In the method, adopt existing order of operation to complete a little to add, times point operation, operation register elemental area opens to CPU simultaneously, and software only needs to reconfigure arithmetic operation Code memory, address function Code memory, i.e. adjustable order of operation, facilitates algorithm to upgrade.
(3) the present invention is in the overall process of carrying out computing, and CPU does not need to participate in, and only before computing starts, writes raw data, and read operation result after computing completes, reduce the load to CPU.
(4) adopt the mode of indirect addressing in the present invention, resolving electricity by address code and resolve address operand, by redefining the rule of correspondence of address code and actual address, can carry out flexible configuration under different applied environments, circuit structure is changed little.
Accompanying drawing explanation
Fig. 1 is that the large several points based on instruction provided by the invention add, point doubling schematic block circuit diagram.
Fig. 2 is the basic format of algorithm operational code of the present invention.
Fig. 3 is the basic format of address operand of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
The present invention be applicable to radix Jacobian in prime field increase the weight of projective coordinate system under SM2 ellipse curve public key cipher algorithm.Complete that SM2 point adds, point doubling, need repeatedly to call finite field operations layer, but different algorithm realization, adopt call order and inconsistent, the point therefore needing a kind of extendability strong adds, point doubling mode.
As shown in Figure 1, a kind of large several points based on instruction provided by the invention add, point doubling circuit, comprise algorithm operation register, operand address register, operating result address register, and the mould in finite field operations layer adds computing circuit, mould subtracts computing circuit and scale multiplying circuit, preferably computing circuit is added with mould in the present embodiment, mould subtracts computing circuit and scale multiplying circuit realizes the various basic operations of finite field operations layer as basic processing unit, in actual use procedure, can increase or reduce the number of times calling basic operations unit as required, and each basic operations unit in the present embodiment can adopt all hardware logic unit realizing its calculation function, such as mould adds device, mould subtracts device or modular multiplier, in addition, all hardware logic structures realizing its calculation function can also be adopted between each basic operations unit.
The present invention is by self-built instruction: algorithm operational code, operand address, operating result address, is stored in algorithm operation register, operand address register, operating result address register respectively, wherein:
Algorithm operational code is represented by 2 bit signals, represents that point adds and/or point doubling order, the rule of correspondence: " 01 " represents that carrying out mould to two operands adds computing; " 10 " represent that carrying out mould to two operands subtracts computing; " 11 " expression carries out modular multiplication to two operands; " 00 " represents that current elliptic curve operations completes, as shown in table 1.
Table 1 algorithm operational code
| Coding (b) | 00 | 01 | 10 | 11 |
| Computing | Stop | Mould adds | Mould subtracts | Mould is taken advantage of |
Point adds, point doubling is dual-operand computing, so operand address is made up of operand a address and operand b address two parts, by result write operation result address after computing completes.The order structure that addressing of address involved by this method all adopts form consistent, comprises operand place RAM selection instruction, the address ram instruction of operand place.That is the operating result that operating result address stores still can extract as the operand of computing next time.
As shown in table 2, operand place RAM selection instruction is represented by 2 bit signals, the rule of correspondence: " 00 " selects RAM_A to read and write; " 01 " selects RAM_B to read and write; " 10 " select RAM_M to read and write; " 11 " select RAM_R to read and write.
Table 2 operand place RAM selection instruction
| Coding (b) | 00 | 01 | 10 | 11 |
| Sheet selects | RAM_A | RAM_B | RAM_M | RAM_R |
As shown in table 3, the address ram instruction of operand place is represented by 3 bit signals, the rule of correspondence: " 000 " selects `h00-1c in current RAM to read and write address; " 001 " selects `h20-3c in current RAM to read and write address; " 010 " selects `h40-5c in current RAM to read and write address; " 011 " selects `h60-7c in current RAM to read and write address; " 100 " select `h80-9c in current RAM to read and write address; " 101 " select `ha0-bc in current RAM to read and write address.
The address ram instruction of table 3 operand place
| Coding (b) | 000 | 001 | 010 | 011 | 100 | 101 |
| Address (h) | `h00-1c | `h20-3c | `h40-5c | `h60-7c | `h80-9c | ‘ha0-bc |
Explanation for the address ram instruction of operand place adopts the mode of indirect addressing, first through address instruction parser circuitry, finds the address corresponding to present instruction.This addressing mode, more flexibly.By building an address code parser circuitry, for different application environment, flexible configuration can be carried out, only needing the rule of correspondence redefining address code and actual address.
The basic format of command operation code as shown in Figure 2, is made up of Non-pe-riodic shift register, the arithmetic type of the current execution of 0x28 and 0,x27 two bit representation, the next arithmetic type that will perform of 0x26 and 0,x25 two bit representation.After current operation completes, register moves to left two, and low level is by " 00 " polishing.When 0x28 and 0,x27 two is " 00 ", represent that current elliptic curve operations completes.
The basic format of address operand as shown in Figure 3, is made up of 6 groups of Non-pe-riodic shift registers.Operand RAM selects position, the current RAM of 0x28 and 0,x27 two bit representation; Operand address selects position, the position of operand in the current RAM of 0x3c, 0x3b and 0x3a tri-bit representation.
Command operation code and address operand, adopt regular length, is conducive to simplifying hardware design and reducing instruction decode time; Meanwhile, after CPU reads operation result, remove this computing complement mark position, operational code turns back to default conditions, prepares new round computing.
Algorithm operation register in this method and address register, can be configured by CPU, is written in corresponding registers by algorithm operational code and order of operation and operand access address, and meet the requirement of algorithm upgrading, expansion is strong.And point adds, point doubling can directly be performed by hardware, participates in calculating process without the need to software, and computing completes post command operation register and produces look-at-me, this computing of notice CPU completes.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. the large several point add operation circuit based on instruction, include confinement operation layer basic operations circuit, it is characterized in that: also comprise algorithm operation register, operand address register, operating result address register, described basic operations circuit is according to the algorithm operational code stored in algorithm operation register and order of operation, the operand corresponding to the operand address stored in operand address register carries out basic operations, and operation result is stored to the operating result address place of operating result address register storage.
2. a kind of large several point add operation circuit based on instruction according to claim 1, it is characterized in that: the order structure that described operand address adopts form consistent with the addressing of address of operating result address, comprise operand place RAM selection instruction, the address ram instruction of operand place.
3. a kind of large several point add operation circuit based on instruction according to claim 2, is characterized in that: the address ram instruction of described operand place adopts the mode of indirect addressing, through address instruction parser circuitry, searches the address corresponding to present instruction.
4. a kind of large several point add operation circuit based on instruction according to claim 1, is characterized in that: described algorithm operation register, operand address register, operating result address register are Non-pe-riodic shift register; Described basic operations circuit comprises that mould adds computing circuit, mould subtracts computing circuit and scale multiplying circuit.
5. the large several times point processing circuit based on instruction, include confinement operation layer basic operations circuit, it is characterized in that: also comprise algorithm operation register, operand address register, operating result address register, described basic operations circuit is according to the algorithm operational code stored in algorithm operation register and order of operation, the operand corresponding to the operand address stored in operand address register carries out basic operations, and operation result is stored to the operating result address place of operating result address register storage.
6. a kind of large several times point processing circuit based on instruction according to claim 5, it is characterized in that: the order structure that described operand address adopts form consistent with the addressing of address of operating result address, comprise operand place RAM selection instruction, the address ram instruction of operand place.
7. a kind of large several times point processing circuit based on instruction according to claim 6, is characterized in that: the address ram instruction of described operand place adopts the mode of indirect addressing, through address instruction parser circuitry, searches the address corresponding to present instruction.
8. a kind of large several times point processing circuit based on instruction according to claim 5, is characterized in that: described algorithm operation register, operand address register, operating result address register are Non-pe-riodic shift register; Described basic operations circuit comprises that mould adds computing circuit, mould subtracts computing circuit and scale multiplying circuit.
9. the large several points based on instruction described in claim 1 or 5 add, a point doubling circuit implementing method, it is characterized in that comprising the steps:
(1) CPU writes performed algorithm operational code, operand address, operating result address successively to algorithm operation register, operand address register, operating result address register;
(2) addressing extract operand address register current operation operand address respective operations number, then input in basic operations circuit corresponding to algorithm operation register current execution algorithm and carry out computing, and operation result is stored to operating result address register current operation result address place;
(3) algorithm operation register, operand address register, operating result address register move to left and enter executable operations next time, judge algorithm operation register current operation command operation code whether complete zero, if, represent that elliptic curve operations completes, otherwise, repeat step (2);
(4) after elliptic curve operations completes, algorithm operation register produces look-at-me, and this computing of notice CPU completes, and algorithm operation register, operand address register, operating result address register turn back to default conditions.
10. a kind of large several times point processing circuit based on instruction according to claim 9, is characterized in that: described basic operations circuit comprises that mould adds computing circuit, mould subtracts computing circuit and scale multiplying circuit; Described algorithm operation register comprises three command operation codes, and corresponding mould adds computing circuit respectively, mould subtracts computing circuit and scale multiplying circuit.
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| CN112134704B (en) * | 2020-09-21 | 2022-04-01 | 中国电子科技网络信息安全有限公司 | Sm2 performance optimization implementing method |
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Application publication date: 20150408 |