CN104579630A - System random number generation method - Google Patents
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- CN104579630A CN104579630A CN201310512138.5A CN201310512138A CN104579630A CN 104579630 A CN104579630 A CN 104579630A CN 201310512138 A CN201310512138 A CN 201310512138A CN 104579630 A CN104579630 A CN 104579630A
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Abstract
The invention relates to an electronic device and discloses a system random number generation method. The system random number generation method disclosed by the invention comprises the following steps: obtaining a chip identifier which is saved in a set address in a one-time programmable (OTP) register; taking the obtained chip identifier as an initial seed number; generating a system random number according to the initial seed number and a set generator polynomial. Compared with the prior art, the system random number generation method has the advantages as follows: the initial seed number is the chip identifier, and as the chip identifier has the characteristics of uniqueness and irreplicability, a user can obtain the unique and irreplicable system random number.
Description
Technical field
The present invention relates to electronic device, particularly the generation method of system random number.
Background technology
Random number is the important tool that system is encrypted (such as system utilizes generating random number key), and therefore random number generator is the essential link of all encryption systems.The ability that random number generator must have safe enough goes to prevent the attack from outside or inside.Following is a list three the most basic security doctrines.
1) frequency and distance of swimming randomness, the output of maker will have randomness, meets frequency test and distance of swimming test, ensures safety for the long distance of swimming with spying to attack;
2) reconstruct recovery/forward security, even if know the state of maker in a certain particular moment, the output number before maker at the moment can not be inferred thus;
3) intrusion prediction/backward security, even if know the state of maker in a certain particular moment, can not infer the output number that maker is later at the moment thus.
Mainly contain at present and generate random number by real hardware random number generator, and generate random number two kinds of modes by the Pseudo-random number generator of software simulating.Being generated the mode of random number by real hardware random number generator, can be the patent document of " 201010559971.1 ", " 201020624542.3 " see application number.
The Pseudo-random number generator of real hardware random number generator and software simulating is diverse.The former uses hardware implementing purely, and for identical input, each result is all completely unpredictable; The latter is easy to software simulating, can obtain statistical random number, but algorithm realization open after, same input can obtain same output, is difficult to accomplish that algorithm random number sequence is not reproducible, can not ensure the uniqueness of random number sequence.
Summary of the invention
The object of the present invention is to provide a kind of system random number generation method, make user can obtain unique and not reproducible system random number.
For solving the problems of the technologies described above, the invention provides a kind of system random number generation method, comprising following steps:
Obtain and be kept in one-off programming OTP register the chip identifier set in address;
Using the chip identifier of described acquisition as initial seed number;
Generator polynomial according to described initial seed number and setting generates described system random number.
Embodiment of the present invention in terms of existing technologies, chip identifier in address is set as " initial seed number " to obtain to be kept in one-off programming OTP register, user ID in OTP register is written to as " generator polynomial ", according to described initial seed number and generator polynomial generation system random number using user.Because described chip identifier has uniqueness and not reproducible characteristic, make user can obtain unique and not reproducible system random number.
In addition, before acquisition is kept in one-off programming OTP register the chip identifier set in address, also following steps are comprised:
To the chip identifier in one-off programming OTP register be written to, carry out the computing of SHA SHA, obtain the chip identifier after described SHA encryption;
Chip identifier after described SHA encryption is written in the setting address in described OTP register;
The chip identifier of described acquisition is the chip identifier be written to after SHA encryption in described setting address.
In the present invention; the chip identifier of the encryption obtained after the chip identifier being written to OTP register is through SHA computing; the chip identifier of this encryption is different from the above-mentioned chip identifier be written in OTP register; therefore can be encrypted protection to the chip identifier be written in OTP register, prevent from being cracked.Meanwhile, SHA is a string message indefinite length, in addition specific algorithm process, be fixed the data of length, these data crack very difficult in theory, and Project Realization is also impossible, so it is not the chip identifier in the present invention is also unique, reproducible.
In addition, in the described chip identifier that will be written in OTP register, before carrying out the computing of SHA, also following steps are comprised:
Chip identifier in OTP register is written to as the first field using described, the second field after described first field is used for depositing position of rest, the 3rd field after described second field is for filling field, and each bit in described filling field is filled to 0;
The 4th field after described 3rd field is used to indicate the number of bits that described first field takies;
The bit length summation of described first field, the second field, the 3rd field and the 4th field is 512 bits;
In the described chip identifier that will be written in OTP register, carry out in the step of the computing of SHA, by 512 bits that described first field, the second field, the 3rd field and the 4th field form, carry out the computing of described SHA.
In SHA calculating process, because the data of input must be 512 bits, by the preparation process before above-mentioned SHA computing, just the first field, the second field, the 3rd field and the bit length summation integrated treatment of the 4th field can be become be applicable to 512 bits of SHA computing, ensure that operability and the accuracy of SHA computing.
In addition, chip identifier comprises the ID of user's setting and the ID of factory settings.Make in this way; as long as protect vendor code or personal code work; even know the research staff of whole design details; lack any one code; all can not crack said chip identifier; blank chip, the chip of specific Chip ID can not be rewritten as, than singly have a vendor code or personal code work coefficient of safety higher.
In addition, the chip identifier after described SHA encryption is written in the step in the setting address in described OTP register, comprises following sub-step:
In the data obtained after described SHA computing, get N number of bit of low level, described N is the bit length of the ID of described factory settings;
Described N number of bit is written to and is used for depositing in the field of the ID of factory settings in described OTP register; N1 bit of the low level in described N number of bit is written to being used in described OTP register deposit user setting ID field in; Wherein, described N1 is the bit length of the ID of described user setting.
Because the chip identifier information after using the computing of SHA algorithm can be written in OTP register in a certain order, and the field of the field of ID that in the present invention, in OTP register, user sets and the ID of factory settings has position one to one to deposit relation, this just provides guarantee for the accuracy of SHA algorithm, make whole calculating process in perfect order, the operation mistake caused because position relationship is incorrect is less likely to occur.
Accompanying drawing explanation
Fig. 1 is the flow chart according to the system random number generation method in first embodiment of the invention;
Fig. 2 is the flow chart according to the chip identifier wiring method in second embodiment of the invention;
Fig. 3 is the schematic diagram according to the chip identifier wiring method in second embodiment of the invention;
Fig. 4 is the data channel of the chip identifier according to the write OTP register in second embodiment of the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, persons of ordinary skill in the art may appreciate that in each execution mode of the present invention, proposing many ins and outs to make reader understand the application better.But, even without these ins and outs with based on the many variations of following execution mode and amendment, each claim of the application technical scheme required for protection also can be realized.
First execution mode of the present invention relates to a kind of system random number generation method.Idiographic flow as shown in Figure 1.
First be step 101, obtain initial seed number.This initial seed number is kept in one-off programming OTP register the chip identifier set in address, and this chip identifier has uniqueness and not reproducible characteristic.OTP register by electrical fuse e-Fuse, blow laser or fusing fuse realize, wherein e-Fuse type OTP register comprises the e-Fuse register of the e-Fuse register of coupling capacitance type, the e-Fuse register of series crystal cast and dielectric breakdown type.The OTP register feature that these modes realize is can only one-time write, can not rewrite, but can repeat sense data.
Then be step 102, obtain generator polynomial.
This generator polynomial can be written to the user ID in OTP register for user.
It should be noted that, step 101 and step 102 there is no clear and definite sequencing, both first can perform step 101, also first can perform step 102, and the two also can carry out simultaneously.
Finally step 103, generation system random number.According to the initial seed number obtained and generator polynomial generation system random number.
So far, whole generating random number process terminates.
Compared with prior art, chip identifier in address is set as " initial seed number " to obtain to be kept in one-off programming OTP register in the present invention, user ID in OTP register is written to as " generator polynomial " using user, and according to the initial seed number obtained and generator polynomial generation system random number.Because described chip identifier has uniqueness and not reproducible characteristic, make user can obtain unique and not reproducible system random number.
The step of various method divides above, just in order to be described clearly, can merge into a step or splitting some step, being decomposed into multiple step, when realizing as long as comprise identical logical relation, all in the protection range of this patent; To adding inessential amendment in algorithm or in flow process or introducing inessential design, but the core design not changing its algorithm and flow process is all in the protection range of this patent.
Second execution mode of the present invention relates to a kind of system random number generation method, and idiographic flow as shown in Figure 1.Second execution mode has done further refinement on the basis of the first execution mode, give concrete grammar chip identifier being write in OTP register and set in address, further illustrate the uniqueness of chip identifier and system random number and not reproducible characteristic.Specifically, before acquisition is kept in one-off programming OTP register the chip identifier set in address, comprises and chip identifier is written in OTP register the step set in address after SHA computing encryption.In the present embodiment, chip identifier (Chip ID) is write in OTP register set idiographic flow in address as shown in Figure 2.
First be step 201, obtain the Chip ID be written in OTP register through system interface.
This Chip ID comprises ID, ID, other self-defining ID of factory settings or the ID of its combination in any of user's setting, uses the combination of the ID of user's setting and the ID of factory settings in the present embodiment, as shown in Figure 3.Make in this way; as long as protect the ID of user's setting and the ID of factory settings; even know the research staff of whole design details; lack any one value; all can not crack said chip identifier; blank chip, the chip of specific Chip ID can not be rewritten as, than singly have a vendor code or personal code work coefficient of safety higher.
Obtain after the Chip ID be written in OTP register through system interface, need the process through a merging treatment, become certain order with the ID merging treatment of factory settings, for use in follow-up SHA computing for the ID that user is set.Specifically as shown in Figure 4:
First system interface is using numbering 1 in the ID(Fig. 4 be set by the user be written in OTP register) and factory settings ID(Fig. 4 in numbering 2) the Chip ID that forms is as the first field, as the numbering 3 in Fig. 4, then the second field after above-mentioned first field deposits position of rest, as the numbering 4 in Fig. 4, afterwards using the 3rd field after above-mentioned second field as be fill field, each bit in this filling field is filled to 0, as the numbering 5 in Fig. 4, finally using the 4th field after the 3rd field as the number of bits that takies of above-mentioned first field of instruction, as the numbering 6 in Fig. 4.
The bit length summation of above-mentioned first field, the second field, the 3rd field and the 4th field is 512 bits.
After above-mentioned merging process completes, SHA computing could be carried out to the value of these settings, in SHA calculating process, because the data of input must be 512 bits, by the preparation process before above-mentioned SHA computing, just the first field, the second field, the 3rd field and the bit length summation integrated treatment of the 4th field can be become be applicable to 512 bits of SHA computing, ensure that operability and the accuracy of SHA computing.
Then be step 202, use safety hashing algorithm SHA(Secure Hash Algorithm) the Chip ID of algorithm to setting carry out computing encryption.
SHA algorithm is a string set point indefinite length, and in addition specific algorithm process, is fixed the data of length, the Chip ID namely after encryption.
For the ID [31:0] of user's setting, as shown in Figure 4.
Assuming that the ID(that sets of user prepares write) initial data is 0XF66FAA55, the ID of the user's setting after SHA computing encryption is 0x8558c7b5d53fb052af498dcf9b17fb487fe877e9=SHA (F66FAA55), the value that is saved of actual write OTP register is 0x7fe877e9, the data read out by obtaining OTP register after SHA are 0x66c1e9f19a4891253a100e86cac4239a58604ad7=SHA (7fe877e9), and the ID that the user that software systems are read is arranged is 0x58604ad7.
Software thinks that write value efuse_pgm_word [103:72] (ID [31:0] of respective user setting) is 0xF66FAA55, but the actual save value efuse_pgm_real_word [103:72] of OTP register is 0x7FE877E9.
During system write OTP register, the ID [31:0] of the ID [143:0] of factory settings and user's setting must write at twice, and write data later could real write OTP register by SHA encryption.
The most important thing is that the process of SHA computing is unidirectional irreversible, encrypting the Chip ID obtained after using the ChipID of SHA algorithm to setting to carry out computing is different Chip ID with the original Chip ID be written in OTP register, when not knowing the ID initial data of ID initial data that user sets and factory settings, even the ID in known specific OTP register, also can not be replicated.
SHA algorithm comprises the many algorithms such as SHA160/224/256/384/512 and MD4/MD5/MD6 and realizes, crack that very difficult (namely current mathematical analysis theory has demonstrated current mathematical tool not by the analysis to encrypted data in theory, instead push away the initial data before cracking out encryption), Project Realization is impossible (namely cannot use force exhaustive mode, cracks out the initial data before encryption according to the data after encryption).Its feature is as follows:
1) pushing away former input data by data summarization is counter, is very difficult the theory of computation;
2) wanting to find two groups of different data to correspond to identical data summarization, is also very difficult the theory of computation;
3) any variation to input data, the data summarization having very high probability to cause it to produce is totally different.
The specific algorithm of SHA has been existing mature technology, does not repeat them here.
Then enter step 203, the Chip ID after SHA encryption is write in the setting address of OTP register.Specifically:
First the Chip ID after above-mentioned encryption, get N number of bit of low level, described N is the bit length of the ID of factory settings, above-mentioned N number of bit being written to being used in OTP register deposits in the field of the ID of factory settings again, then N1 bit of the low level in this N number of bit is written to being used in OTP register to deposit in the field of the ID of user's setting.Wherein, N1 is the bit length of the ID that user sets.
So far, ablation process terminates.
In the present embodiment, as shown in Figure 4, the field of the ID for depositing user's setting in OTP register, for the 72nd bit from low to high in this OTP register is to the 103rd bit, for depositing the field of the ID of factory settings, for the 104th bit from low to high in this OTP register is to the 247th bit.
Because the chip identifier information after using the computing of SHA algorithm can be written in OTP register in a certain order, and the field of the field of ID that in the present invention, in OTP register, user sets and the ID of factory settings has position one to one to deposit relation, this just provides guarantee for the accuracy of SHA algorithm, make whole calculating process in perfect order, the operation mistake caused because position relationship is incorrect is less likely to occur.
In present embodiment, the write of OTP register by electrical fuse e-Fuse, blow laser or fusing fuse realizes, wherein e-fuse type OTP register comprises the e-fuse register of the e-fuse register of coupling capacitance type, the e-fuse register of series crystal cast and dielectric breakdown type.The OTP register feature that these modes realize is can only one-time write, can not rewrite, but can sense data be repeated, if necessary, chip manufacturer also can write specific sequence number according to the needs of client, and like this, each chip can have one different No. ID, avoid being replicated, meet Chip ID and there is uniqueness and not modifiable requirement.
When needs generate random number, can according to the generator polynomial generation system random number being kept in OTP register the chip identifier set in address, setting.Identical with the first execution mode, do not repeat them here.
Compared with prior art, chip identifier in address is set as " initial seed number " to obtain to be kept in one-off programming OTP register in the present invention, user ID in OTP register is written to as " generator polynomial " using user, and according to the initial seed number obtained and generator polynomial generation system random number.Due to a string message that SHA is indefinite length, in addition specific algorithm process, is fixed the data of length, these data crack very difficult in theory, Project Realization is also impossible, so the chip identifier in the present invention is also unique, not reproducible.So, also there is using chip identifier as the system random number that " initial seed number " generates uniqueness and not reproducible characteristic, make user can obtain unique and not reproducible system random number.Persons of ordinary skill in the art may appreciate that the respective embodiments described above realize specific embodiments of the invention, and in actual applications, various change can be done to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (10)
1. a system random number generation method, is characterized in that, comprise following steps:
Obtain and be kept in one-off programming OTP register the chip identifier set in address;
Using the chip identifier of described acquisition as initial seed number;
Generator polynomial according to described initial seed number and setting generates described system random number.
2. system random number generation method according to claim 1, is characterized in that, described generator polynomial is the user ID that user is written in described OTP register.
3. system random number generation method according to claim 1, is characterized in that, before acquisition is kept in one-off programming OTP register the chip identifier set in address, also comprises following steps:
To the chip identifier in one-off programming OTP register be written to, carry out the computing of SHA SHA, obtain the chip identifier after described SHA encryption;
Chip identifier after described SHA encryption is written in the setting address in described OTP register;
The chip identifier of described acquisition is the chip identifier be written to after SHA encryption in described setting address.
4. system random number generation method according to claim 3, is characterized in that, in the described chip identifier that will be written in OTP register, before carrying out the computing of SHA, also comprises following steps:
Chip identifier in OTP register is written to as the first field using described, the second field after described first field is used for depositing position of rest, the 3rd field after described second field is for filling field, and each bit in described filling field is filled to 0;
The 4th field after described 3rd field is used to indicate the number of bits that described first field takies;
The bit length summation of described first field, the second field, the 3rd field and the 4th field is 512 bits;
In the described chip identifier that will be written in OTP register, carry out in the step of the computing of SHA, by 512 bits that described first field, the second field, the 3rd field and the 4th field form, carry out the computing of described SHA.
5. system random number generation method according to claim 3, is characterized in that,
Described chip identifier comprises the ID of user's setting and the ID of factory settings.
6. system random number generation method according to claim 5, is characterized in that,
The ID of described user setting and the ID of factory settings is obtained by system interface.
7. system random number generation method according to claim 5, is characterized in that, the chip identifier after described SHA encryption is written in the step in the setting address in described OTP register, comprises following sub-step:
In the data obtained after described SHA computing, get N number of bit of low level, described N is the bit length of the ID of described factory settings;
Described N number of bit is written to and is used for depositing in the field of the ID of factory settings in described OTP register; N1 bit of the low level in described N number of bit is written to being used in described OTP register deposit user setting ID field in; Wherein, described N1 is the bit length of the ID of described user setting.
8. system random number generation method according to claim 7, is characterized in that,
The field of ID for depositing user's setting in described OTP register, for the 72nd bit from low to high in this OTP register is to the 103rd bit;
The field of the ID for depositing factory settings in described OTP register, for the 104th bit from low to high in this OTP register is to the 247th bit;
Wherein, the lowest bit position in described OTP register is the 0th bit.
9. system random number generation method according to any one of claim 1 to 8, is characterized in that, described OTP register is the OTP register of any one type following:
Blow laser type OTP register, fusing fuse type OTP register, electrical fuse e-fuse type OTP register.
10. system random number generation method according to claim 9, is characterized in that,
Described e-fuse type OTP register comprises the e-fuse register of the e-fuse register of coupling capacitance type, the e-fuse register of series crystal cast and dielectric breakdown type.
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