CN105335679A - Serial number writing-in method and device - Google Patents
Serial number writing-in method and device Download PDFInfo
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- CN105335679A CN105335679A CN201510854521.8A CN201510854521A CN105335679A CN 105335679 A CN105335679 A CN 105335679A CN 201510854521 A CN201510854521 A CN 201510854521A CN 105335679 A CN105335679 A CN 105335679A
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- sequence number
- write
- memory address
- identification information
- write state
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K1/00—Methods or arrangements for marking the record carrier in digital fashion
- G06K1/12—Methods or arrangements for marking the record carrier in digital fashion otherwise than by punching
- G06K1/128—Methods or arrangements for marking the record carrier in digital fashion otherwise than by punching by electric registration, e.g. electrolytic, spark erosion
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Storage Device Security (AREA)
Abstract
The invention is suitable for the technical field of computers and provides a serial number writing-in method and device. The writing-in method includes the steps that a first memory address and a second memory address are set, the first memory address is used for storing a serial number, the second memory address is used for storing identification information, and the identification information represents the writing-in state of the serial number; when serial number writing-in indication information is received, the to-be-written-in serial number is written into the first memory address according to the identification information on the second memory address. The method avoids the situation that the serial number is written in repeatedly, the serial number does not need to be written into an OTP, the purpose that the unique serial number can be written in without the OTP is achieved so that verification operation based on the serial number can be achieved, and the chip encryption purpose is achieved.
Description
Technical field
The invention belongs to field of computer technology, particularly relate to a kind of wiring method and device of sequence number.
Background technology
OTP (OneTimeProgrammable, One Time Programmable) is a kind of type of memory, as the term suggests, after described OTP that program is burned, can not again modify to described program.OTP product (one-off programming product) refers to that inner program internal memory adopts the single-chip microcomputer of disposable programmable read only memory.
Existing product (such as car-mounted terminal) before use, all needs the unique sequence number reading product to carry out verification operation, is proved to be successful, provides rights of using.Therefore, producer is when producing product, and main employing has the IC chip of described OTP, is write in OTP by the sequence number of product.This sequence number once not erasable after write, thus achieves the verification operation based on sequence number.When in IC chip without OTP time, then cannot carry out sequence number setting, even if be written with sequence number, sequence number also can be wiped free of or there is multiple sequence number simultaneously in IC chip, sequence number as the unique identification of product, thus can not cannot realize the verification operation based on sequence number.
Summary of the invention
Given this, the embodiment of the present invention provides a kind of wiring method and device of sequence number, to realize without writing unique sequence number under OTP.
First aspect, provides a kind of wiring method of sequence number, and said write method comprises:
Arrange the first memory address and the second memory address, described first memory address is used for storage sequence number, and described second memory address is used for storaging mark information, and described identification information represents the write state of sequence number;
When receiving sequence number write indication information, according to the identification information on described second memory address, sequence number to be written is write to described first memory address.
Second invention, provides a kind of writing station of sequence number, and said write device comprises:
Arrange module, for arranging the first memory address and the second memory address, described first memory address is used for storage sequence number, and described second memory address is used for storaging mark information, and described identification information represents the write state of sequence number;
Writing module, for when receiving sequence number write indication information, writes to described first memory address according to the identification information on described second memory address by sequence number to be written.
Compared with prior art, the embodiment of the present invention distributes the first memory address and the second memory address in product chips; Described first memory address is used for storage sequence number, and described second memory address is for storing the identification information of the write state showing sequence number; When receiving sequence number write indication information, according to the identification information on described second memory address, sequence number to be written is write to described first memory address; Thus avoid repetition writing sequence number, and without the need to writing in OTP, achieving and also can write unique sequence number without under OTP, to realize the verification operation based on sequence number, reach the object to chip encryption.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the realization flow figure of the wiring method of the sequence number that the embodiment of the present invention provides;
Fig. 2 is the realization flow figure of step S102 in the wiring method of the sequence number that the embodiment of the present invention provides;
Fig. 3 is the composition structural drawing of the writing station of the sequence number that the embodiment of the present invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The embodiment of the present invention distributes the first memory address and the second memory address in product chips; Described first memory address is used for storage sequence number, and described second memory address is for storing the identification information of the write state showing sequence number; When receiving sequence number write indication information, according to the identification information on described second memory address, sequence number to be written is write to described first memory address; Thus avoid repetition writing sequence number, and without the need to writing in OTP, achieving and also can write unique sequence number without under OTP, to realize the verification operation based on sequence number, reach the object to chip encryption.The embodiment of the present invention additionally provides corresponding device, is described in detail respectively below.
Fig. 1 shows the realization flow of the wiring method of the sequence number that the embodiment of the present invention provides.In embodiments of the present invention, said write method is applied to terminal device, is preferably computing machine.Described computing machine is used for the sequence number of product to write in the chip of product.Here, described sequence number is the numbering that product is corresponding, is arranged and write in the chip of product by producer.When user uses this product, carry out verification operation, to obtain rights of using by reading described sequence number.Wherein, described verification operation includes but not limited to rights of using etc. that identify product when connection server, that arrange client.
Consult Fig. 1, the wiring method of described sequence number comprises:
In step S101, the first memory address and the second memory address are set.
The embodiment of the present invention is distributed an address and is used for storage sequence number, i.e. the first memory address in the storer of chip; And distributing an address for storaging mark information, i.e. the second memory address, described identification information represents the write state of sequence number.Wherein, said write state comprises the write state of sequence number and the non-write state of sequence number.Here, described storer is the storer that FLASHROM etc. can be repeatedly erasable.
It should be noted that, the memory headroom that can not use when the first set memory address and the second memory address must be program operations.
In step s 102, when receiving sequence number write indication information, according to the identification information on described second memory address, sequence number to be written is write to described first memory address.
When receiving sequence number write indication information, first the identification information on the second memory address is obtained, to obtain current sequence number write state, and according to said write state, sequence number to be written write in described first memory address or do not write described sequence number.Thus avoid repetition writing sequence number, achieving without writing unique sequence number under OTP, making without the verification operation that also can realize under OTP based on sequence number.
As a preferred exemplary of the present invention, Fig. 2 shows the specific implementation flow process of the step S102 that the embodiment of the present invention provides.Here, the write state of sequence number and non-write state judge to obtain by preset value.
Consult Fig. 2, described step S102 comprises:
In step s 201, when receiving sequence number write indication information, the identification information on described second memory address is obtained.
In step S202, obtain the write state of sequence number according to described identification information.
In step S203, if when the write state of described sequence number is non-write state, obtain sequence number to be written, and described sequence number is write in described first memory address.
In embodiments of the present invention, the identification information on the second memory address has corresponding default value in default situations, such as 0xFFFFFFFF.If after writing sequence number, then described update of identification information is preset value, is such as updated to 0x00000001.Described preset value shows that current is sequence number write state.When receiving sequence number write indication information, by judging whether described identification information is the write state that preset value determines sequence number.If the identification information on the second memory address is not preset value, then shows that current sequence number write state is non-write state, sequence number to be written is write in described first memory address.Otherwise, when the identification information on the second memory address is preset value, show that current sequence number write state is for write state, then perform step S205.
Further, described method also comprises:
In step S204, after sequence number write, be write state by the update of identification information in described second memory address.
Further, step S102 also comprises:
In step S205, if the write state of described sequence number be write state time, the write operation of end sequence number, and export the failed information of write.
After writing sequence number, be write state by the update of identification information in the second memory address, be such as updated to above-mentioned preset value 0x00000001.When again receiving sequence number write indication information, then by repeated execution of steps S201, S202, S205, thus repetition writing sequence number can be avoided, and without the need to writing in OTP, achieve without writing unique sequence number under OTP, solve without the problem that cannot write unique sequence number under OTP, make without the verification operation that also can realize under OTP based on sequence number.
Fig. 3 shows the composition structure of the writing station of the sequence number that the embodiment of the present invention provides, and for convenience of explanation, illustrate only the part relevant to the invention process.
In embodiments of the present invention, said write device, for realizing the wiring method of the sequence number described in above-mentioned Fig. 1 or Fig. 2 embodiment, can be the unit being built in the software unit of terminal device, hardware cell or software and hardware combining.Described terminal device is preferably computing machine.In embodiments of the present invention, described computing machine is used for the sequence number of product to write in the chip of product.Described sequence number is the numbering that product is corresponding, is arranged and write in the chip of product by producer.When user uses this product, carry out verification operation, to obtain rights of using by reading described sequence number.Wherein, described verification operation includes but not limited to identify product when connection server, arrange the rights of using etc. of client.
Consult Fig. 3, said write device comprises:
Arrange module 31, for arranging the first memory address and the second memory address, described first memory address is used for storage sequence number, and described second memory address is used for storaging mark information, and described identification information represents the write state of sequence number;
Writing module 32, for when receiving sequence number write indication information, writes to described first memory address according to the identification information on described second memory address by sequence number to be written.
Further, said write module 32 comprises:
First acquiring unit 321, for when receiving sequence number write indication information, obtains the identification information on described second memory address;
Second acquisition unit 322, for obtaining the write state of sequence number according to described identification information;
Writing unit 323, for when the write state of sequence number is non-write state, obtains sequence number to be written, and is write to by described sequence number in described first memory address; After sequence number write, be write state by the update of identification information in described second memory address.
Further, said write module 32 also comprises:
End unit 324, at the write state of described sequence number be write state time, the write operation of end sequence number, and export the failed information of write.
Wherein, described sequence number is the numbering that product is corresponding.
It should be noted that, device in the embodiment of the present invention may be used for the whole technical schemes realized in said method embodiment, the function of its each functional module can according to the method specific implementation in said method embodiment, its specific implementation process can refer to the associated description in above-mentioned example, repeats no more herein.
The embodiment of the present invention distributes the first memory address and the second memory address in product chips; Described first memory address is used for storage sequence number, and described second memory address is for storing the identification information of the write state showing sequence number; When receiving sequence number write indication information, according to the identification information on described second memory address, sequence number to be written is write to described first memory address; Thus avoid repetition writing sequence number, and without the need to writing in OTP, achieving and also can write unique sequence number without under OTP, to realize the verification operation based on sequence number, reach the object to chip encryption.
Those of ordinary skill in the art can recognize, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with the combination of electronic hardware or computer software and electronic hardware.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
Those skilled in the art can be well understood to, and for convenience and simplicity of description, the device of foregoing description and the specific works process of unit, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
In several embodiments that the application provides, should be understood that the writing station of disclosed sequence number and wiring method can realize by another way.Such as, device embodiment described above is only schematic, such as, the division of described module, unit, be only a kind of logic function to divide, actual can have other dividing mode when realizing, such as multiple unit or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, and the indirect coupling of device or unit or communication connection can be electrical, machinery or other form.
The described unit illustrated as separating component or can may not be and physically separates, and the parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed in multiple network element.Some or all of unit wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.
In addition, each functional unit in each embodiment of the present invention, module can be integrated in a processing unit, also can be that the independent physics of unit, module exists, also can two or more unit, module integration in a unit.
If described function using the form of SFU software functional unit realize and as independently production marketing or use time, can be stored in a computer read/write memory medium.Based on such understanding, the part of the part that technical scheme of the present invention contributes to prior art in essence in other words or this technical scheme can embody with the form of software product, this computer software product is stored in a storage medium, comprising some instructions in order to make a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium comprises: USB flash disk, portable hard drive, ROM (read-only memory) (ROM, Read-OnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disc or CD etc. various can be program code stored medium.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection domain of claim.
Claims (8)
1. a wiring method for sequence number, is characterized in that, said write method comprises:
Arrange the first memory address and the second memory address, described first memory address is used for storage sequence number, and described second memory address is used for storaging mark information, and described identification information represents the write state of sequence number;
When receiving sequence number write indication information, according to the identification information on described second memory address, sequence number to be written is write to described first memory address.
2. the wiring method of sequence number as claimed in claim 1, is characterized in that, described when receiving sequence number write indication information, according to the identification information on described second memory address, sequence number to be written is write to described first memory address and comprises:
When receiving sequence number write indication information, obtain the identification information on described second memory address;
The write state of sequence number is obtained according to described identification information;
If when the write state of sequence number is non-write state, obtain sequence number to be written, and described sequence number is write in described first memory address;
After sequence number write, be write state by the update of identification information in described second memory address.
3. the wiring method of sequence number as claimed in claim 2, it is characterized in that, said write method also comprises:
If the write state of described sequence number be write state time, the write operation of end sequence number, and export the failed information of write.
4. the wiring method of the sequence number as described in any one of claims 1 to 3, is characterized in that, described sequence number is the numbering that product is corresponding.
5. a writing station for sequence number, is characterized in that, said write device comprises:
Arrange module, for arranging the first memory address and the second memory address, described first memory address is used for storage sequence number, and described second memory address is used for storaging mark information, and described identification information represents the write state of sequence number;
Writing module, for when receiving sequence number write indication information, writes to described first memory address according to the identification information on described second memory address by sequence number to be written.
6. the writing station of sequence number as claimed in claim 5, it is characterized in that, said write module comprises:
First acquiring unit, for when receiving sequence number write indication information, obtains the identification information on described second memory address;
Second acquisition unit, for obtaining the write state of sequence number according to described identification information;
Writing unit, for when the write state of sequence number is non-write state, obtains sequence number to be written, and is write to by described sequence number in described first memory address; After sequence number write, be write state by the update of identification information in described second memory address.
7. the writing station of sequence number as claimed in claim 6, it is characterized in that, said write module also comprises:
End unit, at the write state of described sequence number be write state time, the write operation of end sequence number, and export the failed information of write.
8. the writing station of the sequence number as described in any one of claim 5 to 7, is characterized in that, described sequence number is the numbering that product is corresponding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510854521.8A CN105335679A (en) | 2015-11-30 | 2015-11-30 | Serial number writing-in method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510854521.8A CN105335679A (en) | 2015-11-30 | 2015-11-30 | Serial number writing-in method and device |
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| CN105335679A true CN105335679A (en) | 2016-02-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510854521.8A Pending CN105335679A (en) | 2015-11-30 | 2015-11-30 | Serial number writing-in method and device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107341411A (en) * | 2017-06-13 | 2017-11-10 | 广州视源电子科技股份有限公司 | The product ID generation method and device of a kind of electronic equipment |
| CN111131291A (en) * | 2019-12-30 | 2020-05-08 | 广东中鹏热能科技有限公司 | Protocol implementation method using upper computer software as lower computer equipment |
| CN112613081A (en) * | 2020-12-10 | 2021-04-06 | 深圳市时创意电子有限公司 | Memory chip sequence code generation method and device, electronic equipment and storage medium |
| CN112950236A (en) * | 2021-03-31 | 2021-06-11 | 四川虹美智能科技有限公司 | Serial number writing method and device and computer readable medium |
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| CN112950236A (en) * | 2021-03-31 | 2021-06-11 | 四川虹美智能科技有限公司 | Serial number writing method and device and computer readable medium |
| CN112950236B (en) * | 2021-03-31 | 2023-05-23 | 四川虹美智能科技有限公司 | Sequence number writing method, device and computer readable medium |
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