CN104579321A - Phase-locked loop built-in test structure for quickly detecting catastrophic failure - Google Patents
Phase-locked loop built-in test structure for quickly detecting catastrophic failure Download PDFInfo
- Publication number
- CN104579321A CN104579321A CN201510001477.6A CN201510001477A CN104579321A CN 104579321 A CN104579321 A CN 104579321A CN 201510001477 A CN201510001477 A CN 201510001477A CN 104579321 A CN104579321 A CN 104579321A
- Authority
- CN
- China
- Prior art keywords
- phase
- input
- output
- locked loop
- mode setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a phase-locked loop built-in test structure for quickly detecting a catastrophic failure. The phase-locked loop built-in test structure comprises three delay units, two mode setting units and a test evaluation unit. The delay units are used for conducting different delay on reference signals to provide charge-discharge test signals needed by catastrophic failure testing. The mode setting units are used for setting the working modes, namely the normal working mode, the charging failure test mode and the discharging failure test mode for an entire circuit. The test evaluation unit is used for scanning the output signals of a frequency divider in a phase-locked loop to be detected and outputting the output signals in a digital mode, and the output signals are used as the basis for judging whether the catastrophic failure exists in the phase-locked loop or not. The phase-locked loop built-in test structure for quickly detecting the catastrophic failure has the advantages of being simple in test structure, short in test time and low in test cost.
Description
Technical field
The present invention relates to a kind of phase locking loop built-in test structure for fast detecting bust, under the prerequisite not affecting phase-locked loop performance to be measured, the fast detecting of the bust to phase-locked loop can be realized.
Background technology
Phase-locked loop can produce the mixed signal module of reference signal or clock signal as one, be widely used in radio communication, optical fiber link, microcomputer and various communication equipments etc., have vital impact to the performance of whole electronic system, therefore needs its performance of correct verification.But, due to closed loop feedback and the mixed signal characteristic of phase-locked loop itself, become one of circuit of the most difficult test.Especially during volume production test, expensive fine measuring instrument, the longer testing time, unacceptable testing cost, and external equipment is on the impact of phase-locked loop performance to be measured, had a strong impact on production cost and the Time To Market of electronic product, therefore, the low cost QuickTest solution of research phase-locked loop circuit is significant.
PLL fault testing method mainly detects the bust existed in phase-locked loop, thus filters out rapidly the phase-locked loop that can not satisfy the demands.The bust of phase-locked loop generally refers to the fault caused by defect existed in the structure by phase-locked loop circuit, as transistor gate source short, grid drain electrode open circuit, capacitance-resistance open circuit short circuit etc.These faults often impact the performance of phase-locked loop, as caused the skew of phase-lock-ring output frequency, and the increase of shake, the change of locking time, change of reference spur etc.Can judge that whether phase-locked loop is qualified fast by detecting these changes of monitoring.And due to the fault testing method of phase-locked loop, usually can utilize the circuit structure existed in phase-locked loop, therefore general test cost is lower.During volume production test, bust detects the highly effective method of one becoming fast and low-cost phase locked loop.
The bust method of testing of phase-locked loop must be noted that following 4 points: 1, built-in testing is to avoid the great number testing expense of outside high-end fine measuring instrument generation; 2, even can not have any impact to the performance impact of phase-locked loop is less, inappropriate built-in detecting circuit can affect the normal work of qualified phase-locked loop on the one hand, also the accuracy rate of test can be reduced on the other hand, some common solutions open loop as tried not, and try not to open loop etc. in analog node; 3, digital test circuit and test export, more reliable to ensure the result of testing, and Output rusults is convenient to viewing, does not need or only needs general tester to watch; 4, testing time and testing cost is reduced, phase-locked loop is as mixed signal circuit unique in most of SOC (system on a chip), its testing time, testing cost directly affects production cost and the Time To Market of electronic product, and the volume production testing scheme of fast and low-cost is badly in need of in the test of current phase-locked loop.
As summary, the bust test of fast and low-cost is applicable to the volume production test of phase-locked loop very much.Therefore, research be applicable to phase-locked loop volume production test, there is the phase-locked loop bust testing scheme that test structure is simple, the testing time is fast, testing cost is low there is great Research Significance.
Summary of the invention
Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides a kind of phase locking loop built-in test structure for fast detecting bust, has the advantages that test structure is simple, the testing time is fast, testing cost is low; Automatically can complete the bust test of phase-locked loop, discharge underproof phase-locked loop when producing in batches rapidly.
Technical scheme: for achieving the above object, the technical solution used in the present invention is:
For a phase locking loop built-in test structure for fast detecting bust, put the logic level values that in phase-locked loop to be measured, frequency divider exports, to judge whether phase-locked loop to be measured exists bust for detecting certain several set time; Comprise three delay cells, two mode setting unit and a testing evaluation unit; Delay cell carries out different time delays for realizing Reference Signal, to provide the charge-discharge test signal needed for bust test; Mode setting unit for arranging the mode of operation of whole circuit, i.e. normal mode of operation, charge fault test pattern and discharge fault test pattern; Testing evaluation unit for scanning the output signal of frequency divider in phase-locked loop to be measured, and exports in digital form, as judging whether phase-locked loop exists the foundation of bust;
Remember that three delay units are respectively the first delay unit Delay1, the second delay unit Delay2 and the 3rd delay unit Delay3, two mode setting unit are respectively first mode setting unit MODE1 and the second mode setting unit MODE2, and testing evaluation unit comprises a d type flip flop DFF;
Reference signal inputs the input of the S1 input of first mode setting unit MODE1, the input of the first delay unit Delay1 and the 3rd delay unit Delay3 respectively, test signal connects the input end of clock of d type flip flop DFF, first mode selects signal to connect the SET control end of first mode setting unit MODE1, and the second mode select signal connects the SET control end of the second mode setting unit MODE2;
The input of the output termination second delay unit Delay2 of the first delay unit Delay1, the S2 input of the output termination first mode setting unit MODE1 of the second delay unit Delay2, the output OUT1 of first mode setting unit MODE1 receives the reference input REF surveying phase-locked loop; The S1 input of the output termination second mode setting unit MODE2 of the 3rd delay unit Delay3, the frequency divider output DBN_out of phase-locked loop to be measured connects the S2 input of the second mode setting unit MODE2, and the output OUT2 of the second mode setting unit MODE2 receives the feedback signal input terminal CLK surveying phase-locked loop.
This built-in testing structure, in conjunction with the part of the circuit existed in phase-locked loop to be measured as test circuit, saves the area overhead of test circuit, its test structure and simple; Further, the bust that this built-in testing structure can exist in fast detecting phase-locked loop, the monolithic testing time hundred nanosecond rank; Meanwhile, adopt built-in testing structure, can carry out surveying the bust existed in phase-locked loop without the need to any complex precise tester and detect, save the cost of test.Therefore there is the feature that test structure is simple, the testing time is fast, testing cost is low.
Described two mode setting unit are respectively first mode setting unit MODE1 and the second mode setting unit MODE2;
First mode setting unit MODE1, comprises the first inverter INV1, first and door AND1, second and door AND2 and first or door OR1; First inputs termination reference signal with the A of door AND1, and B inputs termination first mode and selects signal, exports the A input of termination first or door OR1; The input termination first mode of the first inverter INV1 selects signal, exports the A input of termination second and door AND2; Second inputs the output of termination first inverter INV1 with the A of door AND2, and B inputs the output of termination second delay unit Delay2, exports the B input of termination first or door OR1; First or the A of door OR1 input the output of termination first and door AND1, B inputs the output of termination second or door AND2, and the reference input REF of phase-locked loop is surveyed in output reception;
Second mode setting unit MODE2, comprise the second inverter INV2, the 3rd with door AND3, the 4th with door AND4, second or door OR2; 3rd inputs the output of termination the 3rd delay unit Delay3 with the A of door AND3, and B inputs termination second mode select signal, exports the A input of termination second or door OR2; Input termination second mode select signal of the second inverter INV2, exports the A input of termination the 4th and door AND4; 4th inputs the output of termination second inverter INV2 with the A of door AND4, and the frequency divider output DBN_out of phase-locked loop is surveyed in the reception of B input, exports the B input of termination second or door OR2; Second or the A of door OR2 input the output of termination the 3rd and door AND3, B inputs the output of termination the 4th or door AND4, and the feedback signal input terminal CLK of phase-locked loop is surveyed in output reception.
Described testing evaluation unit comprises a d type flip flop DFF, and the frequency divider output DBN_out of phase-locked loop is surveyed in the D input reception of d type flip flop DFF, and input end of clock connects test signal, and clear terminal CLR meets power vd D, exports Q end and is test output signal end.
Described phase-locked loop to be measured is charge pump phase lock loop, its reference input REF connects the output of first mode setting unit MODE1, feedback signal input terminal CLK connects the output of the second mode setting unit MODE2, frequency divider output DBN_out connects the S2 input of the second mode setting unit MODE2, phase-locked loop output output signal PLL_out to be measured.
Beneficial effect: the phase locking loop built-in test structure for fast detecting bust provided by the invention, automatically can complete the bust test of phase-locked loop, discharge underproof phase-locked loop when producing in batches rapidly; This built-in testing structure mainly comprises three delay cells, two mode setting unit and a testing evaluation unit, test structure and simple; This built-in testing structure, in conjunction with the part of the circuit existed in phase-locked loop to be measured as test circuit, saves the area overhead of test circuit; Because the test circuit additionally added only has done very little change to the digital circuits section of phase-locked loop, therefore less to the performance impact of phase-locked loop; Test exports as digital, only needs a tester the most general, avoids the high cost using complex precise tester to bring, saves the cost of test; And its bust that can exist in fast detecting phase-locked loop, the monolithic testing time hundred nanosecond rank, accelerate the time of test; In sum, the phase locking loop built-in test structure for fast detecting bust provided by the invention, has the advantages that test structure is simple, the testing time is fast, testing cost is low.
Accompanying drawing explanation
Fig. 1 is the phase locking loop built-in test structure schematic diagram for fast detecting bust of the present invention;
Fig. 2 is the test flow chart of the phase locking loop built-in test structure for fast detecting bust of the present invention;
Fig. 3 is that wherein 3 (a) is fault-free, there is DSS fault in 3 (b) charge pump, there is GSS fault in 3 (c) charge pump based on the test output detected for phase-locked loop bust of the present invention;
Fig. 4 is on the impact of surveying phase lock loop lock on time based on the phase locking loop built-in test structure for fast detecting bust of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Be illustrated in figure 1 a kind of phase locking loop built-in test structure for fast detecting bust, the logic level values that in phase-locked loop to be measured, frequency divider exports is put for detecting certain several set time, to judge whether phase-locked loop to be measured exists bust, concrete principle is as follows:
Wherein, θ
ins input that () is phase-locked loop, θ
outs output that () is phase-locked loop, K
dfor the gain of phase frequency detector, I
pfor the electric current of charge pump, K
vCOfor the gain of voltage controlled oscillator VCO, the impedance that Z (s) is filter, N is the coefficient of frequency divider; Functional relation between being exported as can be seen from phase-locked loop and inputting, the output of phase-locked loop and each structural parameters of phase-locked loop are closely related, and therefore can disclose in these structures whether there is bust by the output observing phase-locked loop; That is, the bust owing to existing in phase-locked loop can affect the performance of phase-locked loop, therefore can be detected the bust of phase-locked loop by the skew of the frequency divider output frequency detecting phase-locked loop, thus discharge underproof phase-locked loop rapidly.
This phase locking loop built-in test structure comprises three delay cells, two mode setting unit and a testing evaluation unit; Delay cell carries out different time delays for realizing Reference Signal, to provide the charge-discharge test signal needed for bust test; Mode setting unit for arranging the mode of operation of whole circuit, i.e. normal mode of operation, charge fault test pattern and discharge fault test pattern; Testing evaluation unit for scanning the output signal of frequency divider in phase-locked loop to be measured, and exports in digital form, as judging whether phase-locked loop exists the foundation of bust.When normal mode of operation, phase-locked loop to be measured completes clock generating function, provides the clock signal of system; When test pattern (charge fault test pattern and discharge fault test pattern), reference signal is through different delay units, phase-locked loop to be measured is inputed to produce the test and excitation signal with different initial phase, then by observing the skew of phase-lock-ring output frequency to be measured, come whether there is bust in testing circuit.
Remember that three delay units are respectively the first delay unit Delay1, the second delay unit Delay2 and the 3rd delay unit Delay3, two mode setting unit are respectively first mode setting unit MODE1 and the second mode setting unit MODE2, and testing evaluation unit comprises a d type flip flop DFF.The time of delay unbounded size system of three delay cells, only need be consistent.
Reference signal connects the S1 input of first mode setting unit MODE1, and the frequency divider output DBN_out of phase-locked loop to be measured connects the S2 input of the second mode setting unit MODE2; During normal mode of operation, these two signals are as the input of phase-locked loop to be measured, and phase-locked loop to be measured completes clock generating function.Reference signal connects the S1 input of first mode setting unit MODE1, and reference signal connects the S1 input of the second mode setting unit MODE2 through the second test signal that the 3rd delay unit Delay3 produces; During test job pattern, these two signals are as the input of phase-locked loop to be measured, and phase-locked loop to be measured completes charge fault measuring ability.Reference signal connects the S2 input of first mode setting unit MODE1 through the first test signal that the first delay cell Delay1 and the second delay cell Delay2 produces, and reference signal connects the S1 input of the second mode setting unit MODE2 through the second test signal that the 3rd delay unit Delay3 produces; During test job pattern, these two signals are as the input of phase-locked loop to be measured, and phase-locked loop to be measured completes discharge fault measuring ability.
Mode setting unit comprises first mode setting unit MODE1 and the second mode setting unit MODE2, and the structure of two mode setting unit is the same.First mode setting unit MODE1 comprises first mode setting unit MODE1, comprises the first inverter INV1, first and door AND1, second and door AND2 and first or door OR1.Second mode setting unit MODE2, comprise the second inverter INV2, the 3rd with door AND3, the 4th with door AND4, second or door OR2.Model selection 1 connects the SET input of first mode setting unit MODE1, model selection 2 connects the SET input of the second mode setting unit MODE2, both produce different logic level assembled state at combination, and corresponding normal mode of operation, charge fault detect test pattern and discharge examination test pattern three kinds of mode of operations respectively.
Testing evaluation unit comprises a d type flip flop DFF, and the D of d type flip flop DFF inputs the frequency divider output DBN_out that phase-locked loop is surveyed in termination reception, and input end of clock connects test signal.The frequency of test signal is set, makes it at some some regular time, scan the output of frequency divider in phase-locked loop to be measured, whether produce skew as the foundation judging whether to exist in phase-locked loop fault according to the frequency of frequency divider.The output of d type flip flop is digital, only the most general tester such as oscilloscope need be used to read.
Just in conjunction with example, the present invention is further illustrated below.
The work of this built-in testing structure is arranged:
(1) during normal mode of operation, reference signal connects the S1 input of first mode setting unit MODE1, the frequency divider output DBN_out of phase-locked loop to be measured connects the S2 input of the second mode setting unit MODE2, the frequency divider output DBN_out of phase-locked loop to be measured follows reference signal, final locking, phase-locked loop completes clock generating function.
(2) when test pattern charge fault detects, reference signal connects the S1 input of first mode setting unit MODE1 as the first test signal, reference signal connects the S1 input of the second mode setting unit MODE2 as the second test signal through the 3rd delay unit Delay3, advanced second test signal of initial phase of the first test signal, whole circuit structure completes the charge fault measuring ability of phase-locked loop to be measured.
(3) when test pattern discharge fault detects, reference signal connects the S2 input of first mode setting unit MODE1 as the first test signal through the first delay cell Delay1 and the second delay cell Delay2, reference signal connects the S1 input of the second mode setting unit MODE2 as the second test signal through the 3rd delay unit Delay3, the initial phase of the first test signal lags behind the second test signal, and whole circuit structure completes the discharge fault measuring ability of phase-locked loop to be measured.
(4) model selection 1 connects the SET input of first mode setting unit MODE1, and model selection 2 connects the SET input of the second mode setting unit MODE2.Model selection 1 is logic low, corresponding normal mode of operation when model selection 2 is logic high; Model selection 1 is logic low, corresponding charge fault test pattern when model selection 2 is logic low; Model selection 1 is logic high, corresponding discharge fault pattern when model selection 2 is logic low.
(5) testing evaluation unit comprises a d type flip flop DFF, and the D of d type flip flop DFF inputs the frequency divider output DBN_out that phase-locked loop is surveyed in termination reception, and input end of clock connects test signal.Arrange the frequency of test signal, make it scan the output of frequency divider in phase-locked loop to be measured respectively at 60ns, 310ns, 560ns and 810ns tetra-time points: as fault-free, test output is 11000100; If when there is DSS fault in charge pump, test output is 11000111; If when there is GSS fault in VCO, test output is 11111111.Test the difference exported when contrasting test output in all kinds of situation and fault-free, whether can there is bust in quick detection circuit.
Fig. 1 is the phase locking loop built-in test structure schematic diagram for fast detecting bust of the present invention.Fig. 2 is the test flow chart of the phase locking loop built-in test structure for fast detecting bust of the present invention.Fig. 3 is that wherein 3 (a) is fault-free, and test exports: 11000100 based on the test output detected for phase-locked loop bust of the present invention; There is DSS fault in 3 (b) charge pump, test exports: 11000111; There is GSS fault in 3 (c) charge pump, test exports: 11111111.Fig. 4 is on the impact of surveying phase lock loop lock on time based on the phase locking loop built-in test structure for fast detecting bust of the present invention.Table 1 is based on the phase locking loop built-in test structure for fast detecting bust of the present invention, corresponding various different fault category, the test Output rusults of each testing time point.Table 2 is the failure measure based on the phase locking loop built-in test structure for fast detecting bust of the present invention.
The test of each testing time point of table 1 exports
The failure measure of table 2 new type digital phase locking loop built-in of the present invention self-testing structure
As seen from Figure 1, phase locking loop built-in test structure for fast detecting bust of the present invention is full-digital circuit, and only needing several trigger and gate, the bust for phase-locked loop detects, and described built-in testing structure has the simple feature of test structure.
The test flow chart of the phase locking loop built-in test structure for fast detecting bust of the present invention, has three kinds of mode of operations as seen from Figure 2, and namely normal mode of operation, charge fault detect test pattern and discharge fault detection test pattern.
As can be seen from Fig. 3 and table 1, phase locking loop built-in test structure for fast detecting bust of the present invention, when there is various different types of fault during fault-free and in phase-locked loop circuit, it is different that test exports, and therefore can get rid of out of order phase-locked loop fast.Monolithic test time be hundred nanosecond rank.Therefore described built-in testing structure has testing time fast feature.And test result is digital, only the most general tester need be used to read, avoid the huge cost using high-end fine measuring instrument to bring, therefore described built-in testing structure has the low feature of testing cost.
As seen from Figure 4, the phase locking loop built-in test structure for fast detecting bust of the present invention is less to the performance impact of phase-locked loop to be measured.Use the phase locking loop built-in test structure for fast detecting bust of the present invention, and under not using two kinds of situations, the locking time of phase-locked loop to be measured is respectively 600ns and 550ns.
As can be seen from Table 2, the phase locking loop built-in test structure for fast detecting bust of the present invention, when carrying out bust to phase-locked loop to be measured and detecting, total fault coverage is 98.18%, and fault coverage is higher.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (4)
1. for a phase locking loop built-in test structure for fast detecting bust, it is characterized in that: put the logic level values that in phase-locked loop to be measured, frequency divider exports, to judge whether phase-locked loop to be measured exists bust for detecting certain several set time; Comprise three delay cells, two mode setting unit and a testing evaluation unit; Delay cell carries out different time delays for realizing Reference Signal, to provide the charge-discharge test signal needed for bust test; Mode setting unit for arranging the mode of operation of whole circuit, i.e. normal mode of operation, charge fault test pattern and discharge fault test pattern; Testing evaluation unit for scanning the output signal of frequency divider in phase-locked loop to be measured, and exports in digital form, as judging whether phase-locked loop exists the foundation of bust;
Remember that three delay units are respectively the first delay unit Delay1, the second delay unit Delay2 and the 3rd delay unit Delay3, two mode setting unit are respectively first mode setting unit MODE1 and the second mode setting unit MODE2, and testing evaluation unit comprises a d type flip flop DFF;
Reference signal inputs the input of the S1 input of first mode setting unit MODE1, the input of the first delay unit Delay1 and the 3rd delay unit Delay3 respectively, test signal connects the input end of clock of d type flip flop DFF, first mode selects signal to connect the SET control end of first mode setting unit MODE1, and the second mode select signal connects the SET control end of the second mode setting unit MODE2;
The input of the output termination second delay unit Delay2 of the first delay unit Delay1, the S2 input of the output termination first mode setting unit MODE1 of the second delay unit Delay2, the output OUT1 of first mode setting unit MODE1 receives the reference input REF surveying phase-locked loop; The S1 input of the output termination second mode setting unit MODE2 of the 3rd delay unit Delay3, the frequency divider output DBN_out of phase-locked loop to be measured connects the S2 input of the second mode setting unit MODE2, and the output OUT2 of the second mode setting unit MODE2 receives the feedback signal input terminal CLK surveying phase-locked loop.
2. the phase locking loop built-in test structure for fast detecting bust according to claim 1, is characterized in that: described two mode setting unit are respectively first mode setting unit MODE1 and the second mode setting unit MODE2;
First mode setting unit MODE1, comprises the first inverter INV1, first and door AND1, second and door AND2 and first or door OR1; First inputs termination reference signal with the A of door AND1, and B inputs termination first mode and selects signal, exports the A input of termination first or door OR1; The input termination first mode of the first inverter INV1 selects signal, exports the A input of termination second and door AND2; Second inputs the output of termination first inverter INV1 with the A of door AND2, and B inputs the output of termination second delay unit Delay2, exports the B input of termination first or door OR1; First or the A of door OR1 input the output of termination first and door AND1, B inputs the output of termination second or door AND2, and the reference input REF of phase-locked loop is surveyed in output reception;
Second mode setting unit MODE2, comprise the second inverter INV2, the 3rd with door AND3, the 4th with door AND4, second or door OR2; 3rd inputs the output of termination the 3rd delay unit Delay3 with the A of door AND3, and B inputs termination second mode select signal, exports the A input of termination second or door OR2; Input termination second mode select signal of the second inverter INV2, exports the A input of termination the 4th and door AND4; 4th inputs the output of termination second inverter INV2 with the A of door AND4, and the frequency divider output DBN_out of phase-locked loop is surveyed in the reception of B input, exports the B input of termination second or door OR2; Second or the A of door OR2 input the output of termination the 3rd and door AND3, B inputs the output of termination the 4th or door AND4, and the feedback signal input terminal CLK of phase-locked loop is surveyed in output reception.
3. the phase locking loop built-in test structure for fast detecting bust according to claim 1, it is characterized in that: described testing evaluation unit comprises a d type flip flop DFF, the frequency divider output DBN_out of phase-locked loop is surveyed in the D input reception of d type flip flop DFF, input end of clock connects test signal, clear terminal CLR meets power vd D, exports Q end and is test output signal end.
4. the phase locking loop built-in test structure for fast detecting bust according to claim 1, it is characterized in that: described phase-locked loop to be measured is charge pump phase lock loop, its reference input REF connects the output of first mode setting unit MODE1, feedback signal input terminal CLK connects the output of the second mode setting unit MODE2, frequency divider output DBN_out connects the S2 input of the second mode setting unit MODE2, phase-locked loop output output signal PLL_out to be measured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510001477.6A CN104579321A (en) | 2015-01-04 | 2015-01-04 | Phase-locked loop built-in test structure for quickly detecting catastrophic failure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510001477.6A CN104579321A (en) | 2015-01-04 | 2015-01-04 | Phase-locked loop built-in test structure for quickly detecting catastrophic failure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104579321A true CN104579321A (en) | 2015-04-29 |
Family
ID=53094665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510001477.6A Pending CN104579321A (en) | 2015-01-04 | 2015-01-04 | Phase-locked loop built-in test structure for quickly detecting catastrophic failure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104579321A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108847843A (en) * | 2018-05-23 | 2018-11-20 | 东南大学 | A kind of quadrature ring oscillator based on the enhanced feedforward of resistance |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1475891A1 (en) * | 2003-05-07 | 2004-11-10 | STMicroelectronics S.r.l. | Built-in self-test circuit for phase locked loops, test method and computer program product therefore |
| CN1763552A (en) * | 2004-10-21 | 2006-04-26 | 扬智科技股份有限公司 | Jitter signal circuit device of phase-locked loop for built-in self-test and method thereof |
| CN103986459A (en) * | 2014-04-24 | 2014-08-13 | 东南大学 | All-digital phase-locked loop built-in self-testing structure |
-
2015
- 2015-01-04 CN CN201510001477.6A patent/CN104579321A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1475891A1 (en) * | 2003-05-07 | 2004-11-10 | STMicroelectronics S.r.l. | Built-in self-test circuit for phase locked loops, test method and computer program product therefore |
| CN1763552A (en) * | 2004-10-21 | 2006-04-26 | 扬智科技股份有限公司 | Jitter signal circuit device of phase-locked loop for built-in self-test and method thereof |
| CN103986459A (en) * | 2014-04-24 | 2014-08-13 | 东南大学 | All-digital phase-locked loop built-in self-testing structure |
Non-Patent Citations (1)
| Title |
|---|
| CHUN-LUNG HSU ETC.: "Built-In Self-Test for Phase-Locked Loops", 《IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108847843A (en) * | 2018-05-23 | 2018-11-20 | 东南大学 | A kind of quadrature ring oscillator based on the enhanced feedforward of resistance |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106357266B (en) | Lock detecting circuit, method and phase lock circuitry | |
| CN102981063B (en) | Single event transient pulse method for measuring width and measurement mechanism, pulse generating device | |
| CN101106375B (en) | PLL device and current compensation method | |
| CN103986459B (en) | All-digital phase-locked loop built-in self-testing structure | |
| CN107202951B (en) | SoC on piece NBTI degeneration detection system | |
| CN102565676B (en) | Automation measuring apparatus for crystal oscillator parameters | |
| CN101655544A (en) | Device for measuring and checking errors of digital mutual inductor | |
| CN105790736B (en) | It is a kind of to trim device for frequency signal generation chip | |
| Chan et al. | A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line | |
| CN101834601B (en) | Method and apparatus for determining peak phase error between clock signals | |
| CN104931863B (en) | Synchronous generator for cable local discharge test | |
| CN110515292B (en) | TDC circuit based on bidirectional running annular carry chain and measuring method | |
| CN103954946B (en) | A kind of TR assembly debugging instrument | |
| CN108120919A (en) | A kind of integrated circuit time parameter test circuit and method | |
| CN110887992A (en) | Clock frequency detection circuit | |
| CN106932745A (en) | Calibration circuit and system | |
| CN113092858A (en) | High-precision frequency scale comparison system and comparison method based on time-frequency information measurement | |
| CN109856525A (en) | A kind of circuit aging detection sensor based on look-up table | |
| US20150249453A1 (en) | Fast on-chip oscillator trimming | |
| CN104579321A (en) | Phase-locked loop built-in test structure for quickly detecting catastrophic failure | |
| Hsu et al. | Built-in self-test for phase-locked loops | |
| CN104569786A (en) | Embedded test method of phase-locked loop circuits | |
| CN106027044B (en) | A kind of polycyclic frequency synthesizer predetermined frequency automated calibration system and method | |
| US20220187350A1 (en) | Test method for high-speed signal frequency measurement and signal integrity | |
| CN107255748A (en) | A kind of data signal measurement and generator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150429 |
|
| RJ01 | Rejection of invention patent application after publication |