CN104576902B - A kind of LED structure and preparation method thereof - Google Patents
A kind of LED structure and preparation method thereof Download PDFInfo
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- CN104576902B CN104576902B CN201410854036.6A CN201410854036A CN104576902B CN 104576902 B CN104576902 B CN 104576902B CN 201410854036 A CN201410854036 A CN 201410854036A CN 104576902 B CN104576902 B CN 104576902B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
Abstract
The present invention provides a kind of LED structure and preparation method thereof, the ITO of high-impedance state is arranged at the lower section of P pad as barrier layer to improve the luminosity of LED chip, material due to expansion electrode and barrier layer is ITO, thus do not exist poor adhesion lead to P pad or P pad and expansion electrode in packaging and routing or later stage application in depart from or the phenomenon that simultaneously departs from LED die.And, because barrier material is the ITO of high-impedance state, so barrier layer can be made very thin, which solve that subsequent expansion electrode ITO thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
Description
Technical field
The invention belongs to semiconductor optoelectronic chip manufacturing field, more particularly, to a kind of LED structure and preparation method thereof.
Background technology
Since early 1990s commercialization, through the development of twenties years, GaN base LED was widely used
In fields such as indoor and outdoor display screen, Projection Display lighting source, backlight, landscape brightening illumination, advertisement, traffic instructions, and
It is described as 21st century the most competitive solid light source of new generation.But for light emitting semiconductor device LED, generation
For conventional light source, enter high-end lighting field, the problem of " three improve a reduction " of its key technology must solve：I.e. luminance
The problem that problem, the problem of uniformity of luminance raising, the problem of device reliability raising and the device heating amount that degree improves reduces
Must solve.
In recent years, the various technology for improving LED luminosity are arisen at the historic moment, such as patterned substrate technology, barrier layer
Technology, side wall coarsening technique, DBR technology, optimization electrode structure, making 2 D photon crystal on substrate or nesa coating
Deng.Wherein patterned substrate technology most effect, between 2010 to 2012, the dry method figure of the cone structure occurring in front and back
The wet method pattern substrate of change substrate and Pyramid instead of the flat Sapphire Substrate in surface completely becomes LED chip
Main flow substrate, makes the crystal mass of LED and luminosity be obtained for revolutionary raising.
In addition, barrier technology also can make the luminosity of LED component improve 5-10 percentage point, yet with titanium dioxide
The presence on silicon barrier layer, so that the lower thickness of ITO expansion electrode around LED component P pad, which increases ITO extension electricity
The bulk resistor of pole and contact resistance, improve the voltage of LED chip；Moreover, P pad surrounding silicon dioxide barrier layer border
Locate ITO expansion electrode the thinnest to be also easiest to be punctured by electrostatic, it reduce the reliability of LED chip；Additionally due to ITO expands
The adhesiveness of exhibition electrode and silicon dioxide blocking layer is not good, usually makes P pad or P pad and the ITO extension electricity of LED chip
Pole departs from packaging and routing or in later stage application with LED die or departs from simultaneously.
The problem that uniformity of luminance improves and the problem of device heating amount reduction are two associated problems, and the former solves
The latter is benefited, vice versa.This two problems all have relation with the extension effect of ITO expansion electrode, more precisely work as ITO
When the extended capability of the extended capability of expansion electrode and N-type epitaxy layer is in the same order of magnitude, the uniformity of luminance of LED component
Can be addressed with the heat dissipation problem of LED component simultaneously.
Existing two methods can improve the extension effect of ITO expansion electrode：
First method is to arrange the SiO2 extension secondary graphics of periodic arrangement to improve in the lower section of ITO expansion electrode
The extension effect of ITO expansion electrode；
Second method is to improve ITO extension electricity by the cavernous structure of setting cycle arrangement in ITO expansion electrode
The extension effect of pole.
There are two kinds of defects in above-mentioned first method：One is it will usually use laughing gas when forming SiO2 extension secondary graphics
And silane, and laughing gas plasma cognition causes to p-type epitaxial layer to damage, thus raising the voltage of LED chip；Two is due to ITO
Expansion electrode and SiO2 extend secondary graphics adhesiveness poor so that ITO expansion electrode easily comes off from LED die.
Above-mentioned second method equally exists two kinds of defects：One be by wet corrosion technique in ITO expansion electrode shape
During the cavernous structure of one-tenth cycle arrangement, the shape and size of cavernous structure are difficult to control to；Two is the presence due to cavernous structure, makes
The p-type epitaxial layer obtaining LED chip is come out by cavernous structure, subsequently adopts laughing gas and silane to form SiO2 passivation protection layer
When, p-type epitaxial layer is easily destroyed by laughing gas plasma, thus improve the voltage of LED chip.
Content of the invention
It is an object of the invention to, solve barrier layer and expansion electrode adhesiveness in prior art not good lead to P pad and
The problem that expansion electrode is departed from LED die in packaging and routing or in later stage application.
Another object of the present invention is to, solve to be drawn because ITO expansion electrode is thinning around P pad in prior art
The LED chip voltage rising is high, the problem of poor reliability.
A further object of the present invention is, extends auxiliary layer raising TIO expansion electrode and extension auxiliary layer by forming ITO
Adhesiveness, and avoid p-type epitaxial layer by laughing gas plasma damage.
In order to solve the above problems, the present invention provides a kind of manufacture method of LED structure, including：
One substrate is provided, described substrate is formed with stacking epitaxial structure, described stacking epitaxial structure is from the bottom to top successively
Including N-type epitaxy layer, active layer and p-type epitaxial layer, described stacking epitaxial structure has the N area exposing described N-type epitaxy layer
Table top；
ITO barrier layer is formed on described p-type epitaxial layer；
ITO expansion electrode is formed on described p-type epitaxial layer and ITO barrier layer；
ITO expansion electrode above described ITO barrier layer forms P pad, described N area table top forms N pad；
And
Passivation protection layer is formed on described ITO expansion electrode, described passivation protection layer has the described P pad of exposure and N
The perforate of pad.
Optionally, the step of ITO barrier layer, in the manufacture method of described LED structure, is formed on described p-type epitaxial layer
Rapid inclusion：
Ito thin film is formed on described p-type epitaxial layer by evaporation mode；
ITO barrier layer figure is formed by photoetching and etching technics；
Described ITO barrier layer figure is processed using fluorine-containing solution；And
Described ITO barrier layer figure is made annealing treatment, makes the resistivity of described ITO barrier layer figure become big, formed
ITO barrier layer.
Optionally, in the manufacture method of described LED structure, described fluorine-containing solution is DHF solution or BOE is molten
Liquid, the temperature of described annealing is 400 degree～600 degree.
Optionally, the step of ITO barrier layer, in the manufacture method of described LED structure, is formed on described p-type epitaxial layer
Rapid inclusion：
Ito thin film is formed on p-type epitaxial layer by evaporation mode, evaporation process controls evaporation power, evaporation temperature
One of degree, oxygen atmosphere of evaporation cavity or multiple resistivity improving ito thin film；And
ITO barrier layer is formed by photoetching and wet corrosion technique.
Optionally, in the manufacture method of described LED structure, carried by the content improving oxygen and/or stannum in ito thin film
The resistivity of high ito thin film.
Optionally, in the manufacture method of described LED structure, improve stannum in ito thin film by reducing evaporating temperature
Content.
Optionally, in the manufacture method of described LED structure, ITO is improved by the flow that raising is passed through oxygen thin
The content of oxygen in film.
Optionally, in the manufacture method of described LED structure, the resistivity of described ITO barrier layer is 103～106Ω·
Cm, the resistivity of described ITO expansion electrode is 10-3～10-5Ω·cm.
Optionally, in the manufacture method of described LED structure, the thickness of described ITO barrier layer is
The thickness of described ITO expansion electrode is
Optionally, in the manufacture method of described LED structure, the same of ITO barrier layer is formed on described p-type epitaxial layer
When, form the ITO extension auxiliary layer of array arrangement also on described p-type epitaxial layer.
According to the another side of the present invention, also provide a kind of LED structure, including：
Substrate；
It is formed at the stacking epitaxial structure on described substrate, described stacking epitaxial structure is included outside N-type from the bottom to top successively
Prolong layer, active layer and p-type epitaxial layer, described stacking epitaxial structure has the N area table top exposing described N-type epitaxy layer；
It is formed at the ITO barrier layer on described p-type epitaxial layer；
It is formed at the ITO expansion electrode on described p-type epitaxial layer and on ITO barrier layer；
The P pad that is formed on the ITO expansion electrode above described ITO barrier layer and being formed in described N area table top
N pad；And
Be formed at the passivation protection layer on described ITO expansion electrode, described passivation protection layer have exposure described P pad and
The perforate of N pad.
Optionally, in described LED structure, also include the ITO extension being formed at array arrangement on described p-type epitaxial layer
Auxiliary layer.
Optionally, in described LED structure, the resistivity of described ITO barrier layer is 103～106Ω cm, described ITO
The resistivity of expansion electrode is 10-3～10-5Ω·cm.
Optionally, in described LED structure, the thickness of described ITO barrier layer isDescribed ITO expands
Exhibition electrode thickness be
LED structure of the present invention and preparation method thereof has advantages below：
First, LED structure of the present invention and preparation method thereof, the ITO of high-impedance state is arranged at the lower section of P pad as resistance
To improve the luminosity of LED chip, the material due to expansion electrode and barrier layer is ITO to barrier, so there is not adhesion
Property difference lead to P pad or P pad and expansion electrode in packaging and routing or the later stage application in LED die depart from or simultaneously
The phenomenon departing from.And, because barrier material is the ITO of high-impedance state, thus barrier layer can be made very thin, after which solving
Continuous expansion electrode ITO thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
In addition, the high-impedance state ITO pattern of periodic arrangement is arranged on p-type epitaxial layer corresponding with luminous zone the present invention
As extension auxiliary layer, improve the extension effect of expansion electrode, thus improving the uniformity of luminance of LED chip.Due to extension electricity
The material of pole and extension auxiliary layer is ITO, there is not the ITO that expansion electrode is led to because adhesiveness is not good with extension auxiliary layer
The phenomenon that expansion electrode easily comes off from LED die；And, because extension auxiliary layer is the high-impedance state of periodic arrangement
, so there is not figure and the unmanageable phenomenon of size in ITO pattern rather than cavernous structure；Furthermore it is provided by the present invention
There is not p-type epitaxial layer by laughing gas plasma damage in LED structure.
Brief description
Referring to the drawings, according to detailed description below, the present invention can be more clearly understood from.For the sake of clarity, scheme
In the relative thickness of each layer and the relative size of given zone be not drawn to draw.
In the accompanying drawings：
Figure 1A～1F is the device profile structural representation being formed in the embodiment of the present invention one and two manufacturing process.
Fig. 2A～2F is the device profile structural representation being formed in the embodiment of the present invention three and four manufacturing process.
Specific embodiment
In the research of the problem mentioned for background technology, inventors herein have recognized that, although in P pad and p-type
Between epitaxial layer, setting silicon dioxide blocking layer can improve the luminosity of LED component, but ITO expansion electrode and titanium dioxide
The adhesiveness on silicon barrier layer is not good, usually make P pad and ITO expansion electrode in packaging and routing or the later stage application in LED
Tube core departs from.Based on this, the ITO of high-impedance state is arranged at the lower section of P pad as barrier layer by the present invention, due to expansion electrode and
The material on barrier layer is ITO, so not existing, poor adhesion leads to P pad and expansion electrode in packaging and routing or the later stage should
With in LED die depart from phenomenon.
In addition, compared to silicon dioxide blocking layer, ITO barrier layer can do thinner (e.g., less than), this is
If because silicon dioxide blocking layer is made thin its color thin and is not easy identification when carrying out photoetching para-position out, and ITO stops
Even if layer is made thin its color thin and is also easier when carrying out photoetching para-position to recognize, and, works as silicon dioxide blocking layer thickness
When relatively thin, its blocking effect can be deteriorated, even and if ITO barrier layer be made thin thin blocking effect still will not be impacted, due to ITO
Barrier layer is thinner compared to silicon dioxide blocking layer of the prior art, and the step of formation is relatively small, shape on p-type epitaxial layer
Become ITO expansion electrode when, it is very thin that the ITO expansion electrode around ITO barrier layer will not become, which solves in prior art by
Problem in ITO expansion electrode thinning caused LED chip voltage height, poor reliability around P pad.
Additionally, the ITO that the present invention forms periodic arrangement while forming ITO barrier layer also on p-type epitaxial layer expands
Exhibition auxiliary layer, the high-impedance state ITO pattern of periodic arrangement is arranged at auxiliary as extending on p-type epitaxial layer corresponding with luminous zone
Help layer can improve the extension effect of ITO expansion electrode, thus improving the uniformity of luminance of LED chip, and, due to expansion electrode
It is ITO with the material of extension auxiliary layer, do not have that ITO expansion electrode is not good with extension auxiliary layer adhesiveness and the ITO that leads to
The phenomenon that expansion electrode easily comes off from LED die.Arrange compared to passing through the setting cycle in ITO expansion electrode in prior art
For the cavernous structure of cloth is to improve extension effect, when forming ITO extension auxiliary layer, figure and size are more prone to control, also not
There is a problem of being come out thus by laughing gas plasma damage by cavernous structure due to p-type epitaxial layer.
Below in conjunction with accompanying drawing, LED structure proposed by the present invention and preparation method thereof is described in further detail.According under
Face explanation and claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is all using very simplification
Form and all using non-accurately ratio, only in order to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
Embodiment one
As shown in Figure 1A, provide an epitaxial wafer, described epitaxial wafer includes substrate 11 and is formed on described substrate 11
Stacking epitaxial structure, described stacking epitaxial structure includes N-type epitaxy layer 121, active layer 122 and p-type extension from the bottom to top successively
Layer 123, described substrate 11 is, for example, Sapphire Substrate.
As shown in Figure 1B, N area table top 1210 is produced on described stacking epitaxial structure by conventional lithographic etching technics,
Described N area table top 1210 exposes described N-type epitaxy layer 121.In the present embodiment, the depth of described N area table top 1210 is more than described
The summation of active layer 122 and p-type epitaxial layer 123 thickness and be less than described stacking epitaxial structure thickness summation, i.e. outside N-type
Prolong the thickness less than the N-type epitaxy layer 121 in other regions for the thickness of layer 121.
As shown in Figure 1 C, ito thin film is formed on described p-type epitaxial layer 123 by evaporation mode, and pass through photoetching and quarter
Etching technique forms ITO barrier layer figure, then adopts fluorine-containing solution to process described ITO barrier layer figure, finally to described again
ITO barrier layer figure carries out the high temperature anneal, makes the resistance of described ITO barrier layer figure become big, to form ITO barrier layer
21.
Repeatedly test discovery through inventor, process ito thin film using fluorine-containing solution, then high annealing work is carried out to it
Skill, you can make the resistance of ITO become big (electric conductivity variation), thus the present invention utilizes the ITO that said method forms high-impedance state to stop
Layer 21.
In the present embodiment, described fluorine-containing solution is DHF (Fluohydric acid. of dilution) solution or BOE (buffered hydrofluoric acid) is molten
Liquid.The atmosphere of described high annealing is nitrogen atmosphere, and the annealing temperature of described high annealing is 400 degree～600 degree.Before process
The resistivity of ito thin film is between 10-3～10-5Between Ω cm, and the ito thin film of the high-impedance state being formed after above-mentioned process
Resistivity then between 103～106Between Ω cm, the ito thin film of the high-impedance state after process can play the effect on barrier layer.
In preferred version, the thickness of described ITO barrier layer 21 isDescribed ITO barrier layer 21 is less thanUnderstand, described ITO barrier layer 21 is thinner, the step that is, it forms is less, subsequently in ITO barrier layer 21 and p-type extension
When forming ITO expansion electrode on layer, it is very thin that the ITO expansion electrode around ITO barrier layer 21 will not become, it is possible to resolve prior art
In due to ITO expansion electrode, around P pad, thinning caused LED chip voltage is high, poor reliability problem.
As shown in figure ip, ITO expansion electrode 3 is formed on described ITO barrier layer 21 and p-type epitaxial layer 123, described
ITO expansion electrode 3 covers described ITO barrier layer 21 and p-type epitaxial layer 123, in order to extend electric current, described ITO expansion electrode
Resistivity is, for example, 10-3～10-5Ω cm, the thickness of described ITO expansion electrode 3 is, for example,
As referring to figure 1e, the ITO expansion electrode 3 above described ITO barrier layer 21 forms P pad 41, in described N area
Form N pad 42 in table top 1210.
As shown in fig. 1f, passivation protection layer 5 is formed on described ITO expansion electrode 3, described passivation protection layer 5 has cruelly
Reveal the perforate of described P pad 41 and N pad 42, so that lead, ultimately form LED structure of the present invention.
The present embodiment also provides a kind of LED structure, in conjunction with shown in Figure 1A～1F, including：
Substrate 11；
It is formed at the stacking epitaxial structure on described substrate 11, described stacking epitaxial structure includes N-type from the bottom to top successively
Epitaxial layer 121, active layer 122 and p-type epitaxial layer 123, described stacking epitaxial structure has the described N-type epitaxy layer 121 of exposure
N area table top 1210；
It is formed at the ITO barrier layer 21 on described p-type epitaxial layer 123；
It is formed at the ITO expansion electrode 3 on described p-type epitaxial layer 123 and on ITO barrier layer 21；
The P pad 41 that is formed on the ITO expansion electrode 3 of described ITO barrier layer 21 top and be formed at described N area platform
N pad 42 in face 1210；
It is formed at the passivation protection layer 5 on described ITO expansion electrode 3, described passivation protection layer 5 has exposure described P weldering
Disk 41 and the perforate of N pad 42.
Wherein, described substrate 11 is, for example, Sapphire Substrate, and the material of described passivation protection layer 5 is, for example, silicon dioxide.
The thickness of described ITO barrier layer 21 is, for example,The thickness of described ITO expansion electrode 3 is, for example,
Embodiment two
The present embodiment is with the difference of embodiment one, forms the ITO of high-impedance state on p-type epitaxial layer by evaporation mode
Thin film, then forms ITO barrier layer by lithographic etch process.The present embodiment can save high-temperature annealing process, by evaporation
During control evaporation power, evaporating temperature, one of oxygen atmosphere of evaporation cavity or various ways directly in p-type extension
The ito thin film of high-impedance state is formed on layer, then etches formation ITO pattern again, you can form the ITO barrier layer of high-impedance state.
Specifically, in the present embodiment, in conjunction with Figure 1A～1F, first pass through evaporation mode and high resistant is formed on p-type epitaxial layer 123
The ito thin film of state, can be formed by raising the modes such as evaporation power, reduction evaporating temperature, the oxygen atmosphere of raising evaporation cavity
The ito thin film of high-impedance state；Then, by photoetching and wet corrosion technique, ito thin film is graphical, only retain correspondence and be subsequently formed
The high-impedance state of P pad locations ito thin film, and then formed ITO barrier layer 21.
Practice finds, in ITO (tin indium oxide) thin film, the more high then resistance of the content of oxygen and stannum is bigger, therefore can be by improving
The content of oxygen and/or stannum and then improve its resistance in ito thin film.Specifically can be entered by reducing evaporating temperature or rising evaporation power
And improve the content of stannum in ito thin film, for example, during forming ito thin film institute using ITO ingot be diameter be about 2.5cm,
Highly it is about the cylinder of 10cm, electron beam impacts ITO ingot, make indium in ITO ingot and stannum all in vaporized state, in certain chamber
Under temperature, indium and stannum all up volatilize, and reach and deposit film forming, i.e. shape on ITO ingot substrate farther out thus on substrate
Become ito thin film, the volatilization point due to stannum is less than indium, so under lower temperature, the stannum reaching on substrate can be some more, raise evaporation work(
Rate then can make indium stannum all be easy to gasify, the content of stannum in equally controllable ito thin film.Or, by improving the stream being passed through oxygen
Measure and to improve the content of oxygen in ito thin film.
In the present embodiment, evaporation power is the 5%～20% of evaporation board peak power, and evaporating temperature is 200 degree～300
Degree, oxygen flow is 2sccm～10sccm.
Embodiment three
The present embodiment is with the difference of embodiment one, and on described p-type epitaxial layer 123, the position of corresponding P pad is formed
Also on described p-type epitaxial layer 123, while ITO barrier layer 21, form the ITO extension auxiliary layer 22 of array arrangement.In conjunction with figure
Shown in 2A～2F, in the present embodiment, ito thin film is formed on described p-type epitaxial layer 123 by evaporation mode, and pass through photoetching
Form ITO barrier layer figure and extension auxiliary layer pattern with etching technics simultaneously, more described ITO resistance is processed using fluorine-containing solution
Barrier figure and extension auxiliary layer pattern, and described ITO barrier layer figure and extension auxiliary layer pattern are carried out at high annealing
Reason, makes described ITO barrier layer figure and the resistance of extension auxiliary layer pattern become big (electric conductivity variation), to form ITO resistance simultaneously
Barrier 21 and ITO extension auxiliary layer 22.
Example IV
The present embodiment is with the difference of embodiment three, directly forms high resistant on p-type epitaxial layer 123 by evaporation mode
ITO (tin indium oxide) thin film of state.In conjunction with shown in Fig. 2A～2F, can be by controlling evaporation power, evaporating temperature, evaporation cavity
One of oxygen atmosphere or various ways forming the ito thin film of high-impedance state, then by photoetching and wet corrosion technique simultaneously
ITO barrier layer 21 and ITO extension auxiliary layer 22 are formed on p-type epitaxial layer 123.
In sum, LED structure of the present invention and preparation method thereof, the lower section that the ITO of high-impedance state is arranged at P pad is made
For barrier layer to improve the luminosity of LED chip, the material due to expansion electrode and barrier layer is ITO, so not existing
Poor adhesion lead to P pad or P pad and expansion electrode in packaging and routing or the later stage application in LED die depart from or
The phenomenon simultaneously departing from.Further, since barrier material is the ITO of high-impedance state, so barrier layer can be made very thin, this solution
Subsequent expansion electrode ITO thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
Further, the high-impedance state ITO pattern of periodic arrangement is arranged at p-type extension corresponding with luminous zone by the present invention
As extension auxiliary layer on layer, improve the extension effect of expansion electrode, thus improving the uniformity of luminance of LED chip.Due to expanding
The material of exhibition electrode and extension auxiliary layer is ITO, there is not expansion electrode and leads to because adhesiveness is not good with extension auxiliary layer
The phenomenon that easily comes off from LED die of ITO expansion electrode；And, because extension auxiliary layer is the high resistant of periodic arrangement
, so there is not figure and the unmanageable phenomenon of size in the ITO pattern of state rather than cavernous structure；Furthermore it is provided by the present invention
LED structure there is not p-type epitaxial layer by laughing gas plasma damage.
It should be noted that each embodiment is described by the way of going forward one by one in this specification, each embodiment emphasis is said
Bright is all the difference with other embodiment, and between each embodiment, identical similar portion description is fairly simple, related
Part mutually referring to.
Although being described in detail to the present invention by exemplary embodiment, those skilled in the art should
This understanding, exemplary embodiment above merely to illustrating, rather than in order to limit the scope of the present invention.The skill of this area
Art personnel are it should be understood that can modify to above example without departing from the scope and spirit of the present invention.This
Bright scope is defined by the following claims.
Claims (14)
1. a kind of manufacture method of LED structure is it is characterised in that include：
One substrate is provided, described substrate is formed with stacking epitaxial structure, described stacking epitaxial structure includes N from the bottom to top successively
Type epitaxial layer, active layer and p-type epitaxial layer, described stacking epitaxial structure has the N area table top exposing described N-type epitaxy layer；
ITO barrier layer is formed on described p-type epitaxial layer；
ITO expansion electrode is formed on described p-type epitaxial layer and ITO barrier layer；
ITO expansion electrode above described ITO barrier layer forms P pad, described N area table top forms N pad；And
Passivation protection layer is formed on described ITO expansion electrode, described passivation protection layer has the described P pad of exposure and N pad
Perforate.
2. the manufacture method of LED structure as claimed in claim 1 is it is characterised in that form ITO on described p-type epitaxial layer
The step on barrier layer includes：
Ito thin film is formed on described p-type epitaxial layer by evaporation mode；
ITO barrier layer figure is formed by photoetching and etching technics；
Described ITO barrier layer figure is processed using fluorine-containing solution；And
Described ITO barrier layer figure is made annealing treatment, makes the resistivity of described ITO barrier layer figure become big, form ITO resistance
Barrier.
3. LED structure as claimed in claim 2 manufacture method it is characterised in that described fluorine-containing solution be DHF solution or
Person's BOE solution, the temperature of described annealing is 400 DEG C～600 DEG C.
4. the manufacture method of LED structure as claimed in claim 1 is it is characterised in that form ITO on described p-type epitaxial layer
The step on barrier layer includes：
Ito thin film is formed on p-type epitaxial layer by evaporation mode, evaporation process controls evaporation power, evaporating temperature, steaming
Send out one of oxygen atmosphere of cavity or multiple resistivity improving ito thin film；And
ITO barrier layer is formed by photoetching and wet corrosion technique.
5. LED structure as claimed in claim 4 manufacture method it is characterised in that by improve ito thin film in oxygen and/or
The content of stannum improves the resistivity of ito thin film.
6. the manufacture method of LED structure as claimed in claim 5 is it is characterised in that improve ITO by reducing evaporating temperature
The content of stannum in thin film.
7. the manufacture method of LED structure as claimed in claim 5 is it is characterised in that pass through to improve the flow of the oxygen being passed through
To improve the content of oxygen in ito thin film.
8. the manufacture method of LED structure as claimed in claim 1 is it is characterised in that the resistivity of described ITO barrier layer is 103
～106Ω cm, the resistivity of described ITO expansion electrode is 10-5～10-3Ω·cm.
9. the manufacture method of LED structure as claimed in claim 1 is it is characterised in that the thickness of described ITO barrier layer isThe thickness of described ITO expansion electrode is
10. the manufacture method of LED structure as claimed in claim 1 is it is characterised in that form ITO on described p-type epitaxial layer
Also on described p-type epitaxial layer, while barrier layer, form the ITO extension auxiliary layer of array arrangement.
A kind of 11. LED structure are it is characterised in that include：
Substrate；
Be formed at the stacking epitaxial structure on described substrate, described stacking epitaxial structure include successively from the bottom to top N-type epitaxy layer,
Active layer and p-type epitaxial layer, described stacking epitaxial structure has the N area table top exposing described N-type epitaxy layer；
It is formed at the ITO barrier layer on described p-type epitaxial layer；
It is formed at the ITO expansion electrode on described p-type epitaxial layer and on ITO barrier layer；
The P pad being formed on the ITO expansion electrode above described ITO barrier layer and the N being formed in described N area table top weld
Disk；And
It is formed at the passivation protection layer on described ITO expansion electrode, described passivation protection layer has the described P pad of exposure and N weldering
The perforate of disk.
12. LED structure as claimed in claim 11 are it is characterised in that also include being formed at array row on described p-type epitaxial layer
The ITO extension auxiliary layer of cloth.
13. LED structure as claimed in claim 11 are it is characterised in that the resistivity of described ITO barrier layer is 103～106
Ω cm, the resistivity of described ITO expansion electrode is 10-5～10-3Ω·cm.
14. LED structure as claimed in claim 11 are it is characterised in that the thickness of described ITO barrier layer is
The thickness of described ITO expansion electrode is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410854036.6A CN104576902B (en) | 2014-12-31 | 2014-12-31 | A kind of LED structure and preparation method thereof |
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|---|---|---|---|
| CN201410854036.6A CN104576902B (en) | 2014-12-31 | 2014-12-31 | A kind of LED structure and preparation method thereof |
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| Publication Number | Publication Date |
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| CN104576902A CN104576902A (en) | 2015-04-29 |
| CN104576902B true CN104576902B (en) | 2017-03-01 |
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| CN101944558A (en) * | 2009-07-09 | 2011-01-12 | 晶发光电股份有限公司 | Light-emitting diode with passivation layer and preparation method thereof |
| US8324649B2 (en) * | 2010-09-17 | 2012-12-04 | Lg Innotek Co., Ltd. | Light emitting device |
| CN202871850U (en) * | 2012-10-13 | 2013-04-10 | 江苏新广联科技股份有限公司 | Gallium nitride (GaN)-based ipsilateral electrode light-emitting diode (LED) chip structure |
| CN204303863U (en) * | 2014-12-31 | 2015-04-29 | 杭州士兰明芯科技有限公司 | A kind of LED structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944558A (en) * | 2009-07-09 | 2011-01-12 | 晶发光电股份有限公司 | Light-emitting diode with passivation layer and preparation method thereof |
| US8324649B2 (en) * | 2010-09-17 | 2012-12-04 | Lg Innotek Co., Ltd. | Light emitting device |
| CN202871850U (en) * | 2012-10-13 | 2013-04-10 | 江苏新广联科技股份有限公司 | Gallium nitride (GaN)-based ipsilateral electrode light-emitting diode (LED) chip structure |
| CN204303863U (en) * | 2014-12-31 | 2015-04-29 | 杭州士兰明芯科技有限公司 | A kind of LED structure |
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