TW201320032A - Pixel structure and field emission device - Google Patents

Abstract

A pixel structure disposed on a first substrate, suitable for a field emission display, and including a scan line, a data line, and an insulation structure layer is provided. The scan line has a scan main line extending in a first direction and a scan branch connected to the scan main line. The data line has a data main line extending in a second direction and a data branch connected to the data branch. The scan main line intersects with and overlaps the data main line to define a main line overlapping region. The scan branch overlaps the data branch to define a display emission region. The insulation structure layer is disposed between the scan line and the data line. The data line and the insulation structure layer has a first opening in the main line overlapping region, and a second opening in the display emission region.

Description

Pixel structure and field emission display

The present invention relates to a pixel structure, and more particularly to a pixel structure suitable for use in a field emission display.

The importance of displays in people's lives is increasing. In addition to computers or the Internet, televisions, mobile phones, personal digital assistants (PDAs), digital cameras, etc., must transmit messages through display controls. Compared to traditional image tube displays, the new generation of flat panel displays have the advantages of light weight, small size, and human health.

Among many emerging flat panel display technologies, field emission display (FED) not only has the advantages of traditional image tube high image quality, but also has a smaller viewing angle, a lower temperature range, and a slower response than liquid crystal displays. In terms of shortcomings, the field emission display has the advantages of high luminous efficiency, rapid reaction time, good coordinated display performance, high brightness exceeding 100 ftL, light and thin structure, wide viewing angle, large operating temperature range, and high operational efficiency. In addition, the field emission display does not require a backlight module when used. Therefore, even in outdoor sunlight, it can provide excellent brightness performance. Therefore, current field emission displays have been seen as quite a chance to compete with liquid crystal display technology and even replace it with new display technologies.

The present invention provides a pixel structure having reduced parasitic capacitance to maintain good electrical characteristics.

The invention provides a pixel structure, which is arranged on a first substrate and is suitable for a field emission display. The pixel structure includes a scan line, a data line, and an insulating structure layer. The scan line has a scan main line and at least one scan branch. The scanning main line extends along a first square line, and the scanning branch is connected to the scanning main line. The data line has a data main line and at least one data branch. The data main line extends in a second direction, and the data branch is connected to the data main line. The scan main line overlaps with the data main line to define a main line overlap area, and the scan branch overlaps with the data branch to define at least one display emissive area. The insulating structure layer is disposed between the scan line and the data line, and the data main line and the insulating structure layer in the main line overlap area have at least one first opening, and the data branch and the insulating structure layer in the display emission area have at least a second Open the hole.

In an embodiment of the invention, the first opening comprises a main line opening in the main line of the data, and a first insulating opening in the insulating structure layer, the second opening comprising a first branch in the data branch a branch opening and a second insulating opening in the insulating structure layer.

In an embodiment of the invention, the first insulating opening has a depth extending downward from the data line that is less than or equal to a thickness of the insulating structure layer.

In an embodiment of the invention, the contour of each of the first insulating openings surrounds the contour of the main line opening through which it communicates.

In an embodiment of the invention, the first insulating opening has a larger aperture than the main line opening, and the second insulating opening has a larger aperture than the branch opening.

In an embodiment of the invention, the insulating structural layer comprises at least one interlayer insulating layer. The material of at least one interlayer insulating layer includes tantalum oxide, tantalum nitride, niobium oxynitride or a combination thereof.

In an embodiment of the invention, the pixel structure further includes a resistive layer disposed between the insulating structure layer and the scan line. The material of the resistance layer includes a ruthenium carbon compound, a ruthenium carbon oxide compound, or a combination thereof.

In an embodiment of the invention, the pixel structure further includes a plurality of emission sources located in the second opening and disposed on the scanning branch. In addition, the pixel structure further includes an anode disposed on a second substrate opposite to the emission source, wherein the scanning branch acts as a cathode and the data branch acts as a gate.

Based on the above, in order to reduce the parasitic capacitance in the pixel structure to make the pixel structure have ideal characteristics, the present invention forms a plurality of main line openings on the main line of the data line, and the main line openings are located on the main line of the scanning line and the main line of the data line. In the area to reduce the overlap area between the scan line and the data line. In addition, the pixel structure of the present invention is further provided in the insulating structure layer between the scan line and the data line to communicate with the main line opening to further reduce the parasitic capacitance that may exist in the pixel structure.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a schematic diagram of a pixel structure according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the pixel structure of FIG. 1 along a line I-I', and FIG. 3 is a diagram of the pixel structure of FIG. 1 applied to a field emission display. At the time, it corresponds to the schematic diagram of the line II-II' of Fig. 1. Referring to FIG. 1 and FIG. 2 , the pixel structure 100 is disposed on the substrate 10 and includes a scan line 110 , a data line 120 , and an insulating structure layer 130 .

The scan line 110 is disposed between the substrate 10 and the data line 120. The insulating structure layer 130 is disposed between the scan line 110 and the data line 120 to electrically insulate the scan line 110 and the data line 120 from each other. In addition, the set resistance layer 150 (or referred to as a resistive layer) may be selectively added between the insulating structure layer 130 and the scan line 110. In this embodiment, although the insulating structure layer 130 is illustrated as a single layer, in other embodiments or practical applications, the insulating structure layer 130 may be a single layer or a multilayer stack, and the insulating structure layer 130 includes at least One or more layers of interlayer insulating layers, the material of which includes tantalum oxide, tantalum nitride, niobium oxynitride or a combination thereof. In addition, the material of the resistance layer 150 includes a bismuth carbon compound, a bismuth carbon oxide compound, or a combination thereof, wherein the resistance layer 150 may be selectively disposed in the pixel structure 100. That is, in other embodiments, the pixel structure 100 may optionally be provided with no impedance layer 150. Of course, the arrangement of the resistive layer 150 and the number of layers of the insulating structural layer 130 may be determined by actual design requirements and should not be used in particular to limit the spirit of the present invention.

In the present embodiment, the scan line 110 has a scan main line 112 and at least one scan branch 114. The scan main line 112 extends along a first square line D1, and the scan branch 114 is connected to the scan main line 112. The data line 120 has a data main line 122 and at least one data branch 124. The data main line 122 extends in a second direction D2, and the data branch 124 is connected to the data main line 122. The scan main line 112 overlaps with the data main line 122 to define a main line overlap area A, and the scan branch 114 overlaps with the data branch 124 to define at least one display emissive area B. The scan branch 114 and the data branch 124 may constitute a further The other display area of D2 in the second direction (not shown). In addition, at least one first opening 142 is defined in the data main line 122 and the insulating structure layer 130 of the main line overlap area A, and at least one second opening 144 is defined in the data branch 124 and the insulating structure layer 130 of the display emissive area B. . The first opening 142 includes a main line opening 122A in the data main line 122, and a first insulating opening 132 in the insulating structure layer 130. The second opening 144 includes a branch located in the data branch 124. The opening 124A and a second insulating opening 134 in the insulating structure layer 130.

In addition, as can be seen from FIG. 1 and FIG. 3, the first insulating opening 132 is located in the main line overlapping area A and communicates with the main line opening 122A, and the second insulating opening 134 is located in the display emitting area B and communicates with the branch opening 124A. At the same time, the emission source 140 is, for example, located in the second insulating opening 134 of the second opening 144 and may be disposed on the scanning branch 114. Specifically, as shown in FIG. 3, when the pixel structure 100 is applied to a field emission display, an anode 160 may be further disposed on a second substrate 170, and the anode 160 is disposed opposite to the emission source 140. At this time, the scanning branch 114 is, for example, a cathode, and the data branch 124 is, for example, a gate. In addition, as shown in FIG. 5, a pad layer 152, such as a chrome layer, may be selectively added between the emission source 140 and the scanning branch 114 to enhance the emission efficiency of the emission source 140. If the resistive layer 150 is provided in the pixel structure 100, the pad layer 152 is disposed between the emissive source 140 and the resistive layer 150. In addition, a spacer (not shown) is disposed between the first substrate 10 and the second substrate 170 for supporting the first substrate 10 and the second substrate 170, which is well known to those skilled in the art, and therefore no longer Narration.

Since the display emissive region B of the emissive source 140 is disposed on the scan branch 114 and corresponds to the data branch 124, any defects occurring in the emissive region B are displayed, such as an improper short circuit between components or an improper disconnection between components. Alternatively, the repair can be performed independently without affecting the scan main line 112 and the data main line 122. For example, when an improper short circuit occurs between components in the emitter region B, the corresponding scan branch 114 and the data branch 124 can be severed by laser cutting or other suitable method. At this time, the scanning main line 112 and the data main line 122 are still continuous transmission lines without being affected by the repairing action. In the embodiment, the scan line 110 and the data line 120 are extended from the scan branch 114 and the data branch 124 as the set emission source 140, as compared with the pixel structure in which the emission source is directly disposed at the intersection of the scan line and the data line. The display of the emitter region B allows the pixel structure 100 to have a repairable structural design that helps to improve the yield of the pixel structure 100.

In addition, for the pixel structure 100, the larger the parasitic capacitance generated between the scan line 110 and the data line 120, the poor electrical characteristics due to parasitic capacitance, such as RC delay, etc. Born to respond. The parasitic capacitance between the scan line 110 and the data line 120 conforms to the following formula: C=εA/d, where C is a parasitic capacitance, and ε is a dielectric constant of a medium between the scan line 110 and the data line 120, where A is The overlapping area of the scan line 110 and the data line 120, and d is the distance between the scan line 110 and the data line 120.

It can be seen from the above formula that the larger the overlapping area of the scanning line 110 and the data line 120, the more unfavorable the characteristics of the pixel structure 100. Therefore, in order to reduce the parasitic capacitance between the scan line 110 and the data line 120, in the present embodiment, the material main line 122 has at least one main line opening 122A located in the main line overlap area A. Providing the main line opening 122A on the data main line 122 helps to reduce the overlapping area between the data main line 122 and the scanning main line 112, thereby reducing the parasitic capacitance between the two.

In addition, the insulating structure layer 130 has at least one first insulating opening 132. The first insulating opening 132 is in communication with the main line opening 122A, and the aperture O1 of each of the first insulating openings 132 is larger than the aperture O2 of the main line opening 122A to which it communicates. At the same time, the contour of the first insulating opening 132 substantially surrounds the contour of the main line opening 122A that it communicates with. Therefore, within the area of the first insulating opening 132, the medium between the scanning main line 112 and the data main line 122 is air without the insulating structure layer 130. Since the dielectric constant of the air is smaller than the dielectric constant of the insulating structure layer 130, according to the above formula, when the medium between the scanning main line 112 and the data main line 122 is air, the parasitic capacitance between the two is smaller than the scanning main line 112 and the data main line. The dielectric between 122 is the parasitic capacitance between the two when the dielectric layer 130 is insulated. That is to say, the design of the first insulating opening 132 in the insulating structure layer 130 is larger than the design of the main line opening 122A, which helps to further reduce the parasitic capacitance between the scanning line 110 and the data line 120, thereby improving the quality of the pixel structure 100, in particular It is to improve the electrical characteristics of the pixel structure 100. Taking the yttrium oxide layer as the insulating structure layer 130, the yttrium oxide has a dielectric constant of about 3.9, the air has a dielectric constant of about 1.0, and when the first opening 142 is not used, the capacitance value is, for example, 162500 pF/μm. After the first opening 142 is formed, the capacitance value can be reduced to 102083 pF/μm, which can reduce the capacitance value by about 30%, which can greatly reduce the power required for driving.

Specifically, the depth H of the first insulating opening 132 extending downward from the data line 120 may be substantially less than or equal to the thickness T of the insulating structure layer 130. For example, when the insulating structure layer 132 is composed of an N-layer interlayer insulating layer, the depth H of the first insulating opening 132 may be the thickness of the M-layer interlayer insulating layer, where M is less than or equal to N. When M is less than N, at least one interlayer insulating layer in the insulating structure layer 130 still covers the scan line 110, which helps to prevent the scan line 110 from being exposed by the first insulating opening 132. At this time, the scan line 110 is not easily short-circuited with the data line 120. Of course, the present invention is not limited thereto. In the design of the pixel structure 100, the impedance layer 150 is disposed between the insulating structure layer 130 and the scan line 110. Therefore, when the depth H of the first insulating opening 132 extending downward from the data line 120 is equal to the thickness T of the insulating structure layer 130, the scanning line 110 is still covered by the resistive layer 110 without being exposed by the first insulating opening 132. It is also not easy to short circuit with the data line 120. Therefore, the depth H of the first insulating opening 132 can be determined depending on the overall structural design.

In detail, FIG. 4 illustrates a flow of making a main line opening and a first insulating opening according to an embodiment of the invention. Referring to FIG. 4, in step a, a plurality of fine particles 20 are sprinkled on the substrate 10. At this time, the scan line 110, the insulating structure layer 130, and the resistive layer 150 have been formed on the substrate 10, wherein the insulating structure layer 130 may be composed of a plurality of interlayer insulating layers, but the present invention does not particularly limit the number of interlayer insulating layers. In addition, the fine particles 20 may be nano particles or other minute particles.

Next, step b is performed to deposit a layer of conductive material 30 on the substrate 10, wherein the layer of conductive material 30 is locally deposited on the particles 20 and locally deposited on the insulating layer 130. Then, as shown in step c, the microparticles 20 are removed with a brush or other suitable tool. As such, the conductive material layer 30 can form the data main line 122 having a plurality of main line openings 122A as shown in step d.

Then, as shown in step e, an etching process is performed with the material main line 122 as a mask to form a plurality of first insulating openings 132 in the insulating structure layer 130. The etching process employed herein may include successive dry etching steps and wet etching steps. The dry etching step may first remove a portion of the insulating structure layer 130 in the depth direction, and the subsequent wet etching step may remove a portion of the insulating structure layer 130 in the width direction.

In step e, since the first insulating opening 132 is etched by using the material main line 122 as a mask, the first insulating opening 132 may communicate with the main line opening 122A. Further, after the above wet etching step is completed, curved side walls may be formed as shown in FIG. Further, the etching conditions may be appropriately controlled so that the first insulating opening 132 has a pyramid shape to form an oblique side wall (not shown). The aperture of the first insulating opening 132 is larger than the aperture of the main line opening 122A and the contour of the first insulating opening 132 may surround the contour of the main opening 122A. Further, the etching process employed in step e can be appropriately adjusted to determine the depth of the first insulating opening 13 and the sidewall profile.

It should be noted that although FIG. 4 shows the manufacturing process of the first insulating opening 132 and the main opening 122A, the branch opening 124A and the second shown in FIG. 3 can be simultaneously formed in such a manufacturing process. Insulation opening 134. That is to say, this embodiment does not require an additional step of fabricating the first insulating opening 132 and the main line opening 122A without causing an extension of the manufacturing time or an increase in the manufacturing cost. Of course, the above production process is for illustrative purposes only, and is not intended to limit the invention by the steps described above. Any of the patterning processes used in the art can be applied to the present invention to form the desired first and second openings in the insulating structure layer 130 and the data line 120.

In summary, the present invention overlaps the scan line and the branch from which the data line extends to form a display emission area in which the emission source is disposed. In this way, once the components in the emission area are defective, the branches extending from the scanning lines and the data lines can be repaired to make the pixel structure have repairable characteristics. In addition, a plurality of openings on the data line are arranged on the overlapping area of the main line of the scan line and the data line, which can reduce the overlapping area of the main line of the scan line and the data line and reduce the parasitic capacitance between the scan line and the data line. At the same time, the insulating structure layer in the overlap region of the main line may be provided with an insulating opening to further reduce the parasitic capacitance between the scan line and the data line. Therefore, in the pixel structure of the present invention which is suitable for a field emission display, the parasitic capacitance between the scanning line and the data line can be significantly lowered to make the pixel structure have desired electrical characteristics.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Substrate

20. . . Microparticle

30. . . Conductive material layer

100. . . Pixel structure

110. . . Scanning line

112. . . Scanning main line

114. . . Scanning branch

120. . . Data line

122. . . Data main line

122A. . . Main line opening

124. . . Data branch

124A. . . Branch opening

130. . . Insulating structural layer

132. . . First insulating opening

134. . . Second insulating opening

140. . . Source of emission

142. . . First opening

144. . . Second opening

150. . . Impedance layer

152. . . Cushion

160. . . anode

170. . . Second substrate

A. . . Main line overlap

B. . . Display launch area

D1. . . First direction

D2. . . Second direction

H. . . depth

I-I’, II-II’. . . Section line

O1, O2. . . Aperture

T. . . thickness

FIG. 1 illustrates a pixel structure according to an embodiment of the present invention.

Figure 2 is a cross-sectional view of the pixel structure of Figure 1 taken along line I-I'.

Fig. 3 is a view corresponding to the line II-II' of Fig. 1 when the pixel structure of Fig. 1 is applied to a field emission display.

4 is a flow chart of fabricating a main line opening and a first insulating opening according to an embodiment of the invention.

Fig. 5 is a view corresponding to the line II-II' of Fig. 1 when the pixel structure of Fig. 1 is applied to a field emission display.

100. . . Pixel structure

110. . . Scanning line

112. . . Scanning main line

114. . . Scanning branch

120. . . Data line

122. . . Data main line

122A. . . Main line opening

124. . . Data branch

124A. . . Branch opening

132. . . First insulating opening

134. . . Second insulating opening

140. . . Source of emission

142. . . First opening

144. . . Second opening

A. . . Main line overlap

B. . . Display launch area

D1. . . First direction

D2. . . Second direction

I-I’, II-II’. . . Section line

Claims (14)

A pixel structure, disposed on a first substrate, is suitable for a field emission display, comprising: a scan line having a scan main line and at least one scan branch, the scan main line extending along a first square line, the scan branch Connecting the scan main line; a data line having a data main line and at least one data branch, the data main line extending along a second direction, the data branch connecting the data main line, the scan main line and the data main line intersecting to define a a main line overlap region, and the scan branch overlaps with the data branch to define at least one display emissive region; and an insulating structure layer disposed between the scan line and the data line, and the data main line of the main line overlap region The insulating structural layer has at least one first opening, and the data branch of the display emitting region and the insulating structural layer have at least one second opening. The pixel structure of claim 1, wherein the first opening comprises a main line opening in the main line of the data, and the first insulating opening in the insulating structure layer, the second opening The aperture includes a branch opening in the branch of the data and the second insulating opening in the insulating structure layer. The pixel structure of claim 2, wherein the first insulating opening extends downward from the data line by a depth less than or equal to a thickness of the insulating structural layer. The pixel structure of claim 2, wherein the contour of each of the first insulating openings surrounds a contour of the main line opening through which it communicates. The pixel structure of claim 2, wherein the first insulating opening has a larger aperture than the main line opening, and the second insulating opening has a larger aperture than the branch opening. The pixel structure of claim 1, wherein the insulating structure layer comprises at least one interlayer insulating layer. The pixel structure of claim 6, wherein the material of the at least one interlayer insulating layer comprises tantalum oxide, tantalum nitride, niobium oxynitride or a combination thereof. The pixel structure of claim 1, further comprising a resistive layer disposed between the insulating structure layer and the scan line. The pixel structure of claim 8, wherein the material of the impedance layer comprises a ruthenium carbon compound, a ruthenium carbon oxide compound or a combination thereof. The pixel structure of claim 1, further comprising a plurality of emission sources located in the second opening and disposed on the scanning branch. The pixel structure of claim 10, further comprising a pad disposed between the emission source and the scan line. The pixel structure of claim 10, further comprising a second substrate opposite to the first substrate, the second substrate comprising an anode disposed on the second substrate, opposite to the emission sources The setting, wherein the scanning branch acts as a cathode, and the data branch acts as a gate. A field emission display includes: a first substrate; a plurality of scan lines, each scan line having a scan main line and at least one scan branch, the scan main line extending along a first square line, the scan branch connecting the scan main line; a plurality of data lines, each data line having a data main line and at least one data branch, the data main line extending along a second direction, the data branch connecting the data main line, the scan main lines and the data main lines intersecting and defining And a plurality of main line overlap regions, wherein the scan branches overlap with the data branches to define a plurality of display emission regions; an insulating structure layer disposed between the scan lines and the data lines, and each of the The data main line of the main line overlap region and the insulating structure layer have at least one first opening, and the data branch of each of the display emissive regions and the insulating structure layer have at least one second opening; and a plurality of emission sources, Located in the second opening. The field emission display of claim 13, further comprising a second substrate opposite to the first substrate, the second substrate comprising an anode disposed on the second substrate, opposite to the emission sources The setting, wherein the scanning branch acts as a cathode, and the data branch acts as a gate.