CN204303863U - A kind of LED structure - Google Patents
A kind of LED structure Download PDFInfo
- Publication number
- CN204303863U CN204303863U CN201420869326.3U CN201420869326U CN204303863U CN 204303863 U CN204303863 U CN 204303863U CN 201420869326 U CN201420869326 U CN 201420869326U CN 204303863 U CN204303863 U CN 204303863U
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- Prior art keywords
- ito
- barrier layer
- pad
- expansion electrode
- layer
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Abstract
The utility model provides a kind of LED structure, the below ITO of high-impedance state being arranged at P pad as barrier layer to improve the luminosity of LED chip, because the material on expansion electrode and barrier layer is ITO, so there is not the phenomenon that poor adhesion causes P pad or P pad and expansion electrode when packaging and routing or depart from or depart from LED die in later stage application simultaneously.Further, because barrier material is the ITO of high-impedance state, so barrier layer can be done very thin, which solve that subsequent expansion electrode ITO thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
Description
Technical field
The utility model belongs to semiconductor optoelectronic chip manufacturing field, particularly relates to a kind of LED structure.
Background technology
Since early 1990s commercialization, through the development of twenties years, GaN base LED has been widely used in the fields such as indoor outer display screen, Projection Display lighting source, backlight, view brightening illumination, advertisement, traffic instruction, and is described as 21st century the most competitive solid light source of new generation.But for light emitting semiconductor device LED, replace conventional light source, enter high-end lighting field, the problem of " three improve reduces " of its key technology must solve: the problem that problem, the problem of uniformity of luminance raising, the problem of device reliability raising and device heating amount that namely luminosity improves reduce must solve.
In recent years, the various technology for improving LED luminosity is arisen at the historic moment, and such as patterned substrate technology, barrier technology, sidewall coarsening technique, DBR technology, optimizes electrode structure, on substrate or nesa coating, makes 2 D photon crystal etc.Wherein patterned substrate technology most effect, between 2010 to 2012, the dry method patterned substrate of cone structure that front and back occur and the wet method pattern substrate of Pyramid instead of the main flow substrate that the smooth Sapphire Substrate in surface becomes LED chip completely, make the crystal mass of LED and luminosity be obtained for revolutionary raising.
In addition, barrier technology also can make the luminosity of LED component improve 5-10 percentage point, but due to the existence of silicon dioxide blocking layer, make the lower thickness of the ITO expansion electrode around LED component P pad, which increase the volume resistance of ITO expansion electrode and contact resistance, improve the voltage of LED chip; Moreover, the thinnest ITO expansion electrode of P pad surrounding silicon dioxide barrier layer boundary also the most easily puncture by electrostatic, it reduce the reliability of LED chip; In addition the adhesiveness due to ITO expansion electrode and silicon dioxide blocking layer is not good, usually makes the P pad of LED chip or P pad and ITO expansion electrode when packaging and routing or departs from LED die in later stage application or depart from simultaneously.
The problem that uniformity of luminance improves and the problem that device heating amount reduces are two problems be associated, and the former solves, and the latter is benefited, vice versa.This two problems all has relation with the expansion effect of ITO expansion electrode, more precisely when the extended capability of ITO expansion electrode and the extended capability of N-type epitaxy layer are in the same order of magnitude, the uniformity of luminance of LED component and the heat dissipation problem of LED component can be solved simultaneously.
Existing two kinds of methods can improve the expansion effect of ITO expansion electrode:
First method is that the SiO2 arranging periodic arrangement in the below of ITO expansion electrode expands auxiliary pattern to improve the expansion effect of ITO expansion electrode;
Second method be by arrange in ITO expansion electrode the cycle arrangement cavernous structure to improve the expansion effect of ITO expansion electrode.
There are two kinds of defects in above-mentioned first method: one is, when forming SiO2 expansion auxiliary pattern, usually can use laughing gas and silane, and laughing gas plasma cognition causes damage to P type epitaxial loayer, thus raise the voltage of LED chip; Two is because the adhesiveness of ITO expansion electrode and SiO2 expansion auxiliary pattern is poor, and ITO expansion electrode is easily come off from LED die.
There are two kinds of defects in above-mentioned second method: one when being the cavernous structure by wet corrosion technique formation cycle arrangement in ITO expansion electrode, and the shape and size of cavernous structure are difficult to control equally; Two is the existence due to cavernous structure; the P type epitaxial loayer of LED chip is come out by cavernous structure; when follow-up employing laughing gas and silane form SiO2 passivation protection layer, P type epitaxial loayer is easily subject to the destruction of laughing gas plasma, thus improves the voltage of LED chip.
Utility model content
The purpose of this utility model is, solve barrier layer and expansion electrode adhesiveness in prior art not good cause P pad and expansion electrode when packaging and routing or the later stage apply in the problem that departs from LED die.
Another object of the present utility model is, solves in prior art because ITO expansion electrode thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
Another object of the present utility model is, expands the adhesiveness that auxiliary layer improves TIO expansion electrode and expansion auxiliary layer, and avoid P type epitaxial loayer by laughing gas plasma damage by forming ITO.
In order to solve the problem, the utility model provides a kind of LED structure, comprising:
Substrate;
Be formed at the stacked epitaxial structure on described substrate, described stacked epitaxial structure comprises N-type epitaxy layer, active layer and P type epitaxial loayer from the bottom to top successively, described stacked epitaxial structure has the N district table top exposing described N-type epitaxy layer;
Be formed at the ITO barrier layer on described P type epitaxial loayer;
To be formed on described P type epitaxial loayer and ITO expansion electrode on ITO barrier layer;
Be formed at the P pad on the ITO expansion electrode above described ITO barrier layer and be formed at the N pad in described N district table top; And
Be formed at the passivation protection layer on described ITO expansion electrode, described passivation protection layer has the perforate exposing described P pad and N pad.
Optionally, in described LED structure, also comprise the ITO being formed at array arrangement on described P type epitaxial loayer and expand auxiliary layer.
Optionally, in described LED structure, the resistivity on described ITO barrier layer is 10
3~ 10
6Ω cm, the resistivity of described ITO expansion electrode is 10
-3~ 10
-5Ω cm.
Optionally, in described LED structure, the thickness on described ITO barrier layer is
the thickness of described ITO expansion electrode is
LED structure of the present utility model has the following advantages:
First, LED structure of the present utility model, the below ITO of high-impedance state being arranged at P pad as barrier layer to improve the luminosity of LED chip, because the material on expansion electrode and barrier layer is ITO, so there is not the phenomenon that poor adhesion causes P pad or P pad and expansion electrode when packaging and routing or depart from or depart from LED die in later stage application simultaneously.Further, because barrier material is the ITO of high-impedance state, so barrier layer can be done very thin, which solve that subsequent expansion electrode ITO thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
In addition, the high-impedance state ITO pattern of periodic arrangement is arranged at as expansion auxiliary layer on the P type epitaxial loayer corresponding with luminous zone by the utility model, the expansion effect of raising expansion electrode, thus improves the uniformity of luminance of LED chip.Because the material of expansion electrode and expansion auxiliary layer is ITO, there is not expansion electrode with the ITO expansion electrode that causes because adhesiveness is not good of expansion auxiliary layer easily from the phenomenon that LED die comes off; Further, because expansion auxiliary layer is ITO pattern instead of the cavernous structure of the high-impedance state of periodic arrangement, so there is not figure and the unmanageable phenomenon of size; Moreover there is not P type epitaxial loayer by the problem of laughing gas plasma damage in LED structure provided by the utility model.
Accompanying drawing explanation
With reference to accompanying drawing, according to detailed description below, clearly the utility model can be understood.For the sake of clarity, in figure, the relative thickness of each layer and the relative size of given zone are not drawn in proportion.
In the accompanying drawings:
Figure 1A ~ 1F is the device profile structural representation in the utility model embodiment one and two manufacturing process.
Fig. 2 A ~ 2F is the device profile structural representation in the utility model embodiment three and four manufacturing process.
Embodiment
In the research of the problem mentioned for background technology, present inventor finds, although arrange the luminosity that silicon dioxide blocking layer can improve LED component between P pad and P type epitaxial loayer, but the adhesiveness of ITO expansion electrode and silicon dioxide blocking layer is not good, usually makes P pad and ITO expansion electrode when packaging and routing or depart from LED die in later stage application.Based on this, the ITO of high-impedance state is arranged at the below of P pad as barrier layer by the utility model, because the material on expansion electrode and barrier layer is ITO, so there is not the phenomenon that poor adhesion causes P pad and expansion electrode when packaging and routing or depart from LED die in later stage application.
In addition, compared to silicon dioxide blocking layer, what ITO barrier layer can be done thinlyyer (is such as less than
), if this is because its color very thin that silicon dioxide blocking layer does is not easy identification out when carrying out photoetching contraposition, even and if its color very thin that ITO barrier layer is done when carrying out photoetching contraposition also than being easier to identification, and, when silicon dioxide blocking layer thinner thickness, its blocking effect can be deteriorated, even and if the very thin blocking effect that ITO barrier layer is done still can not be influenced, because ITO barrier layer is thinner compared to silicon dioxide blocking layer of the prior art, the step formed is relatively little, when P type epitaxial loayer forms ITO expansion electrode, it is very thin that ITO expansion electrode around ITO barrier layer can not become, which solves in prior art because ITO expansion electrode thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
In addition, the ITO that the utility model also forms periodic arrangement while forming ITO barrier layer on P type epitaxial loayer expands auxiliary layer, the high-impedance state ITO pattern of periodic arrangement is arranged at the expansion effect that the P type epitaxial loayer corresponding with luminous zone can improve ITO expansion electrode as expansion auxiliary layer, thus improve the uniformity of luminance of LED chip, and, because the material of expansion electrode and expansion auxiliary layer is ITO, there is not ITO expansion electrode and the ITO expansion electrode that cause not good with expansion auxiliary layer adhesiveness easily from the phenomenon that LED die comes off.Expansion effect is improved by the cavernous structure arranging cycle arrangement in ITO expansion electrode compared in prior art, form figure and size when ITO expands auxiliary layer to be more prone to control, also do not exist because P type epitaxial loayer to be come out by cavernous structure thus by the problem of laughing gas plasma damage.
Below in conjunction with accompanying drawing, the LED structure that the utility model proposes is described in further detail.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, aid illustration the utility model embodiment lucidly.
Embodiment one
As shown in Figure 1A, one epitaxial wafer is provided, described epitaxial wafer comprises substrate 11 and is formed at the stacked epitaxial structure on described substrate 11, and described stacked epitaxial structure comprises N-type epitaxy layer 121, active layer 122 and P type epitaxial loayer 123 from the bottom to top successively, and described substrate 11 is such as Sapphire Substrate.
As shown in Figure 1B, produce N district table top 1210 by conventional lithographic etching technics on described stacked epitaxial structure, described N district table top 1210 exposes described N-type epitaxy layer 121.In the present embodiment, the degree of depth of described N district table top 1210 is greater than the summation of described active layer 122 and P type epitaxial loayer 123 thickness and is less than the summation of the thickness of described stacked epitaxial structure, that is, the thickness of N-type epitaxy layer 121 is less than the thickness of the N-type epitaxy layer 121 in other regions.
As shown in Figure 1 C, on described P type epitaxial loayer 123, ito thin film is formed by evaporation mode, and form ITO barrier layer figure by photoetching and etching technics, and then adopt ITO barrier layer figure described in fluorine-containing solution-treated, finally the high temperature anneal is carried out to described ITO barrier layer figure, the resistance of described ITO barrier layer figure is made to become large, to form ITO barrier layer 21.
Repeatedly discovery is tested through inventor, utilize fluorine-containing solution-treated ito thin film, carry out high-temperature annealing process to it again, the resistance of ITO can be made to become large (conductivity variation), and thus the utility model utilizes said method to form the ITO barrier layer 21 of high-impedance state.
In the present embodiment, described fluorine-containing solution is DHF (hydrofluoric acid of dilution) solution or BOE (buffered hydrofluoric acid) solution.The atmosphere of described high annealing is nitrogen atmosphere, and the annealing temperature of described high annealing is 400 degree ~ 600 degree.Before process, the resistivity of ito thin film is between 10
-3~ 10
-5between Ω cm, the resistivity of the ito thin film of the high-impedance state formed after above-mentioned process is then between 10
3~ 10
6between Ω cm, the ito thin film of the high-impedance state after process can play the effect on barrier layer.
In preferred version, the thickness on described ITO barrier layer 21 is
described ITO barrier layer 21 is less than
known, described ITO barrier layer 21 is thinner, namely its step formed is less, follow-up when forming ITO expansion electrode on ITO barrier layer 21 and P type epitaxial loayer, it is very thin that ITO expansion electrode around ITO barrier layer 21 can not become, and can solve in prior art because ITO expansion electrode thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
As shown in figure ip, described ITO barrier layer 21 and P type epitaxial loayer 123 form ITO expansion electrode 3, described ITO expansion electrode 3 covers described ITO barrier layer 21 and P type epitaxial loayer 123, and in order to extend current, the resistivity of described ITO expansion electrode is such as 10
-3~ 10
-5Ω cm, the thickness of described ITO expansion electrode 3 is such as
As referring to figure 1e, the ITO expansion electrode 3 above described ITO barrier layer 21 forms P pad 41, in described N district table top 1210, form N pad 42.
As shown in fig. 1f, described ITO expansion electrode 3 forms passivation protection layer 5, described passivation protection layer 5 has the perforate exposing described P pad 41 and N pad 42, to go between, and final formation LED structure described in the utility model.
The present embodiment also provides a kind of LED structure, shown in Figure 1A ~ 1F, comprising:
Substrate 11;
Be formed at the stacked epitaxial structure on described substrate 11, described stacked epitaxial structure comprises N-type epitaxy layer 121, active layer 122 and P type epitaxial loayer 123 from the bottom to top successively, described stacked epitaxial structure has the N district table top 1210 exposing described N-type epitaxy layer 121;
Be formed at the ITO barrier layer 21 on described P type epitaxial loayer 123;
To be formed on described P type epitaxial loayer 123 and ITO expansion electrode 3 on ITO barrier layer 21;
Be formed at the P pad 41 on the ITO expansion electrode 3 above described ITO barrier layer 21 and be formed at the N pad 42 in described N district table top 1210;
Be formed at the passivation protection layer 5 on described ITO expansion electrode 3, described passivation protection layer 5 has the perforate exposing described P pad 41 and N pad 42.
Wherein, described substrate 11 is such as Sapphire Substrate, and the material of described passivation protection layer 5 is such as silicon dioxide.The thickness on described ITO barrier layer 21 is such as
the thickness of described ITO expansion electrode 3 is such as
Embodiment two
The difference of the present embodiment and embodiment one is, is formed the ito thin film of high-impedance state by evaporation mode on P type epitaxial loayer, then forms ITO barrier layer by lithographic etch process.The present embodiment can save high-temperature annealing process, on P type epitaxial loayer, the ito thin film of high-impedance state is directly formed by one or more modes controlled in evaporation process in the oxygen atmosphere of evaporation power, evaporating temperature, evaporation cavity, and then etching forms ITO pattern, can form the ITO barrier layer of high-impedance state.
Concrete, in the present embodiment, in conjunction with Figure 1A ~ 1F, on P type epitaxial loayer 123, first formed the ito thin film of high-impedance state by evaporation mode, by raising evaporation power, reducing evaporating temperature, improving the ito thin film that the modes such as the oxygen atmosphere of evaporation cavity form high-impedance state; Then, by photoetching and wet corrosion technique, ito thin film is graphical, only retain the ito thin film of the high-impedance state of the P pad locations of corresponding follow-up formation, and then form ITO barrier layer 21.
Practice finds, in ITO (tin indium oxide) film, the higher then resistance of the content of oxygen and tin is larger, therefore by improving the content of oxygen and/or tin in ito thin film and then improving its resistance.Specifically by reducing evaporating temperature or raising the content evaporating power and then improve tin in ito thin film, such as, formed ito thin film process in adopt ITO ingot to be that diameter is about 2.5cm, highly be about the cylinder of 10cm, electron beam impact ITO ingot, the indium in ITO ingot and tin is made all to be in vaporized state, under certain cavity temperature, indium and tin all up volatilize, to arrive on distance ITO ingot substrate far away thus deposit film forming on substrate, namely ito thin film is formed, because the volatilization point of tin is lower than indium, so under lower temperature, arriving on-chip tin can be some more, raising evaporation power then can make indium tin all be easy to gasification, the content of tin in ito thin film can be controlled equally.Or, the content of oxygen in ito thin film is improved by improving the flow passing into oxygen.
In the present embodiment, evaporation power is 5% ~ 20% of evaporation board maximum power, and evaporating temperature is 200 degree ~ 300 degree, and oxygen flow is 2sccm ~ 10sccm.
Embodiment three
The difference of the present embodiment and embodiment one is, while on described P type epitaxial loayer 123, the position of corresponding P pad forms ITO barrier layer 21, the ITO also forming array arrangement on described P type epitaxial loayer 123 expands auxiliary layer 22.Shown in composition graphs 2A ~ 2F, in the present embodiment, on described P type epitaxial loayer 123, ito thin film is formed by evaporation mode, and form ITO barrier layer figure and expansion auxiliary layer figure by photoetching and etching technics simultaneously, adopt ITO barrier layer figure described in fluorine-containing solution-treated and expansion auxiliary layer figure again, and the high temperature anneal is carried out to described ITO barrier layer figure and expansion auxiliary layer figure, the resistance of described ITO barrier layer figure and expansion auxiliary layer figure is become large (conductivity variation), to form ITO barrier layer 21 and ITO expansion auxiliary layer 22 simultaneously.
Embodiment four
The difference of the present embodiment and embodiment three is, on P type epitaxial loayer 123, directly formed ITO (tin indium oxide) film of high-impedance state by evaporation mode.Shown in composition graphs 2A ~ 2F, form the ito thin film of high-impedance state by one or more modes controlled in the oxygen atmosphere of evaporation power, evaporating temperature, evaporation cavity, then on P type epitaxial loayer 123, form ITO barrier layer 21 and ITO expansion auxiliary layer 22 by photoetching and wet corrosion technique simultaneously.
In sum, LED structure of the present utility model, the below ITO of high-impedance state being arranged at P pad as barrier layer to improve the luminosity of LED chip, because the material on expansion electrode and barrier layer is ITO, so there is not the phenomenon that poor adhesion causes P pad or P pad and expansion electrode when packaging and routing or depart from or depart from LED die in later stage application simultaneously.In addition, because barrier material is the ITO of high-impedance state, so barrier layer can be done very thin, which solve that subsequent expansion electrode ITO thinning caused LED chip voltage around P pad is high, the problem of poor reliability.
Further, the high-impedance state ITO pattern of periodic arrangement is arranged at as expansion auxiliary layer on the P type epitaxial loayer corresponding with luminous zone by the utility model, the expansion effect of raising expansion electrode, thus improves the uniformity of luminance of LED chip.Because the material of expansion electrode and expansion auxiliary layer is ITO, there is not expansion electrode with the ITO expansion electrode that causes because adhesiveness is not good of expansion auxiliary layer easily from the phenomenon that LED die comes off; Further, because expansion auxiliary layer is ITO pattern instead of the cavernous structure of the high-impedance state of periodic arrangement, so there is not figure and the unmanageable phenomenon of size; Moreover there is not P type epitaxial loayer by the problem of laughing gas plasma damage in LED structure provided by the utility model.
It should be noted that, in this specification, each embodiment adopts the mode of going forward one by one to describe, what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion describe fairly simple, relevant part mutually see.
Although be described in detail the utility model by exemplary embodiment, it should be appreciated by those skilled in the art, above exemplary embodiment is only to be described, instead of in order to limit scope of the present utility model.It should be appreciated by those skilled in the art, when not departing from scope and spirit of the present utility model, above embodiment can be modified.Scope of the present utility model is limited by claims.
Claims (4)
1. a LED structure, is characterized in that, comprising:
Substrate;
Be formed at the stacked epitaxial structure on described substrate, described stacked epitaxial structure comprises N-type epitaxy layer, active layer and P type epitaxial loayer from the bottom to top successively, described stacked epitaxial structure has the N district table top exposing described N-type epitaxy layer;
Be formed at the ITO barrier layer on described P type epitaxial loayer;
To be formed on described P type epitaxial loayer and ITO expansion electrode on ITO barrier layer;
Be formed at the P pad on the ITO expansion electrode above described ITO barrier layer and be formed at the N pad in described N district table top; And
Be formed at the passivation protection layer on described ITO expansion electrode, described passivation protection layer has the perforate exposing described P pad and N pad.
2. LED structure as claimed in claim 1, is characterized in that, also comprises the ITO being formed at array arrangement on described P type epitaxial loayer and expands auxiliary layer.
3. LED structure as claimed in claim 1, it is characterized in that, the resistivity on described ITO barrier layer is 10
3~ 10
6Ω cm, the resistivity of described ITO expansion electrode is 10
-3~ 10
-5Ω cm.
4. LED structure as claimed in claim 1, it is characterized in that, the thickness on described ITO barrier layer is
the thickness of described ITO expansion electrode is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420869326.3U CN204303863U (en) | 2014-12-31 | 2014-12-31 | A kind of LED structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420869326.3U CN204303863U (en) | 2014-12-31 | 2014-12-31 | A kind of LED structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204303863U true CN204303863U (en) | 2015-04-29 |
Family
ID=53109381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420869326.3U Withdrawn - After Issue CN204303863U (en) | 2014-12-31 | 2014-12-31 | A kind of LED structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204303863U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576902A (en) * | 2014-12-31 | 2015-04-29 | 杭州士兰明芯科技有限公司 | LED structure and manufacturing method thereof |
-
2014
- 2014-12-31 CN CN201420869326.3U patent/CN204303863U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576902A (en) * | 2014-12-31 | 2015-04-29 | 杭州士兰明芯科技有限公司 | LED structure and manufacturing method thereof |
| CN104576902B (en) * | 2014-12-31 | 2017-03-01 | 杭州士兰明芯科技有限公司 | A kind of LED structure and preparation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150429 Effective date of abandoning: 20171114 |