CN104576806B - Side incident type PIN photoelectric detector chip and preparation method thereof - Google Patents
Side incident type PIN photoelectric detector chip and preparation method thereof Download PDFInfo
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- CN104576806B CN104576806B CN201410391822.7A CN201410391822A CN104576806B CN 104576806 B CN104576806 B CN 104576806B CN 201410391822 A CN201410391822 A CN 201410391822A CN 104576806 B CN104576806 B CN 104576806B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L31/03046—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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Abstract
The present invention discloses a kind of side incident type PIN photoelectric detector chip and preparation method thereof, comprising: substrate, resilient coating, absorbed layer, transition zone, top layer, contact layer, layer compound passivation, the first protective layer, negative electrode, positive electrode, doped with source region and an anti-reflection film, described substrate has an incidence surface, described anti-reflection film is formed at described incidence surface, formation one " V " type etching tank bottom described substrate, the position of described etching tank is relatively described to be arranged doped with source region, described etching tank has the first side wall and the second sidewall, described the first side wall and described substrate floor at 45 °, described first protective layer is the polyimide covercoat that dielectric constant is low, described contact layer, top layer, the layer compound passivation at transition zone and absorbed layer place forms a P type table top, the layer compound passivation at described resilient coating place forms a N-type table top, described P type table top and N-type table top are all arranged doped with source region is concentric with described.
Description
Technical field
The present invention relates to optical communication transmission field, particularly relate to a kind of side incident type PIN photoelectric detector chip and preparation method thereof.
Background technology
Along with the fast development of optical communication technique, the requirement of people to optical communication transmission rate is also more and more higher.The optical network system of current 10G spreads out in a large number, and and then follow-on optical communication system will develop into the optical network system of taking as the leading factor with 100G optical communication gradually.And PIN photoelectric detector chip is as the acp chip in optical communication system, also thereupon more and more higher to the requirement of receiving velocity.Owing to also not having the receiving velocity of single-chip can reach the light-receiving chip of 100G at present, so the array chip that the PIN photoelectric detector chip that the design of present common 100G light-receiving chip is 28G by 4 receiving velocities forms is formed, this array chip again with passive optical waveguide direct-coupling, form a hybrid integrated device, and then by a passive frequency mixer, thus overall receiving velocity is made to reach 100G.Wherein, the PIN photoelectric detector chip of the single 28G key that will be 100G optical communication receiving system.And, as depicted in figs. 1 and 2, the PIN photoelectric detector chip of current routine adopts conventional design epitaxial wafer 100, the photo-generated carrier that PIN photoelectric detector chip produces after receiving light is longer for the drift time in chip PN junction, in addition larger diffusion source region 200 and planar design, cause chip capacity and distributed constant relatively large, thus cause the receiving velocity of PIN photoelectric detector chip to reach 28G.The receipts light face of current common photoelectric detector chip is all at chip front side or the back side in addition, as the photosurface 300 in Fig. 1 with as the photosurface 400 in Fig. 2, thus direct Butt-coupling cannot be carried out with passive optical waveguide, so can not be used for forming the light-receiving chip that receiving velocity reaches 100G.
Therefore, prior art existing defects, needs to improve.
Summary of the invention
The object of the present invention is to provide a kind of side incident type PIN photoelectric detector chip, its receiving velocity can reach 28G, and adopts mesa structure, can carry out good butt coupling with passive optical waveguide, thus can be used for forming the light-receiving chip of 100G.
Another object of the present invention is to the manufacture method that a kind of side incident type PIN photoelectric detector chip is provided, the side incident type PIN photoelectric detector chip receiving velocity utilizing the method to make can reach 28G, and adopt mesa structure, good butt coupling can be carried out with passive optical waveguide, thus can be used for forming the light-receiving chip of 100G.
Technical scheme of the present invention is as follows: the invention provides a kind of side incident type PIN photoelectric detector chip, comprise: substrate, be formed at the resilient coating on described substrate, be formed at the absorbed layer on described resilient coating, be formed at the transition zone on described absorbed layer, be formed at the top layer on described transition zone, be formed at the contact layer on described top layer, be formed at described substrate, layer compound passivation on resilient coating and contact layer, be formed at the first protective layer on described layer compound passivation, be formed at described first protective layer, negative electrode on layer compound passivation and resilient coating, be formed at described contact layer, positive electrode on layer compound passivation and the first protective layer, be formed at described absorbed layer, transition zone, in top layer and contact layer doped with source region, and an anti-reflection film, described substrate has an incidence surface, described anti-reflection film is formed at described incidence surface, formation one " V " type etching tank bottom described substrate, the position of described etching tank is relatively described to be arranged doped with source region, described etching tank has the first side wall and the second sidewall, described the first side wall and described substrate floor at 45 °, described first protective layer is the polyimide covercoat that dielectric constant is low, described contact layer, top layer, the layer compound passivation at transition zone and absorbed layer place forms a P type table top, the layer compound passivation at described resilient coating place forms a N-type table top, described P type table top and N-type table top are all arranged doped with source region is concentric with described.
To be that N-type is semi-insulating mix FeInP substrate to described substrate; Described resilient coating is that doping content is greater than 1 × 10
18cm
-3inP resilient coating, the thickness of described resilient coating is greater than 1um and is less than 4um; Described absorbed layer is that doping content is lower than 5 × 10
14cm
-3inGaAs absorbed layer, the thickness of described absorbed layer is greater than 1um and is less than 3um; Described transition zone is InGaAsP transition zone, and the thickness of described transition zone is greater than 0.01um and is less than 0.08um, and the cut-off wavelength of described transition zone is respectively 1.3um and 1.08um; Described top layer is InP top layer, and the thickness of described top layer is greater than 0.5um and is less than 3um; Described contact layer is InGaAs contact layer, and the thickness of described contact layer is greater than 0.1um and is less than 1um.
Described doped with the formation of source region employing Zn diffusion technology, the described diameter doped with source region is greater than 10um and is less than 40um, and the described thickness doped with source region is greater than 0.5um and is less than 2um; The height of described P type table top is greater than 3um and is less than 6um, and the thickness of described N-type table top is greater than 2um and is less than 5um;
Described positive electrode and negative electrode are all formed by thermal evaporation or electron beam evaporation, and by titanium, platinum, chromium and gold, one or more are formed described positive electrode, and described negative electrode is made up of gold.
Described side incident type PIN photoelectric detector chip also comprises: be formed at the metallic solder layer bottom described substrate, described metallic solder layer is formed by the mode of electron beam evaporation or thermal evaporation, and the material of described metallic solder layer is one or more in titanium, platinum, gold and common gold solder.
The length of described etching tank is greater than 80um and is less than 200um, and the width of the notch of described etching tank is greater than 40um and is less than 100um, is greater than 30um and is less than 60um described in the centre distance of described etching tank doped with the distance of the central point in source region.
The present invention also provides the manufacture method of a kind of side incident type PIN photoelectric detector chip, comprises the following steps:
Step 101, provide a substrate, adopt Metalorganic chemical vapor deposition method buffer layer, absorbed layer, transition zone, top layer and contact layer successively over the substrate;
Step 102, using plasma strengthen chemical vapour deposition technique and form layer compound passivation on surface, and on this layer compound passivation, form the diffusion region that a diameter is less than 30um, adopt Zn diffusion technology to be formed doped with source region in this diffusion region, the described thickness doped with source region is greater than 0.5um and is less than 2um;
Step 103, adopt wet etching or RIE etching technics that the layer compound passivation at contact layer, top layer, transition zone and absorbed layer place is formed a P type table top, adopt wet etching or RIE etching technics that the layer compound passivation at resilient coating place is formed a N-type table top afterwards again;
Step 104, employing electron beam evaporation or thermal evaporation process form P type contact electrode and N-type contact electrode in layer compound passivation, at surface-coated polyimides, and adopting photolithographic exposure, development, front baking technique to form the first protective layer, this first protective layer is polyimide covercoat;
Step 105, employing electron beam evaporation process form positive electrode and negative electrode on the first protective layer, and described positive electrode is connected with P type contact electrode, and described negative electrode is connected with N-type contact electrode;
Step 106, using plasma strengthen chemical vapour deposition technique at substrate floor deposition formation one second protective layer, adopt photoetching and wet etching or RIE etching technics on this second protective layer, form a V-type channel opening district, etching process is adopted to form " V " type etching tank in this V-type channel opening district, described etching tank has the first side wall and the second sidewall, described the first side wall and described substrate floor at 45 °;
Step 107, employing thermal evaporation or electron beam evaporation process form a metallic solder layer bottom substrate, adopt electron beam evaporation process to form an anti-reflection film on described substrate one side.
To be that N-type is semi-insulating mix FeInP substrate to described substrate; Described resilient coating is the InP resilient coating that doping content is greater than 1 × 1018cm-3, and the thickness of described resilient coating is greater than 1um and is less than 4um; Described absorbed layer is the InGaAs absorbed layer of doping content lower than 5 × 1014cm-3, and the thickness of described absorbed layer is greater than 1um and is less than 3um; Described transition zone is InGaAsP transition zone, and the thickness of described transition zone is greater than 0.01um and is less than 0.08um, and the cut-off wavelength of described transition zone is respectively 1.3um and 1.08um; Described top layer is InP top layer, and the thickness of described top layer is greater than 0.5um and is less than 3um; Described contact layer is InGaAs contact layer, and the thickness of described contact layer is greater than 0.1um and is less than 1um.
The described diameter doped with source region is greater than 10um and is less than 40um, and the described thickness doped with source region is greater than 0.5um and is less than 2um; The height of described P type table top is greater than 3um and is less than 6um, and the thickness of described N-type table top is greater than 2um and is less than 5um;
Described positive electrode and negative electrode are all formed by thermal evaporation or electron beam evaporation, and by titanium, platinum, chromium and gold, one or more are formed described positive electrode, and described negative electrode is made up of gold; The material of described metallic solder layer is one or more in titanium, platinum, gold and common gold solder.
The length of described etching tank is greater than 80um and is less than 200um, and the width of the notch of described etching tank is greater than 40um and is less than 100um, is greater than 30um and is less than 60um described in the centre distance of described etching tank doped with the distance of the central point in source region.
The composition that described step 106 adopts etching process to use corrosive liquid when " V " type etching tank is fallen in the formation of V channel opening district comprises hydrogen bromide, hydrogen peroxide and water, and the ratio of described hydrogen bromide, hydrogen peroxide and water is 1:1:3.
Adopt such scheme, side of the present invention incident type PIN photoelectric detector chip and preparation method thereof, effectively shortens the transit time of photo-generated carrier at chip internal while guaranteeing die response degree; In addition, owing to have employed less designing and mesa structure doped with source region, and adopt the thick polyimide of low-k to make table top first protective layer, thus make the electric capacity of chip drop to below 0.05Pf, and effectively reducing the distributed constant of chip, the receiving velocity simultaneously effectively ensuring chip can reach 28G; In addition, by chip back integrated fall " V " type etching tank, what change chip enters light direction, thus effectively ensure that the side of chip enters optical mode, can be good carry out Butt-coupling with passive optical waveguide, thus ensure that the array chip that this chip forms can be good at being applied in the optical receiver system of 100G.
Accompanying drawing explanation
Fig. 1 is existing front light inlet PIN photoelectric detector chip structure schematic diagram.
Fig. 2 is existing side incident PIN photoelectric detector chip structure schematic diagram.
Fig. 3 is the structural representation of side of the present invention incident type PIN photoelectric detector chip.
Fig. 4 is the cutaway view of A-A line in Fig. 3.
Fig. 5 is the cutaway view of B-B line in Fig. 4.
Fig. 6 be side of the present invention incident type PIN photoelectric detector chip doped with source region decomposing schematic representation.
Fig. 7 is the P type table top decomposing schematic representation of side of the present invention incident type PIN photoelectric detector chip.
Fig. 8 is the N-type table top decomposing schematic representation of side of the present invention incident type PIN photoelectric detector chip.
Fig. 9 is the P type contact electrode of side of the present invention incident type PIN photoelectric detector chip and the decomposing schematic representation of N-type contact electrode.
Figure 10 is the first protective layer decomposing schematic representation of side of the present invention incident type PIN photoelectric detector chip.
Figure 11 is the positive electrode of side of the present invention incident type PIN photoelectric detector chip and the decomposing schematic representation of negative electrode.
Figure 12 is side of the present invention incident type PIN photoelectric detector chip back structural representation.
Figure 13 is the flow chart of the manufacture method of side of the present invention incident type PIN photoelectric detector chip.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Refer to Fig. 3 to Figure 12, the invention provides a kind of side incident type PIN photoelectric detector chip, comprise: substrate 12, be formed at the resilient coating 13 on described substrate 12, be formed at the absorbed layer 14 on described resilient coating 13, be formed at the transition zone 15 on described absorbed layer 14, be formed at the top layer 16 on described transition zone 15, be formed at the contact layer 17 on described top layer 16, be formed at described substrate 12, resilient coating 13 and the layer compound passivation 19 on contact layer 17, be formed at the first protective layer 7 on described layer compound passivation 19, be formed at described first protective layer 7, layer compound passivation 19 and the negative electrode 6 on resilient coating 13, be formed at described contact layer 17, positive electrode 5 on layer compound passivation 19 and the first protective layer 7, be formed at described absorbed layer 14, transition zone 15, top layer 16 with in contact layer 17 doped with source region 10, and an anti-reflection film 11.Described substrate 12 has an incidence surface, and described anti-reflection film 11 is formed at described incidence surface.
Described substrate 12 is the semi-insulating FeInP substrate of mixing of N-type; Described resilient coating 13 is greater than 1 × 10 for doping content
18cm
-3inP resilient coating, the thickness of described resilient coating 13 is greater than 1um and is less than 4um, and preferred scope is greater than 2um and is less than 3um; Described absorbed layer 14 is that doping content is lower than 5 × 10
14cm
-3inGaAs absorbed layer, the thickness of described absorbed layer 14 is greater than 1um and is less than 3um, and preferred scope is greater than 1.5um and is less than 2um; Described transition zone 15 is InGaAsP transition zone, and the thickness of described transition zone 15 is greater than 0.01um and is less than 0.08um, and preferred scope is for being greater than 0.03um and being less than 0.05um, and the cut-off wavelength of described transition zone 15 is respectively 1.3um and 1.08um; Described top layer 16 is InP top layer, and the thickness of described top layer 16 is greater than 0.5um and is less than 3um, and preferred scope is for being greater than 1um and being less than 2um; Described contact layer 17 is InGaAs contact layer, and the thickness of described contact layer 17 is greater than 0.1um and is less than 1um, and preferred scope is greater than 0.3um and is less than 0.5um.
The present invention by adding InGaAsP transition zone 15 between InGaAs absorbed layer 14 and InP top layer 16, thus effectively shorten the transition time of photo-generated carrier between PN heterojunction, in addition, owing to effectively controlling the thickness of absorbed layer 14, thus the photo-generated carrier that shortens to greatest extent is the time getting over of absorbed layer 14.By arranging InGaAs contact layer 17 on top layer 16, because InGaAs has narrower energy gap, good ohmic contact can be formed when it and Metal Contact, thus effectively can reduce the contact resistance of chip.Formation one " V " type etching tank 20 bottom described substrate 12, the position of described etching tank 20 is relatively described to be arranged doped with source region 10, described etching tank 20 has the first side wall 31 and the second sidewall 32, described the first side wall 31 is 45 ° with described substrate 12 bottom surface angulation θ, the layer compound passivation 19 at described contact layer 17, top layer 16, transition zone 15 and absorbed layer 14 place forms a P type table top, the layer compound passivation at described resilient coating 13 place forms a N-type table top, and described P type table top and N-type table top are all arranged doped with source region 10 is concentric with described.
Refer to Fig. 6, describedly Zn diffusion technology is adopted to be formed doped with source region 10, the described diameter L1 doped with source region 10 is greater than 10um and is less than 40um, and preferred scope is greater than 20um and is less than 30um, and the described thickness H1 doped with source region 10 is greater than 0.5um and is less than 2um.Refer to Fig. 7 and Fig. 8, the height H 2 of described P type table top is greater than 3um and is less than 6um, and the diameter L2 of described P type table top is not more than 40um, this P type table top is arranged with doped with source region 10 is concentric, and the external diameter of P type table top is less than 10um with the external diameter spacing L15 doped with source region 10.The thickness H3 of described N-type table top is greater than 2um and is less than 5um, and the diameter L3 of described N-type table top is greater than 50um, and this N-type table top is arranged with aforementioned p-type table top is concentric, and between the external diameter of external diameter and aforementioned p-type table top, L16 distance is greater than 10um.Described P type table top and N-type table top are etched by RIE or wet corrosion technique obtains.
Refer to Figure 10, described first protective layer 7 is the polyimide covercoat that dielectric constant is low, this first protective layer 7 is by conventional photoetching gluing, exposure, the techniques such as development are formed, the thickness H4 of described first protective layer 7 is greater than 2um, white space 33 in the middle of this first protective layer 7 is the majority of a circle, this circle is arranged with described P type table top is concentric, this diameter of a circle L7 is greater than 30um and is less than 60um, and the distance L8 in this white space 33 Edge Distance center of circle is greater than 10um and is less than 15um(as shown in Figure 10), because polyimides has extremely low dielectric constant, so adopt polyimides as the packing material of the first protective layer 7, the electrode capacitance of chip can be effectively reduced.Owing to have employed less designing and mesa structure doped with source region 10; and adopt the thick polyimide of low-k to make table top protective layer (the first protective layer 7); thus make the electric capacity of chip drop to below 0.05Pf, and effectively reduce the distributed constant of chip.Adopt the rate of testing the speed at end of the PIN photoelectric detector chip of said structure to reach 28.6G, meet the requirement of the optical receiver system of 100G.
Refer to Figure 11, described positive electrode 5 and negative electrode 6 all by thermal evaporation or electron beam evaporation process, then are equipped with photoetching process and are formed.Described positive electrode 5 is by titanium (Ti), platinum (Pt), chromium (Cr) and gold (Au), one or more are formed, and described negative electrode 6 is made up of gold.In order to reduce electrode resistance as much as possible, the thickness of usual positive electrode 5 is greater than 2um, and the thickness of negative electrode 6 is greater than 1um.
Refer to Fig. 5 and Figure 12, formation one " V " type etching tank 20 is formed at bottom described substrate 12, the position of described etching tank 20 is relatively described to be arranged doped with source region 10, described etching tank 20 has the first side wall 31 and the second sidewall 32, and described the first side wall 31 is 45 ° with angle θ formed by described substrate 12 bottom surface.The length L13 of described etching tank 20 is greater than 80um and is less than 200um, and the width L14 of the notch of described etching tank is greater than 40um and is less than 100um, is greater than 30um and is less than 60um described in the centre distance of described etching tank doped with the distance L12 of the central point in source region 10.Can guarantee that incident light reflects change after light path through falling the first side wall 31 of " V " type etching tank like this, enter the absorbed layer 14 of chip.
Described side incident type PIN photoelectric detector chip also comprises: be formed at the metallic solder layer 18 bottom described substrate 12, the Main Function of this metallic solder layer 18 be facilitate chip in TO packaging technology with the welding of brazing metal.Described metallic solder layer 18 is formed by the mode of electron beam evaporation or thermal evaporation, and the material of described metallic solder layer 18 is one or more in titanium, platinum, gold and common gold solder (AuSn).
In addition, in order to reduce the light reflex of incident light in the incident process of chip sides, after completing back process making, needing chip to carry out cleavage along the C-C direction of Fig. 3, obtaining the natural cleavage plane of chip along C-C direction.And then the anti-reflection film 11 adopting the mode of electron beam plated film evaporation in C-C cleavage surface to be made up of SiO2/TiO2/ZrO2.From Fig. 5, we can find out the index path of whole chip, incident light is incident from the anti-reflection film 11 at C-C interface, enter chip, the first side wall 31 passing through " V " type etching tank 20 again reflects and changes direction, make incident light enter the absorbed layer 14 of chip, thus the side incidence completing chip receive the object of light.
Refer to Fig. 3 to Figure 13, the present invention also provides the manufacture method of a kind of side incident type PIN photoelectric detector chip, comprises the following steps:
Step 101, provide a substrate 12, adopt Metalorganic chemical vapor deposition method (MOCVD) buffer layer 13, absorbed layer 14, transition zone 15, top layer 16 and contact layer 17 successively on the substrate 12.
Described substrate 12 is the semi-insulating FeInP substrate of mixing of N-type; Described resilient coating 13 is greater than 1 × 10 for doping content
18cm
-3inP resilient coating, the thickness of described resilient coating 13 is greater than 1um and is less than 4um, and preferred scope is greater than 2um and is less than 3um; Described absorbed layer 14 is that doping content is lower than 5 × 10
14cm
-3inGaAs absorbed layer, the thickness of described absorbed layer 14 is greater than 1um and is less than 3um, and preferred scope is greater than 1.5um and is less than 2um; Described transition zone 15 is InGaAsP transition zone, and the thickness of described transition zone 15 is greater than 0.01um and is less than 0.08um, and preferred scope is for being greater than 0.03um and being less than 0.05um, and the cut-off wavelength of described transition zone 15 is respectively 1.3um and 1.08um; Described top layer 16 is InP top layer, and the thickness of described top layer 16 is greater than 0.5um and is less than 3um, and preferred scope is for being greater than 1um and being less than 2um; Described contact layer 17 is InGaAs contact layer, and the thickness of described contact layer 17 is greater than 0.1um and is less than 1um, and preferred scope is greater than 0.3um and is less than 0.5um.
By adding InGaAsP transition zone 15 between InGaAs absorbed layer 14 and InP top layer 16, thus effectively shorten the transition time of photo-generated carrier between PN heterojunction, in addition, owing to effectively controlling the thickness of absorbed layer 14, thus the photo-generated carrier that shortens to greatest extent is the time getting over of absorbed layer 14.By arranging InGaAs contact layer 17 on top layer 16, because InGaAs has narrower energy gap, good ohmic contact can be formed when it and Metal Contact, thus effectively can reduce the contact resistance of chip.
Step 102, using plasma strengthen chemical vapour deposition technique (PECVD) and form layer compound passivation 19 on surface, and on this layer compound passivation 19, form the diffusion region (sign) that a diameter is less than 30um, Zn diffusion technology is adopted to be formed doped with source region 10 in this diffusion region, the described thickness H1 doped with source region 10 is greater than 0.5um and is less than 2um, and preferred scope is greater than 1um and is less than 1.5um.
Described layer compound passivation 19 is by deposited silicon nitride (SiN
x) or silicon dioxide (SiO
2) and formed, and adopt photoetching and wet etching or RIE etching technics to form diffusion region.
Refer to Fig. 6, describedly adopt Zn diffusion technology to be formed doped with source region 10, the described diameter L1 doped with source region 10 is greater than 10um and is less than 40um, and preferred scope is greater than 20um and is less than 30um, and the described thickness H1 doped with source region is greater than 0.5um and is less than 2um.
Step 103, adopt wet etching or RIE etching technics that the layer compound passivation 19 at contact layer 17, top layer 16, transition zone 15 and absorbed layer 14 place is formed a P type table top, adopt wet etching or RIE etching technics that the layer compound passivation 19 at resilient coating 13 place is formed a N-type table top afterwards again.
This step specifically comprises: using plasma strengthens chemical vapour deposition technique and forms thickness and be greater than the diffusion region diaphragm of 0.3um, and adopts photoetching and wet etching or RIE etching technics, and this diffusion region diaphragm makes the corrosion protection district of P type table top.Adopt corrosive liquid (HBr) afterwards, make P type table top by wet etching or RIE etching technics.
Using plasma strengthens chemical vapour deposition technique and forms thickness and be greater than the layer compound passivation diaphragm of 0.8um, and adopts photoetching and wet etching or RIE etching technics, and this layer compound passivation diaphragm makes the corrosion protection district of N-type table top.Adopt corrosive liquid (HBr) afterwards, make N-type table top by wet etching or RIE etching technics.
Refer to Fig. 7 and Fig. 8, the height H 2 of described P type table top is greater than 3um and is less than 6um, and the diameter L2 of described P type table top is not more than 40um, this P type table top is arranged with doped with source region 10 is concentric, and the external diameter of P type table top is less than 10um with the external diameter spacing L15 doped with source region 10.The thickness of described N-type table top is greater than 2um and is less than 5um, and the diameter L3 of described N-type table top is greater than 50um, and this N-type table top is arranged with aforementioned p-type table top is concentric, and between the external diameter of external diameter and aforementioned p-type table top, L16 distance is greater than 10um.
Step 104, employing electron beam evaporation or thermal evaporation process form P type contact electrode 34 and N-type contact electrode 35 in layer compound passivation 19; at surface-coated polyimides; and adopting photolithographic exposure, development, front baking technique to form the first protective layer 7, this first protective layer 7 is polyimide covercoat.
This step specifically comprises: adopt photoetching and wet etching or RIE etching technics, go out a N-type electrode ring shaped contact hole in surface corrosion; Adopt thermal evaporation or electron beam (e-beam) evaporation technology, be greater than gold (Au) layer of 0.4um at chip surface evaporation thickness, and adopt photoetching and wet etching or RIE etching technics, utilize this layer gold to produce N-type contact electrode 35.
Adopt photoetching and wet etching or RIE etching technics, go out P-type electrode contact hole in surface corrosion.Adopt electron beam evaporation process, be greater than the Ti(titanium of 1um at chip surface evaporation thickness)/Pt(platinum)/Au metal level, and adopt photoetching and wet etching or RIE etching technics, utilize this metal level to produce P type contact electrode 34.
Adopt typical polyimide curing technique, under N2 environment, solidify established polyimide covercoat at chip surface.The thickness of described first protective layer 7 is greater than 2um.
Step 105, employing electron beam evaporation process form positive electrode and negative electrode on the first protective layer 7, and described positive electrode 5 is connected with P type contact electrode 34, and described negative electrode 6 is connected with N-type contact electrode 35.
Adopt electron beam evaporation process, the layer gold being again greater than 1um at chip surface evaporation thickness and thickness are greater than the Ti/Pt/Au metal level of 2um, and adopt photoetching and RIE etching technics, form negative electrode 6 and positive electrode 5 respectively.
Step 106, using plasma strengthen chemical vapour deposition technique and form one second protective layer at substrate 12 bottom surface deposition; adopt photoetching and wet etching or RIE etching technics on this second protective layer, form a V-type channel opening district; etching process is adopted to form " V " type etching tank 20 in this V-type channel opening district; described etching tank 20 has the first side wall 31 and the second sidewall 32, and described the first side wall 31 is 45 ° with described substrate 12 bottom surface angulation θ.
In this step, first adopt chip back reduction process that chip thickness is thinned to 90 ± 10um, and the back side of the chip adopting surface with chemical polishing technology polishing thinning.
Described second protective layer is silicon nitride (SiN
x) protective layer, its thickness is 0.15um.Adopt etching process to form the composition using corrosive liquid when falling " V " type etching tank 20 in V channel opening district in this step and comprise hydrogen bromide, hydrogen peroxide and water, described hydrogen bromide, hydrogen peroxide (H
2o
2) and water (H
2o) ratio is 1:1:3.
Step 107, employing thermal evaporation or electron beam evaporation process form a metallic solder layer 18 bottom substrate 12, adopt electron beam evaporation process to form an anti-reflection film 11 on described substrate 12 1 side.
The Main Function of this metallic solder layer 18 be facilitate chip in TO packaging technology with the welding of brazing metal.After formation metallic solder layer 18, adopt the cleavage process of cleavage machine point solution chip, along the incidence surface C-C direction point solution chip of Fig. 3 chips, form chip bar bar, and form minute surface cleavage surface in chip incidence surface C-C direction.Afterwards in the minute surface cleavage surface of chip along C-C direction evaporation by SiO2(silicon dioxide)/ZrO2(zirconium dioxide) anti-reflection film 11 that forms.Use cleavage machine to adopt common chip cleavage process again, the chip bar bar cleavage completing anti-reflection film 22 evaporation is cut into independent chip.
In sum, the invention provides a kind of side incident type PIN photoelectric detector chip and preparation method thereof, while guaranteeing die response degree, effectively shorten the transit time of photo-generated carrier at chip internal; In addition, owing to have employed less designing and mesa structure doped with source region, and adopt the thick polyimide of low-k to make table top first protective layer, thus make the electric capacity of chip drop to below 0.05Pf, and effectively reducing the distributed constant of chip, the receiving velocity simultaneously effectively ensuring chip can reach 28G; In addition, by chip back integrated fall " V " type etching tank, what change chip enters light direction, thus effectively ensure that the side of chip enters optical mode, can be good carry out Butt-coupling with passive optical waveguide, thus ensure that the array chip that this chip forms can be good at being applied in the optical receiver system of 100G.
These are only preferred embodiment of the present invention, be not limited to the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a side incident type PIN photoelectric detector chip, it is characterized in that, comprise: substrate, be formed at the resilient coating on described substrate, be formed at the absorbed layer on described resilient coating, be formed at the transition zone on described absorbed layer, be formed at the top layer on described transition zone, be formed at the contact layer on described top layer, be formed at described substrate, layer compound passivation on resilient coating and contact layer, be formed at the first protective layer on described layer compound passivation, be formed at described first protective layer, negative electrode on layer compound passivation and resilient coating, be formed at described contact layer, positive electrode on layer compound passivation and the first protective layer, be formed at described absorbed layer, transition zone, in top layer and contact layer doped with source region, and an anti-reflection film, described substrate has an incidence surface, described anti-reflection film is formed at described incidence surface, formation one " V " type etching tank bottom described substrate, the position of described etching tank is relatively described to be arranged doped with source region, described etching tank has the first side wall and the second sidewall, described the first side wall and described substrate floor at 45 °, described first protective layer is the polyimide covercoat that dielectric constant is low, described contact layer, top layer, the layer compound passivation at transition zone and absorbed layer place forms a P type table top, the layer compound passivation at described resilient coating place forms a N-type table top, described P type table top and N-type table top are all arranged doped with source region is concentric with described.
2. side according to claim 1 incident type PIN photoelectric detector chip, is characterized in that, to be that N-type is semi-insulating mix FeInP substrate to described substrate; Described resilient coating is that doping content is greater than 1 × 10
18cm
-3inP resilient coating, the thickness of described resilient coating is greater than 1um and is less than 4um; Described absorbed layer is that doping content is lower than 5 × 10
14cm
-3inGaAs absorbed layer, the thickness of described absorbed layer is greater than 1um and is less than 3um; Described transition zone is InGaAsP transition zone, and the thickness of described transition zone is greater than 0.01um and is less than 0.08um, and the cut-off wavelength of described transition zone is respectively 1.3um and 1.08um; Described top layer is InP top layer, and the thickness of described top layer is greater than 0.5um and is less than 3um; Described contact layer is InGaAs contact layer, and the thickness of described contact layer is greater than 0.1um and is less than 1um.
3. side according to claim 1 incident type PIN photoelectric detector chip, it is characterized in that, described doped with the formation of source region employing Zn diffusion technology, the described diameter doped with source region is greater than 10um and is less than 40um, and the described thickness doped with source region is greater than 0.5um and is less than 2um; The height of described P type table top is greater than 3um and is less than 6um, and the thickness of described N-type table top is greater than 2um and is less than 5um;
Described positive electrode and negative electrode are all formed by thermal evaporation or electron beam evaporation, and by titanium, platinum, chromium and gold, one or more are formed described positive electrode, and described negative electrode is made up of gold.
4. side according to claim 1 incident type PIN photoelectric detector chip, it is characterized in that, also comprise: be formed at the metallic solder layer bottom described substrate, described metallic solder layer is formed by the mode of electron beam evaporation or thermal evaporation, and the material of described metallic solder layer is one or more in titanium, platinum, gold and common gold solder.
5. side according to claim 1 incident type PIN photoelectric detector chip, it is characterized in that, the length of described etching tank is greater than 80um and is less than 200um, the width of the notch of described etching tank is greater than 40um and is less than 100um, is greater than 30um and is less than 60um described in the centre distance of described etching tank doped with the distance of the central point in source region.
6. a manufacture method for side incident type PIN photoelectric detector chip, is characterized in that, comprise the following steps:
Step 101, provide a substrate, adopt Metalorganic chemical vapor deposition method buffer layer, absorbed layer, transition zone, top layer and contact layer successively over the substrate;
Step 102, using plasma strengthen chemical vapour deposition technique and form layer compound passivation on surface, and on this layer compound passivation, form the diffusion region that a diameter is less than 30um, adopt Zn diffusion technology to be formed doped with source region in this diffusion region, the described thickness doped with source region is greater than 0.5um and is less than 2um;
Step 103, adopt wet etching or RIE etching technics that the layer compound passivation at contact layer, top layer, transition zone and absorbed layer place is formed a P type table top, adopt wet etching or RIE etching technics that the layer compound passivation at resilient coating place is formed a N-type table top afterwards again;
Step 104, employing electron beam evaporation or thermal evaporation process form P type contact electrode and N-type contact electrode in layer compound passivation, at surface-coated polyimides, and adopting photolithographic exposure, development, front baking technique to form the first protective layer, this first protective layer is polyimide covercoat;
Step 105, employing electron beam evaporation process form positive electrode and negative electrode on the first protective layer, and described positive electrode is connected with P type contact electrode, and described negative electrode is connected with N-type contact electrode;
Step 106, using plasma strengthen chemical vapour deposition technique at substrate floor deposition formation one second protective layer, adopt photoetching and wet etching or RIE etching technics on this second protective layer, form a V-type channel opening district, etching process is adopted to form " V " type etching tank in this V-type channel opening district, described etching tank has the first side wall and the second sidewall, described the first side wall and described substrate floor at 45 °;
Step 107, employing thermal evaporation or electron beam evaporation process form a metallic solder layer bottom substrate, adopt electron beam evaporation process to form an anti-reflection film on described substrate one side.
7. the manufacture method of side according to claim 6 incident type PIN photoelectric detector chip, is characterized in that, to be that N-type is semi-insulating mix FeInP substrate to described substrate; Described resilient coating is that doping content is greater than 1 × 10
18cm
-3inP resilient coating, the thickness of described resilient coating is greater than 1um and is less than 4um; Described absorbed layer is that doping content is lower than 5 × 10
14cm
-3inGaAs absorbed layer, the thickness of described absorbed layer is greater than 1um and is less than 3um; Described transition zone is InGaAsP transition zone, and the thickness of described transition zone is greater than 0.01um and is less than 0.08um, and the cut-off wavelength of described transition zone is respectively 1.3um and 1.08um; Described top layer is InP top layer, and the thickness of described top layer is greater than 0.5um and is less than 3um; Described contact layer is InGaAs contact layer, and the thickness of described contact layer is greater than 0.1um and is less than 1um.
8. the manufacture method of side according to claim 6 incident type PIN photoelectric detector chip, it is characterized in that, the described diameter doped with source region is greater than 10um and is less than 40um, and the described thickness doped with source region is greater than 0.5um and is less than 2um; The height of described P type table top is greater than 3um and is less than 6um, and the thickness of described N-type table top is greater than 2um and is less than 5um;
Described positive electrode and negative electrode are all formed by thermal evaporation or electron beam evaporation, and by titanium, platinum, chromium and gold, one or more are formed described positive electrode, and described negative electrode is made up of gold; The material of described metallic solder layer is one or more in titanium, platinum, gold and common gold solder.
9. the manufacture method of side according to claim 6 incident type PIN photoelectric detector chip, it is characterized in that, the length of described etching tank is greater than 80um and is less than 200um, the width of the notch of described etching tank is greater than 40um and is less than 100um, is greater than 30um and is less than 60um described in the centre distance of described etching tank doped with the distance of the central point in source region.
10. the manufacture method of side according to claim 6 incident type PIN photoelectric detector chip, it is characterized in that, the composition that described step 106 adopts etching process to use corrosive liquid when " V " type etching tank is fallen in the formation of V channel opening district comprises hydrogen bromide, hydrogen peroxide and water.
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| CN109216477B (en) * | 2018-08-02 | 2024-04-12 | 芯思杰技术(深圳)股份有限公司 | Double-cathode photodiode chip and manufacturing method thereof |
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