CN104576575B - Semiconductor package assembly and a manufacturing method thereof - Google Patents
Semiconductor package assembly and a manufacturing method thereof Download PDFInfo
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- CN104576575B CN104576575B CN201310471066.4A CN201310471066A CN104576575B CN 104576575 B CN104576575 B CN 104576575B CN 201310471066 A CN201310471066 A CN 201310471066A CN 104576575 B CN104576575 B CN 104576575B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 239000010410 layer Substances 0.000 claims description 60
- 239000011241 protective layer Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
Abstract
A kind of semiconductor package assembly and a manufacturing method thereof.Semiconductor package part includes substrate, the first conductive pole and chip.Substrate has relative upper surface and lower surface and perforation, and perforation is through to lower surface from upper surface.First conductive pole is through to lower surface from upper surface, and exposes from the medial surface of perforation.In chip buried-in perforation.
Description
Technical field
There is conduction the invention relates to a kind of semiconductor package assembly and a manufacturing method thereof, and in particular to one kind
The semiconductor package assembly and a manufacturing method thereof of post.
Background technology
Conventional semiconductor package part includes substrate and several conductive poles, conductive pole are formed in substrate, to be electrically connected with base
Relative two faces of plate.However, conductive pole has certain external diameter, it occupies the area of substrate, make the size of semiconductor package part without
Method effectively reduces.
The content of the invention
The present invention is related to a kind of semiconductor package assembly and a manufacturing method thereof, by the design for changing conductive pole, can reduce
The size of semiconductor package part.
A kind of according to the present invention it is proposed that semiconductor package part.Semiconductor package part include a substrate, one first conductive pole and
One chip.There is substrate a relative upper surface to be through to lower surface from upper surface with a lower surface and a perforation, perforation.First
Conductive pole is through to lower surface from upper surface, and exposes from the medial surface of perforation.In chip buried-in perforation.
A kind of according to the present invention it is proposed that manufacture method of semiconductor package part.The manufacture method of semiconductor package part includes
Following steps.A substrate is provided, substrate has a relative upper surface and a lower surface；One first conductive pole is formed from substrate
Upper surface is through to lower surface；Form a perforation and be through to lower surface from the upper surface of substrate, through hole passes through the first conductive pole
A part, the first conductive pole is exposed from a medial surface of perforation；And a chip is inside buried in perforation.
For the above of the present invention can be become apparent, preferred embodiment cited below particularly, and accompanying drawing appended by cooperation, make
Describe in detail as follows：
Brief description of the drawings
Figure 1A illustrates the sectional view of the semiconductor package part according to one embodiment of the invention.
Figure 1B illustrates the top view (not illustrating the first protective layer and the first conductive layer) of Figure 1A semiconductor package part
Fig. 2 illustrates the top view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 A to 4M illustrate the process drawing of Figure 1A semiconductor package part.
Fig. 5 A to 5B illustrate the process drawing of Fig. 3 semiconductor package part.
【Main element symbol description】
10：Paste support plate
100、200、300：Semiconductor package part
110：Substrate
110a：Perforation
110b、130b、150b、160b：Lower surface
110s1、150s：Medial surface
110s2、130s、170s：Lateral surface
110u、150u、160u：Upper surface
120：Chip
120u：Active surface
120b：Non-active face
121：Connection pad
120s：Lateral surface
130：First protective layer
130’：First protective layer material
130a1：First perforate
130a2：Second perforate
130a3：3rd perforate
140：First conductive layer
150、250：First conductive pole
150a：First perforation
160：Second conductive pole
160a：Second perforation
170：Second protective layer
170’：Second protective layer material
170a1：4th perforate
170a2：5th perforate
170a3：6th perforate
180：Second conductive layer
390：3rd conductive layer
D1、D1’、D2：External diameter
D3：Internal diameter
H1：Spacing
Embodiment
Figure 1A is refer to, it illustrates the sectional view of the semiconductor package part according to one embodiment of the invention.Semiconductor packages
Part 100 includes substrate 110, chip 120, the first protective layer 130, the first conductive layer 140, at least one first conductive pole 150, at least
One second conductive pole 160, the second protective layer 170 and the second conductive layer 180.
Substrate 110 is formed by high molecular polymer.Substrate 110 has relative upper surface 110u and lower surface 110b
And perforation 110a.Perforation 110a is through to lower surface 110b from the upper surface 110u of substrate 110.
It is embedded in chip 120 in perforation 110a.Chip 120 has relative active surface 120u and non-active face 120b, its
The active surface 120u of the chips 120 and upper surface 110u of substrate 110 makes the first conductive layer 140 can be in base towards same direction
The same side of plate 110 is electrically connected with the first conductive pole 150, the active surface 120u of the second conductive pole 160 and chip 120.In addition, core
Piece 120 includes an at least connection pad 121, the circuit for making the first conductive layer 140 to be electrically connected with by connection pad 121 inside chip 120.
First protective layer 130 be formed at the lateral surface 120s and perforation 110a of chip 120 medial surface 110s1 (Figure 1B) it
Between, with fixed chip 120 in the position in perforation 110a.In addition, the upper surface 110u of the first protective layer 130 covering substrate 110
And there is at least one first perforate 130a1 and at least one second perforate 130a2, wherein the first perforate 130a1 exposes the first conduction
The upper surface 150u of post 150, and the active surface 120u of the second perforate 130a2 exposed chips 120.
First protective layer 130 can be by being, for example, polyimides (PI), epoxy glass-fiber-fabric prepreg（Prepreg,PP）Or
ABF (Ajinomoto Build-up Film) resin is formed.In another embodiment, the first protective layer 130 is, for example, heat conduction
Glue, it directly bonds the medial surface 110s1 (Figure 1B) of chip 120 and perforation 110a, the heat of chip 120 is passed through the first protection
Layer 130 is quickly outside conduction to semiconductor package part 100.
First conductive layer 140 is, for example, routing layer, and it includes an at least connection pad and an at least cabling.First conductive layer 140
First conductive pole 150 and chip 120 are electrically connected with by the first perforate 130a1 and the second perforate 130a2.In addition, first is conductive
The material of layer 140 includes copper or its alloy, and it is, for example, to be formed with electroplating.Copper has excellent thermal conductivity and electric conductivity.
First conductive pole 150 is the most conductive pole of inner side in semiconductor package part 100.First conductive pole 150 is from substrate 110
Upper surface 110u be through to the lower surface 110b of substrate 110, and distinguish from the upper surface 110u and lower surface 110b of substrate 110
Expose upper surface 150u and lower surface 150b, led wherein the first conductive layer 140 is electrically connected with first by the first perforate 130a1
The upper surface 150u of electric post 150.In addition, the material of the first conductive pole 150 includes copper or copper alloy, it may, for example, be plating skill
Art is formed.
Second conductive pole 160 is through to the lower surface 110b of substrate 110 from the upper surface 110u of substrate 110.First protection
Layer 130 exposes the upper surface 160u of the second conductive pole 160 with more at least one the 3rd perforate 130a3, the 3rd perforate 130a3, can
The first conductive layer 140 is set to be electrically connected with the second conductive pole 160 by the 3rd perforate 130a3.
Second protective layer 170 covers the lower surface 110b of substrate 110 and has at least one the 4th perforate 170a1 and at least one
5th perforate 170a2, wherein the 4th perforate 170a1 exposes the first conductive pole 150, and the 5th perforate 170a2 exposes the second conduction
Post 160.
Second conductive layer 180 is, for example, routing layer, and it includes an at least connection pad and an at least cabling.Second conductive layer 180
First conductive pole 150 is electrically connected with by the 4th perforate 170a1, and the second conductive pole is electrically connected with by the 5th perforate 170a2
160.In addition, the material and forming method of the second conductive layer 180 hold this and repeated no more similar in appearance to the first conductive layer 140.
Figure 1B is refer to, it illustrates the top view of Figure 1A semiconductor package part and (does not illustrate the first protective layer and first lead
Electric layer).The spacing H1 of first conductive pole 150 and chip 120 is about 50 microns, or is smaller than 50 microns.When the first conductive pole
150 further away from chip 120, then bigger and semiconductor package part 100 the sizes of spacing H1 are bigger.
In the present embodiment, because the position of the first conductive pole 150 is to expose toward inside contracting from perforation 110a, therefore it can shorten
Spacing H1, and then reduce the size of semiconductor package part 100 or increase the row of conductive pole.For structure, the first conductive pole
150 expose a medial surface 150s from perforation 110a, and it generally aligns with perforation 110a medial surface 110s1, make the first conduction
Spacing between the medial surface 150s and perforation 110a of post 150 medial surface 110s1 is zero.In addition, compared to the second conductive pole
160, because the first conductive pole 150 passes through cutting in manufacture craft, therefore its outer diameter D 1 is smaller.
The conductive pole 160 of first conductive pole 150 to the second is close to perforation 110a.In the present embodiment, the first conductive pole 150 is base
The most conductive pole of inner side in plate 110, and the second conductive pole 160 is outermost conductive pole in substrate 110, makes several first conductions
Post 150 forms two row's ring shaped conductive posts with several second conductive poles 160.In another embodiment, the first conductive pole 150 is led with second
It can make the first conductive pole 150, the second conductive pole 160 and other conductive studs into three formed with other conductive poles between electric post 160
Arrange the conductive pole of the above.
In the present embodiment, several first conductive poles 150 are around chip 120.First conductive pole 150 optionally electrically connects
An earth terminal is connected to, to provide electromagnetic interference shield function.
Fig. 2 is refer to, it illustrates the top view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 200 includes substrate 110, chip 120, the first protective layer 130, the first conductive layer 140 (not illustrating), single first conductive pole
250th, at least one second conductive pole 160, the second protective layer 170 (not illustrating) and the second conductive layer 180 (not illustrating).With Figure 1B's
Unlike semiconductor package part 100, first conductive pole 250 of the present embodiment is a closed ring conductive pole, its circular chip
120, it can so lift more preferable heat sinking function.In another embodiment, the first conductive pole 250 can be electrically connected with an earth terminal, with
Electromagnetic interference shield function is provided.
Fig. 3 is refer to, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 300 includes substrate 110, chip 120, the first protective layer 130, the first conductive layer 140, at least one first conductive pole 150, at least
One second conductive pole 160, the second protective layer 170, the second conductive layer 180 and the 3rd conductive layer 390.
In the present embodiment, the 3rd conductive layer 390 is formed at the lower surface 110b of substrate 110,120 non-active face of chip
120b, the first conductive pole 150 lower surface 150b on.In one embodiment, the 3rd conductive layer 390 is heat-conducting layer, makes chip 120
Heat can be rapidly conducted to outside semiconductor package part 300 by the 3rd conductive layer 390.3rd conductive layer 390 can be by being, for example,
Copper, aluminium or the good metal of thermal conductivity are made.In addition, the 3rd conductive layer 390 is complete Rotating fields without pierced pattern, it is covered
The whole non-active face 120b of chip 120, and provide a big area of dissipation, and then make chip 120 heat rapidly conduct to
It is extraneous.
In another embodiment, the 3rd conductive layer 390 can be electrically connected with an earth terminal.Because the 3rd conductive layer 390 is complete
Rotating fields without pierced pattern and the whole non-active face 120b for covering chip 120, therefore an excellent electromagnetic interference can be provided
Shield effectiveness.
Second protective layer 170 covers the lower surface 110b and the 3rd conductive layer 390 of substrate 110.Second protective layer 170 has
At least one the 6th perforate 170a3, wherein the 6th perforate 170a3 exposes the 3rd conductive layer 390, the second conductive layer 180 is set to pass through
6th perforate 170a3 is electrically connected with the 3rd conductive layer 390.
In another embodiment, Fig. 3 the first conductive pole 150 can also be substituted with Fig. 2 the first conductive pole 250.
Fig. 4 A to 4M are refer to, it illustrates the process drawing of Figure 1A semiconductor package part 100.
As shown in Figure 4 A, there is provided substrate 110.Substrate 110 has relative upper surface 110u and lower surface 110b.
As shown in Figure 4 B, e.g. patterning techniques can be used, form at least one first perforation 150a and at least one second
Perforation 160a is through to lower surface 110b from the upper surface 110u of substrate 110.Above-mentioned patterning techniques are, for example, photoetching process
（photolithography）, chemical etching（chemical etching）, laser drill（laser drilling）Or machinery
Drilling（mechanical drilling）.
As shown in Figure 4 C, e.g. material can be used to form technology, forms conductive material in the first perforation 150a and second
With the first conductive pole 150 ' of formation and the second conductive pole 160 in perforation 160a.Wherein, conductive material be, for example, copper, its alloy or
Other suitable conductive materials.The outer diameter D 1 ' of first conductive pole 150 ', it is approximately equal to the outer diameter D 2 of the second conductive pole 160.Material
It is, for example, chemical gaseous phase depositing, electroless plating method that material, which forms technology,（electroless plating）, electrolysis plating
（electrolytic plating）.
Although figure does not illustrate, connection pad or surface-treated layer (surface finish) so can be also formed in the first conductive pole
On the upper surface 160u of 150 ' upper surface 150u and the second conductive pole 160.
As shown in Figure 4 D, e.g. above-mentioned patterning techniques can be used, form an at least perforation 110a from the upper of substrate 110
Surface 110u is through to lower surface 110b.The first conductive pole 150 ' is removed because perforation 110a passes through the first conductive pole 150 '
Portion of material, therefore the outer diameter D 1 ' of the first conductive pole 150 ' is reduced into D1.
In the case where perforation 110a outer diameter D 3 is constant, when the first conductive pole 150 ' is closer to perforation 110a, then cut
The outer diameter D 1 of the first conductive pole 150 afterwards is smaller；Consequently, it is possible to the size of semiconductor package part 100 is smaller, but the first conductive pole
150 electrical quality is deteriorated.In one embodiment, the outer diameter D 1 of the first conductive pole 150 after cutting is about first before cutting
The half of the outer diameter D 1 ' of conductive pole 150 ', it can so obtain the semiconductor package part 100 and first for meeting expected small size
The excellent electrical quality of conductive pole 150.
As shown in Figure 4 E, chip 120 is inside buried in perforation 110a.In the present embodiment, can first set Fig. 4 D substrate 110 in
Paste on support plate 10, then chip 120 is pasted on via perforation 110a again and pasted on support plate 10, with fixed chip 120 and base
The relative position of plate 110.Chip 120 has relative active surface 120u and non-active face 120b, and its chips 120 is with non-active
Face 120b is on stickup support plate 10.
As illustrated in figure 4f, to be, for example, coating technique, the first protective layer material 130 ' is formed in the lateral surface of chip 120
Space and the lateral surface 120s of chip 120 and first between 120s and perforation 110a medial surface 110s1 (not illustrating) is conductive
Space between the medial surface 150s of post 150, and cover the upper surface 110u of substrate 110, the active surface 120u of chip 120,
The upper surface 150u of one conductive pole 150 and the second conductive pole 160 upper surface 160u.Above-mentioned coating technique is, for example, to print
（printing）, spin coating（spinning）Or spraying（spraying）.
As shown in Figure 4 G, to be, for example, above-mentioned material removal technology, at least one first perforate 130a1, at least 1 the are formed
Two perforate 130a2 and at least one the 3rd perforate 130a3, wherein the first perforate 130a1 exposes the upper surface of the first conductive pole 150
150u, the second perforate 130a2 exposed chips 120 connection pad 121, and the 3rd perforate 130a3 exposes the upper table of the second conductive pole 160
Face 160u.
As shown at figure 4h, to be, for example, above-mentioned material formation technology, the first conductive layer 140 is formed, wherein the first conductive layer
140u is electrically connected at the first conductive pole 150 by the first perforate 130a1, is electrically connected at chip by the second perforate 130a2
120 connection pad 121 and the second conductive pole 160 is electrically connected at by the 3rd perforate 131.
As shown in fig. 41, remove and paste support plate 10, to expose the non-active face of the lower surface 110b of substrate 110, chip 120
120b, the lower surface 150b of the first conductive pole 150 and the second conductive pole 160 lower surface 160b.
As shown in fig. 4j, to be, for example, above-mentioned coating technique, formed under the second protective layer material 170 ' covering substrate 110
Surface 110b, the non-active face 120b of chip 120, the following table of the lower surface 150b of the first conductive pole 150 and the second conductive pole 160
Face 160b.
As shown in Figure 4 K, to be, for example, above-mentioned patterning techniques, at least one the 4th perforate 170a1 and at least one the 5th is formed
Perforate 170a2 is in the second protective layer material 170 ', wherein the 4th perforate 170a1 exposes the lower surface 150b of the first conductive pole 150,
And the 5th perforate 170a2 exposes the lower surface 160b of the second conductive pole 160.
As illustrated in fig. 4l, to be, for example, above-mentioned material formation technology, the second conductive layer 180 is formed, wherein the second conductive layer
180 are electrically connected at the first conductive pole 150 by the first perforate 130a1, are electrically connected at chip by the second perforate 130a2
120 active surface 120u and the second conductive pole 160 is electrically connected at by the 3rd perforate 131.
As shown in fig. 4m, with such as cutter or laser, an at least Cutting Road P1 is formed by the first protective layer 130, substrate
110 and second protective layer 170, to form the semiconductor package part 100 at least shown in a Figure 1A.After cutting, the first protective layer
130th, the protective layer 170 of substrate 110 and second forms lateral surface 130s, 110s2 and 170s, wherein lateral surface 130s, 110s2 respectively
Generally align with 170s, such as flush.
In the manufacturing process of Fig. 2 semiconductor package part 200, the first perforation 150a is in closed ring, so that after
Continuous the first conductive pole 250 formed is in closed ring.Remaining step of semiconductor package part 200 is similar in appearance to semiconductor package part
100 corresponding step, holds this and repeats no more.
Fig. 5 A to 5B are refer to, it illustrates the process drawing of Fig. 3 semiconductor package part 300.
As shown in Figure 5A, remove after pasting support plate 10, to be, for example, material formation technology, form the 3rd conductive layer 390 and cover
The non-active face 120b of cover core piece 120, the lower surface 150b of the first conductive pole 150 and the first protective layer 130 lower surface 130b.
As shown in Figure 5 B, above-mentioned coating technique and patterning techniques can be used, form the second protective layer 170 covering substrate
110 lower surface 110b, the second conductive pole 160 lower surface 160b and the 3rd conductive layer 390, wherein the second protective layer 170 has
There are at least one the 5th perforate 170a2 and at least one the 6th perforate 170a3, wherein the 5th perforate 170a2 exposes the second conductive pole 160
Lower surface 160b, and the 6th perforate 170a3 exposes the 3rd conductive layer 390.In the present embodiment, the first conductive pole 150 can pass through
3rd conductive layer 390 and the 6th perforate 170a3 are electrically connected at an external circuit elements, e.g. circuit board, chip or partly lead
Body packaging part.
Remaining manufacturing step of Fig. 3 semiconductor package part 300 holds similar in appearance to the corresponding step of semiconductor package part 100
This is repeated no more.
In summary, although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, protection scope of the present invention is worked as and is defined depending on appended claims institute defender.
Claims (10)
1. a kind of semiconductor package part, including：
One substrate, has a relative upper surface and a lower surface and a perforation, and the perforation is through to the following table from the upper surface
Face；
One first conductive pole, the lower surface is through to from the upper surface, and exposed from the medial surface of the perforation；
One chip, have an active surface is simultaneously interior to bury in the perforation；
One first protective layer, it is formed between the lateral surface of the chip and the medial surface of the perforation, first protective layer covering
Simultaneously expose the upper table of first conductive pole with one first perforate and one second perforate, first perforate in the upper surface of the substrate
Face, and the active surface of the chip is exposed in second perforate；And
One first conductive layer, by first perforate and second perforate, first conductive pole is electrically connected to the chip.
2. semiconductor package part as claimed in claim 1, it is characterised in that further include：
One second conductive pole, be through to the lower surface of the substrate from the upper surface of the substrate and than first conductive pole away from
The perforation；
Wherein, first protective layer has more one the 3rd perforate, and the upper surface of second conductive pole is exposed in the 3rd perforate, and this
One conductive layer is electrically connected with second conductive pole by the 3rd perforate.
3. semiconductor package part as claimed in claim 1, it is characterised in that further include：
One second protective layer, the lower surface of the substrate is covered, and there is one the 4th perforate, the 4th perforate is exposed this and first led
The lower surface of electric post；
Wherein, the semiconductor package part further includes one second conductive layer, and second conductive layer is electrically connected with by the 4th perforate
First conductive pole.
4. semiconductor package part as claimed in claim 3, it is characterised in that further include：
One second conductive pole, be through to the lower surface of the substrate from the upper surface of the substrate and than first conductive pole away from
The perforation；
Wherein, second protective layer has more one the 5th perforate, and the lower surface of second conductive pole is exposed in the 5th perforate, and this
Two conductive layers are electrically connected with second conductive pole by the 5th perforate.
5. semiconductor package part as claimed in claim 1, it is characterised in that first conductive pole has a lower surface, and this
The lower surface of one conductive pole is exposed from the lower surface of the substrate, and the chip has a non-active face, the semiconductor package part
Further include：
One the 3rd conductive layer, is formed at the non-active face of the chip and on the lower surface of first conductive pole and is electrically connected with
The lower surface of first conductive pole.
6. semiconductor package part as claimed in claim 5, it is characterised in that further include：
One second protective layer, covers the lower surface and the 3rd conductive layer of the substrate, and has one the 6th perforate, and the 6th opens
Expose the 3rd conductive layer in hole；The semiconductor package part further includes：
One second conductive layer, the 3rd conductive layer is electrically connected with by the 6th perforate.
7. semiconductor package part as claimed in claim 1, it is characterised in that first conductive pole is closed ring conduction
Post, the closed ring conductive pole is around the chip.
8. a kind of manufacture method of semiconductor package part, including：
A substrate is provided, the substrate has a relative upper surface and a lower surface；
Form one first conductive pole and be through to the lower surface from the upper surface of the substrate；
Form a perforation and be through to the lower surface from the upper surface of the substrate, the through hole passes through one of first conductive pole
Point, first conductive pole is exposed from a medial surface of the perforation；And
A chip is inside buried in the perforation.
9. manufacture method as claimed in claim 8, it is characterised in that further include：
One first protective layer is formed between this of the lateral surface of the chip and the perforation medial surface.
10. manufacture method as claimed in claim 9, it is characterised in that the chip has an active surface；In formation first guarantor
The step of sheath, includes：
Form the upper surface that one first protective layer material covers the substrate；And
Form one first perforate and one second perforate and expose first conduction in first protective layer material, wherein first perforate
The upper surface of post, and the active surface of the chip is exposed in second perforate；
The manufacture method further includes：
Form one first conductive layer, wherein first conductive layer by first perforate and second perforate be electrically connected with this first
Conductive pole and the chip.
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| CN201310471066.4A CN104576575B (en) | 2013-10-10 | 2013-10-10 | Semiconductor package assembly and a manufacturing method thereof |
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| CN109768026B (en) * | 2018-12-20 | 2021-06-15 | 西安华为技术有限公司 | Embedded substrate and manufacturing method thereof |
| CN110957291A (en) * | 2019-12-18 | 2020-04-03 | 江苏中科智芯集成科技有限公司 | Wafer-level double-sided fan-out structure and packaging method thereof |
| CN110970397A (en) * | 2019-12-19 | 2020-04-07 | 江苏中科智芯集成科技有限公司 | Stack packaging structure and preparation method thereof |
| EP4101270A4 (en) * | 2020-02-06 | 2024-01-03 | Ericsson Telefon Ab L M | Printed circuit board |
| CN112908943A (en) * | 2021-01-12 | 2021-06-04 | 华为技术有限公司 | Embedded packaging structure, preparation method thereof and terminal equipment |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829416A (en) * | 2005-02-28 | 2006-09-06 | 三星电机株式会社 | Embedded chip printed circuit board and method of manufacturing the same |
| CN101211945A (en) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | Semiconductor image element package structure with die receiving through-hole and method of the same |
| CN101221936A (en) * | 2007-01-03 | 2008-07-16 | 育霈科技股份有限公司 | Wafer level package with die receiving through-hole and method of the same |
| CN101236935A (en) * | 2008-03-07 | 2008-08-06 | 日月光半导体制造股份有限公司 | Bearer with built-in part and its making method |
| CN101325188A (en) * | 2007-03-30 | 2008-12-17 | 育霈科技股份有限公司 | Wafer level semiconductor package with dual side build-up layers and method thereof |
| CN101728368A (en) * | 2008-10-30 | 2010-06-09 | 育霈科技股份有限公司 | Semiconductor assembly packaging structure with a plurality of grains and packaging method thereof |
| CN101937881A (en) * | 2009-06-29 | 2011-01-05 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and packaging method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090130727A (en) * | 2008-06-16 | 2009-12-24 | 삼성전기주식회사 | Printed circuit board with electronic components embedded therein and method for fabricating the same |
-
2013
- 2013-10-10 CN CN201310471066.4A patent/CN104576575B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829416A (en) * | 2005-02-28 | 2006-09-06 | 三星电机株式会社 | Embedded chip printed circuit board and method of manufacturing the same |
| CN101211945A (en) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | Semiconductor image element package structure with die receiving through-hole and method of the same |
| CN101221936A (en) * | 2007-01-03 | 2008-07-16 | 育霈科技股份有限公司 | Wafer level package with die receiving through-hole and method of the same |
| CN101325188A (en) * | 2007-03-30 | 2008-12-17 | 育霈科技股份有限公司 | Wafer level semiconductor package with dual side build-up layers and method thereof |
| CN101236935A (en) * | 2008-03-07 | 2008-08-06 | 日月光半导体制造股份有限公司 | Bearer with built-in part and its making method |
| CN101728368A (en) * | 2008-10-30 | 2010-06-09 | 育霈科技股份有限公司 | Semiconductor assembly packaging structure with a plurality of grains and packaging method thereof |
| CN101937881A (en) * | 2009-06-29 | 2011-01-05 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and packaging method thereof |
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