CN104576575A - Semiconductor packaging piece and manufacture method thereof - Google Patents
Semiconductor packaging piece and manufacture method thereof Download PDFInfo
- Publication number
- CN104576575A CN104576575A CN201310471066.4A CN201310471066A CN104576575A CN 104576575 A CN104576575 A CN 104576575A CN 201310471066 A CN201310471066 A CN 201310471066A CN 104576575 A CN104576575 A CN 104576575A
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- perforate
- conductive pole
- conductive
- substrate
- chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000004806 packaging method and process Methods 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000010410 layer Substances 0.000 claims description 58
- 239000011241 protective layer Substances 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
Abstract
The invention discloses a semiconductor packaging piece. The semiconductor packaging piece comprises a substrate, a first conducting post and a chip; the substrate is provided with an upper surface and a lower surface which are opposite to each other; a through hole penetrates through the substrate from the upper surface to the lower surface. The first conducting post penetrates through the substrate from the upper surface to the lower surface and is exposed to the inner side surface of the through hole. The chip is embedded in the through hole.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and relate to a kind of semiconductor package part and the manufacture method thereof with conductive pole especially.
Background technology
Conventional semiconductor package part comprises substrate and several conductive pole, and conductive stud is formed in substrate, to be electrically connected relative two of substrate.But conductive pole has certain external diameter, it occupies the area of substrate, and the size of semiconductor package part cannot effectively be reduced.
Summary of the invention
The present invention has about a kind of semiconductor package part and manufacture method thereof, by the design changing conductive pole, can reduce the size of semiconductor package part.
According to the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a substrate, one first conductive pole and a chip.Substrate has a relative upper surface and a lower surface and a perforation, and perforation is through to lower surface from upper surface.First conductive pole is through to lower surface from upper surface, and exposes from the medial surface of perforation.In chip buried-in perforation.
According to the present invention, a kind of manufacture method of semiconductor package part is proposed.The manufacture method of semiconductor package part comprises the following steps.There is provided a substrate, substrate has a relative upper surface and a lower surface; Form one first conductive pole and be through to lower surface from the upper surface of substrate; Form a perforation and be through to lower surface from the upper surface of substrate, through hole, through a part for the first conductive pole, makes the first conductive pole expose from a medial surface of perforation; And, inside bury a chip in perforation.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below:
Accompanying drawing explanation
Figure 1A illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.
Figure 1B illustrates the vertical view (not illustrating the first protective layer and the first conductive layer) of the semiconductor package part of Figure 1A
Fig. 2 illustrates the vertical view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 A to 4M illustrates the process drawing of the semiconductor package part of Figure 1A.
Fig. 5 A to 5B illustrates the process drawing of the semiconductor package part of Fig. 3.
[main element symbol description]
10: paste support plate
100,200,300: semiconductor package part
110: substrate
110a: perforation
110b, 130b, 150b, 160b: lower surface
110s1,150s: medial surface
110s2,130s, 170s: lateral surface
110u, 150u, 160u: upper surface
120: chip
120u: active surface
120b: non-active
121: connection pad
120s: lateral surface
130: the first protective layers
130 ': the first protective layer material
130a1: the first perforate
130a2: the second perforate
130a3: the three perforate
140: the first conductive layers
150,250: the first conductive poles
150a: the first perforation
160: the second conductive poles
160a: the second perforation
170: the second protective layers
170 ': the second protective layer material
170a1: the four perforate
170a2: the five perforate
170a3: the six perforate
180: the second conductive layers
390: the three conductive layers
D1, D1 ', D2: external diameter
D3: internal diameter
H1: spacing
Embodiment
Please refer to Figure 1A, it illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 comprise substrate 110, chip 120, first protective layer 130, first conductive layer 140, at least one first conductive pole 150, at least one second conductive pole 160, the second protective layer 170 and the second conductive layer 180.
Substrate 110 formed by high molecular polymer.Substrate 110 has relative upper surface 110u and lower surface 110b and perforation 110a.Perforation 110a is through to lower surface 110b from the upper surface 110u of substrate 110.
Be embedded in chip 120 in perforation 110a.Chip 120 has relative active surface 120u and non-active 120b, the active surface 120u of its chips 120 and upper surface 110u of substrate 110, towards same direction, makes the first conductive layer 140 can be electrically connected the active surface 120u of the first conductive pole 150, second conductive pole 160 and chip 120 in the same side of substrate 110.In addition, chip 120 comprises at least one connection pad 121, makes the first conductive layer 140 be electrically connected the circuit of chip 120 inside by connection pad 121.
First protective layer 130 is formed between the lateral surface 120s of the chip 120 and medial surface 110s1 (Figure 1B) of perforation 110a, with the position of fixed chip 120 in perforation 110a.In addition; the upper surface 110u of the first protective layer 130 covered substrate 110 also has at least one first perforate 130a1 and at least one second perforate 130a2; wherein the first perforate 130a1 exposes the upper surface 150u of the first conductive pole 150, and the active surface 120u of the second perforate 130a2 exposed chip 120.
First protective layer 130 can by be such as polyimides (PI), epoxy glass-fiber-fabric prepreg (Prepreg, PP) or ABF (Ajinomoto Build-up Film) resin formed.In another embodiment, the first protective layer 130 is such as heat-conducting glue, and it directly bonds chip 120 and the medial surface 110s1 (Figure 1B) of perforation 110a, and the heat of chip 120 is conducted to outside semiconductor package part 100 fast by the first protective layer 130.
First conductive layer 140 is such as routing layer, and it comprises at least one connection pad and at least one cabling.First conductive layer 140 is electrically connected the first conductive pole 150 and chip 120 by the first perforate 130a1 and the second perforate 130a2.In addition, the material of the first conductive layer 140 comprises copper or its alloy, and it is such as electroplate formation.Copper has excellent thermal conductivity and conductivity.
First conductive pole 150 is conductive poles of inner side in semiconductor package part 100.First conductive pole 150 is through to the lower surface 110b of substrate 110 from the upper surface 110u of substrate 110, and expose upper surface 150u and lower surface 150b respectively from the upper surface 110u of substrate 110 and lower surface 110b, wherein namely the first conductive layer 140 is electrically connected the upper surface 150u of the first conductive pole 150 by the first perforate 130a1.In addition, the material of the first conductive pole 150 comprises copper or copper alloy, and it can be such as that electroplating technology is formed.
Second conductive pole 160 is through to the lower surface 110b of substrate 110 from the upper surface 110u of substrate 110.First protective layer 130 has more at least one 3rd perforate 130a3, and the 3rd perforate 130a3 exposes the upper surface 160u of the second conductive pole 160, and the first conductive layer 140 can be made to be electrically connected the second conductive pole 160 by the 3rd perforate 130a3.
The lower surface 110b of the second protective layer 170 covered substrate 110 and have at least one 4th perforate 170a1 and at least one 5th perforate 170a2, wherein the 4th perforate 170a1 exposes the first conductive pole 150, and the 5th perforate 170a2 exposes the second conductive pole 160.
Second conductive layer 180 is such as routing layer, and it comprises at least one connection pad and at least one cabling.Second conductive layer 180 is electrically connected the first conductive pole 150 by the 4th perforate 170a1, and is electrically connected the second conductive pole 160 by the 5th perforate 170a2.In addition, the material of the second conductive layer 180 and formation method, similar in appearance to the first conductive layer 140, are held this and are repeated no more.
Please refer to Figure 1B, it illustrates the vertical view (not illustrating the first protective layer and the first conductive layer) of the semiconductor package part of Figure 1A.First conductive pole 150 is approximately 50 microns with the spacing H1 of chip 120, maybe can be less than 50 microns.When the first conductive pole 150 is more away from chip 120, then spacing H1 is larger and the size of semiconductor package part 100 is larger.
In the present embodiment, the position due to the first conductive pole 150 is toward inside contracting and exposing from perforation 110a, therefore can shorten spacing H1, and then reduces the size of semiconductor package part 100 or increase the row of conductive pole.With regard to structure, the first conductive pole 150 exposes a medial surface 150s from perforation 110a, and it aligns haply with the medial surface 110s1 of perforation 110a, makes the spacing between the medial surface 150s of the first conductive pole 150 and medial surface 110s1 of perforation 110a be zero.In addition, compared to the second conductive pole 160, because the first conductive pole 150 passes through cutting in manufacture craft, therefore its outer diameter D 1 is less.
First conductive pole 150 to the second conductive pole 160 is close to perforation 110a.In the present embodiment, the first conductive pole 150 is conductive poles of inner side in substrate 110, and the second conductive pole 160 is outermost conductive poles in substrate 110, makes several first conductive poles 150 form two row's ring shaped conductive posts with several second conductive pole 160.In another embodiment, between the first conductive pole 150 and the second conductive pole 160, other conductive pole can be formed with, make the first conductive pole 150, second conductive pole 160 form three with other conductive pole and arrange above conductive pole.
In the present embodiment, several first conductive pole 150 is around chip 120.First conductive pole 150 is optionally electrically connected at an earth terminal, to provide electromagnetic interference shield function.
Please refer to Fig. 2, it illustrates the vertical view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 200 comprises substrate 110, chip 120, first protective layer 130, first conductive layer 140 (not illustrating), single first conductive pole 250, at least one second conductive pole 160, second protective layer 170 (not illustrating) and the second conductive layer 180 (not illustrating).With the semiconductor package part 100 of Figure 1B unlike, first conductive pole 250 of the present embodiment is a closed ring conductive pole, and it so can promote better heat sinking function around chip 120.In another embodiment, the first conductive pole 250 can be electrically connected an earth terminal, to provide electromagnetic interference shield function.
Please refer to Fig. 3, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 300 comprises substrate 110, chip 120, first protective layer 130, first conductive layer 140, at least one first conductive pole 150, at least one second conductive pole 160, second protective layer 170, second conductive layer 180 and the 3rd conductive layer 390.
In the present embodiment, the 3rd conductive layer 390 is formed on the lower surface 150b of lower surface 110b, chip 120 non-active 120b of substrate 110, the first conductive pole 150.In one embodiment, the 3rd conductive layer 390 is heat-conducting layers, and the heat of chip 120 is conducted to outside semiconductor package part 300 rapidly by the 3rd conductive layer 390.3rd conductive layer 390 can by be such as copper, aluminium or the good metal of thermal conductivity make.In addition, the 3rd conductive layer 390 is complete Rotating fields without pierced pattern, and it covers whole non-active 120b of chip 120, and provides a large area of dissipation, and then makes the heat of chip 120 conduct to the external world rapidly.
In another embodiment, the 3rd conductive layer 390 can be electrically connected an earth terminal.Be the complete Rotating fields without pierced pattern due to the 3rd conductive layer 390 and cover whole non-active 120b of chip 120, therefore an excellent electromagnetic interference shield effect can be provided.
The lower surface 110b of the second protective layer 170 covered substrate 110 and the 3rd conductive layer 390.Second protective layer 170 has at least one 6th perforate 170a3, and wherein the 6th perforate 170a3 exposes the 3rd conductive layer 390, makes the second conductive layer 180 be electrically connected the 3rd conductive layer 390 by the 6th perforate 170a3.
In another embodiment, first conductive pole 150 of Fig. 3 also can replace with first conductive pole 250 of Fig. 2.
Please refer to Fig. 4 A to 4M, it illustrates the process drawing of the semiconductor package part 100 of Figure 1A.
As shown in Figure 4 A, substrate 110 is provided.Substrate 110 has relative upper surface 110u and lower surface 110b.
As shown in Figure 4 B, can adopt is such as patterning techniques, forms at least one first perforation 150a and at least one second perforation 160a is through to lower surface 110b from the upper surface 110u of substrate 110.Above-mentioned patterning techniques is such as photoetching process (photolithography), chemical etching (chemical etching), laser drill (laser drilling) or machine drilling (mechanical drilling).
As shown in Figure 4 C, can adopt is such as material formation technology, forms electric conducting material in the first perforation 150a and the second perforation 160a to form the first conductive pole 150 ' and the second conductive pole 160.Wherein, electric conducting material is such as copper, its alloy or other suitable conductive material.The outer diameter D 1 ' of the first conductive pole 150 ', it equals the outer diameter D 2 of the second conductive pole 160 haply.It is such as that chemical gaseous phase Shen is long-pending, electroless plating method (electroless plating), metallide (electrolytic plating) that material forms technology.
Although figure does not illustrate, connection pad or surface-treated layer (surface finish) so also can be formed on the upper surface 150u of the first conductive pole 150 ' and the upper surface 160u of the second conductive pole 160.
As shown in Figure 4 D, can adopt is such as above-mentioned patterning techniques, forms at least consistent hole 110a and is through to lower surface 110b from the upper surface 110u of substrate 110.Because perforation 110a to remove the portion of material of the first conductive pole 150 ' through the first conductive pole 150 ', therefore the outer diameter D 1 ' of the first conductive pole 150 ' is reduced into D1.
When the outer diameter D 3 of perforation 110a is constant, when the first conductive pole 150 ' is more close to perforation 110a, then the outer diameter D 1 of the first conductive pole 150 after cutting is less; Thus, the size of semiconductor package part 100 is less, but the electrical quality of the first conductive pole 150 is deteriorated.In one embodiment, the outer diameter D 1 of the first conductive pole 150 after cutting is approximately the half of the outer diameter D 1 ' of the first conductive pole 150 ' before cutting, so can obtain and meet the undersized semiconductor package part 100 of expection and the excellent electrical quality of the first conductive pole 150.
As shown in Figure 4 E, chip 120 is inside buried in perforation 110a.In the present embodiment, the substrate 110 of Fig. 4 D first can be set on stickup support plate 10, and then chip 120 is pasted on stickup support plate 10, with the relative position of fixed chip 120 with substrate 110 via perforation 110a.Chip 120 has relative active surface 120u and non-active 120b, and its chips 120 is located at non-active 120b and is pasted on support plate 10.
As illustrated in figure 4f; being such as coating technique; form the space between the lateral surface 120s of the space of the first protective layer material 130 ' between the lateral surface 120s and the medial surface 110s1 (not illustrating) of perforation 110a of chip 120 and the chip 120 and medial surface 150s of the first conductive pole 150, and the upper surface 150u of the active surface 120u of the upper surface 110u of covered substrate 110, chip 120, the first conductive pole 150 and upper surface 160u of the second conductive pole 160.Above-mentioned coating technique is such as printing (printing), spin coating (spinning) or spraying (spraying).
As shown in Figure 4 G, being such as that above-mentioned material removes technology, form at least one first perforate 130a1, at least one second perforate 130a2 and at least one 3rd perforate 130a3, wherein the first perforate 130a1 exposes the upper surface 150u of the first conductive pole 150, the connection pad 121 of the second perforate 130a2 exposed chip 120, and the 3rd perforate 130a3 exposes the upper surface 160u of the second conductive pole 160.
As shown at figure 4h, to be such as above-mentioned material formation technology, form the first conductive layer 140, wherein the first conductive layer 140u is electrically connected at the first conductive pole 150 by the first perforate 130a1, is electrically connected at the connection pad 121 of chip 120 and is electrically connected at the second conductive pole 160 by the 3rd perforate 131 by the second perforate 130a2.
As shown in fig. 41, remove and paste support plate 10, to expose the lower surface 160b of lower surface 110b, non-active the 120b of chip 120 of substrate 110, the lower surface 150b of the first conductive pole 150 and the second conductive pole 160.
As shown in fig. 4j, to be such as above-mentioned coating technique, form the lower surface 160b of the lower surface 110b of the second protective layer material 170 ' covered substrate 110, non-active 120b of chip 120, the lower surface 150b of the first conductive pole 150 and the second conductive pole 160.
As shown in Figure 4 K; to be such as above-mentioned patterning techniques; form at least one 4th perforate 170a1 and at least one 5th perforate 170a2 in the second protective layer material 170 '; wherein the 4th perforate 170a1 exposes the lower surface 150b of the first conductive pole 150, and the 5th perforate 170a2 exposes the lower surface 160b of the second conductive pole 160.
As illustrated in fig. 4l, to be such as above-mentioned material formation technology, form the second conductive layer 180, wherein the second conductive layer 180 is electrically connected at the first conductive pole 150 by the first perforate 130a1, is electrically connected at the active surface 120u of chip 120 and is electrically connected at the second conductive pole 160 by the 3rd perforate 131 by the second perforate 130a2.
As shown in fig. 4m, with such as cutter or laser, at least all cut P1 through the first protective layer 130, substrate 110 and the second protective layer 170, to form the semiconductor package part 100 shown at least one Figure 1A in formation.After cutting, the first protective layer 130, substrate 110 and the second protective layer 170 form lateral surface 130s, 110s2 and 170s respectively, and wherein lateral surface 130s, 110s2 and 170s align haply, as flushed.
In the manufacture process of the semiconductor package part 200 of Fig. 2, the first perforation 150a is closed ring, so makes the first conductive pole 250 of follow-up formation in closed ring.All the other steps of semiconductor package part 200, similar in appearance to the corresponding step of semiconductor package part 100, are held this and are repeated no more.
Please refer to Fig. 5 A to 5B, it illustrates the process drawing of the semiconductor package part 300 of Fig. 3.
As shown in Figure 5A, remove after pasting support plate 10, to be such as material formation technology, form the lower surface 130b that the 3rd conductive layer 390 covers non-active 120b of chip 120, the lower surface 150b of the first conductive pole 150 and the first protective layer 130.
As shown in Figure 5 B; above-mentioned coating technique and patterning techniques can be adopted; form the lower surface 110b of the second protective layer 170 covered substrate 110, the lower surface 160b of the second conductive pole 160 and the 3rd conductive layer 390; wherein the second protective layer 170 has at least one 5th perforate 170a2 and at least one 6th perforate 170a3; wherein the 5th perforate 170a2 exposes the lower surface 160b of the second conductive pole 160, and the 6th perforate 170a3 exposes the 3rd conductive layer 390.In the present embodiment, the first conductive pole 150 is electrically connected at an external circuit elements by the 3rd conductive layer 390 and the 6th perforate 170a3, such as, be circuit board, chip or semiconductor package part.
All the other manufacturing steps of the semiconductor package part 300 of Fig. 3, similar in appearance to the corresponding step of semiconductor package part 100, hold this and repeat no more.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (12)
1. a semiconductor package part, comprising:
One substrate, have a relative upper surface and a lower surface and a perforation, this perforation is through to this lower surface from this upper surface;
One first conductive pole, is through to this lower surface from this upper surface, and exposes from the medial surface of this perforation; And
One chip, inside buries in this perforation.
2. semiconductor package part as claimed in claim 1, is characterized in that, more comprise:
One first protective layer, is formed between the lateral surface of this chip and this medial surface of this perforation.
3. semiconductor package part as claimed in claim 2, it is characterized in that, this chip has an active surface, and this first protective layer covers this upper surface of this substrate and has one first perforate and one second perforate, wherein the upper surface of this first conductive pole is exposed in this first perforate, and this active surface of this chip is exposed in this second perforate; This semiconductor package part more comprises:
One first conductive layer, is electrically connected this first conductive pole and this chip by this first perforate and this second perforate.
4. semiconductor package part as claimed in claim 3, is characterized in that, more comprise:
One second conductive pole, from this upper surface of this substrate be through to this substrate this lower surface and than this first conductive pole away from this perforation;
Wherein, this first protective layer has more one the 3rd perforate, and the upper surface of this second conductive pole is exposed in the 3rd perforate, and this first conductive layer is electrically connected this second conductive pole by the 3rd perforate.
5. semiconductor package part as claimed in claim 1, is characterized in that, more comprise:
One second protective layer, covers this lower surface of this substrate, and has one the 4th perforate, and the lower surface of this first conductive pole is exposed in the 4th perforate;
Wherein, this semiconductor package part more comprises one second conductive layer, and this second conductive layer is electrically connected this first conductive pole by the 4th perforate.
6. semiconductor package part as claimed in claim 5, is characterized in that, more comprise:
One second conductive pole, from this upper surface of this substrate be through to this substrate this lower surface and than this first conductive pole away from this perforation;
Wherein, this second protective layer has more one the 5th perforate, and the lower surface of this second conductive pole is exposed in the 5th perforate, and this second conductive layer is electrically connected this second conductive pole by the 5th perforate.
7. semiconductor package part as claimed in claim 1, it is characterized in that, this first conductive pole has a lower surface, and this lower surface of this first conductive pole exposes from this lower surface of this substrate, and this chip has one non-active, and this semiconductor package part more comprises:
One the 3rd conductive layer, be formed at this non-active of this chip with this lower surface of this first conductive pole on and be electrically connected this lower surface of this first conductive pole.
8. semiconductor package part as claimed in claim 7, is characterized in that, more comprise:
One second protective layer, cover this lower surface and the 3rd conductive layer of this substrate, and have one the 6th perforate, the 3rd conductive layer is exposed in the 6th perforate; This semiconductor package part more comprises:
One second conductive layer, is electrically connected the 3rd conductive layer by the 6th perforate.
9. semiconductor package part as claimed in claim 1, it is characterized in that, this first conductive pole is a closed ring conductive pole, and this closed ring conductive pole is around this chip.
10. a manufacture method for semiconductor package part, comprising:
There is provided a substrate, this substrate has a relative upper surface and a lower surface;
Form one first conductive pole and be through to this lower surface from this upper surface of this substrate;
Form a perforation and be through to this lower surface from this upper surface of this substrate, this through hole, through a part for this first conductive pole, makes this first conductive pole expose from a medial surface of this perforation; And
Inside bury a chip in this perforation.
11. manufacture methods as claimed in claim 10, is characterized in that, more comprise:
Form one first protective layer between the lateral surface and this medial surface of this perforation of this chip.
12. manufacture methods as claimed in claim 11, it is characterized in that, this chip has an active surface; Comprise in the step forming this first protective layer:
Form the upper surface that one first protective layer material covers this substrate; And
Form one first perforate and one second perforate in this first protective layer material, wherein the upper surface of this first conductive pole is exposed in this first perforate, and this active surface of this chip is exposed in this second perforate;
This manufacture method more comprises:
Form one first conductive layer, wherein this first conductive layer is electrically connected this first conductive pole and this chip by this first perforate and this second perforate.
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