CN104576537B - A kind of preparation method of semiconductor devices - Google Patents
A kind of preparation method of semiconductor devices Download PDFInfo
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- CN104576537B CN104576537B CN201310492653.1A CN201310492653A CN104576537B CN 104576537 B CN104576537 B CN 104576537B CN 201310492653 A CN201310492653 A CN 201310492653A CN 104576537 B CN104576537 B CN 104576537B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 121
- 229920005591 polysilicon Polymers 0.000 claims abstract description 110
- 238000000034 method Methods 0.000 claims abstract description 40
- 230000008569 process Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 36
- 238000002955 isolation Methods 0.000 claims description 29
- 150000002500 ions Chemical class 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 claims description 4
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 3
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 claims description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- 238000007667 floating Methods 0.000 abstract description 48
- 230000015654 memory Effects 0.000 abstract description 13
- 230000008878 coupling Effects 0.000 abstract description 5
- 238000010168 coupling process Methods 0.000 abstract description 5
- 238000005859 coupling reaction Methods 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 4
- 238000005498 polishing Methods 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000012530 fluid Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 150000001768 cations Chemical class 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- -1 P ion Chemical class 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Inorganic materials [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 description 1
- CSSYLTMKCUORDA-UHFFFAOYSA-N barium(2+);oxygen(2-) Chemical compound [O-2].[Ba+2] CSSYLTMKCUORDA-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- RGZQGGVFIISIHZ-UHFFFAOYSA-N strontium titanium Chemical compound [Ti].[Sr] RGZQGGVFIISIHZ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of preparation method of semiconductor devices, when n-type doping is carried out to polysilicon layer, while being adulterated to floating grid and logic region, that is, the region adulterated is the whole polysilicon layer in addition to select gate regions.Compared with only carrying out n-type doping to floating grid with prior art, the region of polysilicon layer n-type doping is greatly increased, and this greatly reduces the residual polycrystalline silicon after planarization process is carried out to it, is effectively improved CMP uniformity.Simultaneously in the case where residual polycrystalline silicon is considerably less, deliberately it need not be removed, so avoid the loss of floating gate polysilicon, and then cause the problem of floating grid is short-circuited and caused control gate to decline the coupling efficiency of raceway groove during avoiding follow-up flash memories use to greatest extent so that the generation for the problem of speed of write-in and the erasing of flash memories is slack-off.
Description
Technical field
The invention belongs to the manufacture field of semiconductor devices, it is related to a kind of preparation method of semiconductor devices.
Background technology
Flash memories due to can repeatedly carry out the deposit of data, read, the action such as erase, and the data of deposit exist
The advantage that will not be also disappeared after power-off, so turning into PC and a kind of widely used storage element of electronic equipment
Part.
Typical flash memory components are stacked gate structure, and floating grid and control are made with the polysilicon of doping
Grid.Floating grid is in floating state, is attached thereto without any circuit, with inter-gate dielectric between floating grid and control gate
Layer is separated by, and floating grid is separated by with substrate with tunnel dielectric layer；And control gate is then connected with wordline.
In the preparation process of floating grid, generally using chemical mechanical polishing method（CMP, Chemical Mechanical
Polishing）Planarization process is carried out to floating gate polysilicon layer.But to enter after being formed due to floating gate polysilicon layer
Row ion doping processing, therefore, for formation polysilicon layer be first carry out planarization process or first carry out doping treatment be
The problem of one worth discussion.Due to the limitation of existing CMP technology, the precision to CMP is difficult control, it is difficult to ensure that
The uniformity of thickness after polysilicon layer planarization process, sometimes the thickness difference of the polysilicon layer after planarization process even can exceed
10nm.Ion doping is carried out to polysilicon layer in such a situa-tion, ion doping at thicker polysilicon layer can be caused inadequate,
And ion may go through polysilicon layer into Semiconductor substrate at relatively thin polysilicon layer, this will largely effect on the polysilicon
The uniformity of layer doping, and then the performance of floating grid and whole device is produced serious influence.If to many before CMP
Crystal silicon layer carries out ion doping, and under conditions of thermal diffusion, the ratio that polysilicon layer will adulterate is more uniform, is also not in ion
Enter the phenomenon of Semiconductor substrate through polysilicon layer.Therefore, it is typically first to many in the preparation process of existing floating grid
Crystal silicon layer carries out ion doping, then carries out planarization process to it.
The preparation process of existing floating grid is as shown in Fig. 1 a to Fig. 1 f.As shown in Figure 1a there is provided semi-conductive substrate 10,
Isolation structure 11 is formed in Semiconductor substrate 10 to isolate active area 12, the surface of isolation structure 11 is higher than Semiconductor substrate
10.As shown in Figure 1 b, tunnel oxide 13 is formed on active area 12.As illustrated in figure 1 c, in tunnel oxide 13 and isolation junction
Intrinsically polysilicon layer 14 is formed on structure 11.As shown in Figure 1 d, one layer is formed in intrinsically polysilicon layer 14 has hatch frame
Mask layer 16, the aperture position of mask layer 16 corresponds to the position of floating grid 17, then carries out n-type doping to floating grid 17.
Fig. 1 e be corresponding to Fig. 1 d top view, from Fig. 1 e understand, mask layer 16 cover including select grid 18 including it is whole
Polysilicon layer, only stays the position for being opened on floating grid 17, and this make it that the region of n-type doping is only floating grid 17.Such as Fig. 1 f
It is shown, mask layer 16 is removed, and planarization process is carried out to the polysilicon layer 15 of the n-type doping, form floating grid 17.
Because polysilicon can change in doping after-potential, and CMP is an electrochemical polish and physics polishing phase
With reference to polishing method, the change of polysilicon potential inherently produces influence, the removal of polysilicon after doping to its polishing speed
Speed and the removal speed of undoped polycrystalline silicon are significantly different.The change of polysilicon removal rate and polishing fluid and polycrystalline after doping
Silicon doped chemical type is relevant, but will all cause that CMP uniformity receives obvious influence anyway.And existing floating
In the preparation process of grid, the region of doping is very small, only floating grid, it is larger inherently cause undoped with region its
There is substantial amounts of residual polycrystalline silicon during CMP, the polysilicon of residual can be led during follow-up flash memories use
Floating grid is caused to be short-circuited.And if to remove the polysilicon of residual and carry out further CMP to whole polysilicon layer, will
Floating gate polysilicon can be caused to be lost.The loss of floating gate polysilicon can cause control gate to decline the coupling efficiency of raceway groove,
So that the speed of write-in and the erasing of flash memories is slack-off.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of preparation side of semiconductor devices
CMP uniformities are poor when in method, the preparation process for solving existing floating grid to polysilicon layer progress planarization process, make
Obtain polysilicon layer and there is substantial amounts of residual polycrystalline silicon undoped with region, and then can be led during follow-up flash memories use
Cause the problem of floating grid is short-circuited or enter traveling one undoped with the polysilicon that region is remained to remove polysilicon layer
The CMP of step, causes floating gate polysilicon to be lost, and then causes control gate to decline the coupling efficiency of raceway groove, so that flash memory
Memory write and wipe digit rate it is slack-off the problem of.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of semiconductor devices, described
Method at least includes：
1) isolation structure being formed with semi-conductive substrate, the Semiconductor substrate for isolating active area is provided, every
Surface from structure is higher than Semiconductor substrate；
2) tunnel oxide is formed on the active area of the Semiconductor substrate；
3) intrinsically polysilicon layer is formed on the tunnel oxide and isolation structure；
4) one layer of mask layer of the default corresponding position formation of selection grid in the intrinsically polysilicon layer, then to sudden and violent
The intrinsically polysilicon layer of dew carries out n-type doping；
5) mask layer is removed, and planarization process is carried out to the polysilicon layer of the n-type doping.
Preferably, the step of also including carrying out p-type doping to the corresponding region of selection grid is formed after floating grid.
Alternatively, the ion for n-type doping being carried out to the intrinsically polysilicon layer is the ion of V major elements.It is more excellent
Selection of land, the ion that n-type doping is carried out to the intrinsically polysilicon layer is P ion or As ions.
Preferably, to the intrinsically polysilicon layer（24）Carry out n-type doping when Implantation Energy between 1KeV to 30KeV it
Between.
Preferably, the doping concentration for n-type doping being carried out to the intrinsically polysilicon layer is 1.0 × 1017~5.0 ×
1020atom/cm2。
Alternatively, the isolation structure formed in the Semiconductor substrate is isolated or the isolation of selective oxidation silicon for shallow trench.
Preferably, planarization process is carried out to the polysilicon layer of the n-type doping using chemical mechanical polishing method.
Alternatively, the thickness after the polysilicon layer planarization process of the n-type doping is 100~250nm, is more highly preferred to
Thickness after ground, the polysilicon layer planarization process of the n-type doping is 60~100nm.
Alternatively, the material of the tunnel oxide is silica, silicon oxide/silicon nitride/silicon oxide or hafnium oxide, oxidation
Hafnium silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, oxidation
At least one in strontium titanium, aluminum oxide.
As described above, the preparation method of the semiconductor devices of the present invention, has the advantages that：To many in the present invention
When crystal silicon layer carries out n-type doping, while adulterated to floating grid and logic region, that is, the region adulterated be except
Whole polysilicon layer beyond select gate regions, compared with this only carries out n-type doping with prior art to floating grid, significantly
Add the region of polysilicon layer n-type doping.On the premise of carrying out n-type doping in floating grid, corresponding polishing is used
Liquid can make it that the removal speed of n-type doping polysilicon is significantly greater than the removal speed of undoped polycrystalline silicon, in such condition
Lower increase polysilicon layer carries out the region of n-type doping, when CMP is carried out to it, is ensureing that floating gate polysilicon layer must
While wanting thickness, it can greatly reduce and the residual polycrystalline silicon after CMP is carried out to it, be effectively improved CMP uniformity, enter
And cause the generation for the problem of floating grid is short-circuited during avoiding follow-up flash memories use to greatest extent.
Further, since to doped polysilicon layer carry out CMP after residual polycrystalline silicon it is considerably less, this just need not as prior art,
Further CMP is carried out to whole polysilicon layer in order to remove the polysilicon of residual, so avoids to want to having reached
The CMP of the floating gate polysilicon layer progress of thickness again is sought, the loss of floating gate polysilicon is effectively reduced, and then
Avoid caused control gate therefrom to decline the coupling efficiency of raceway groove so that the speed of write-in and the erasing of flash memories becomes
The generation of slow the problem of.
Brief description of the drawings
Fig. 1 a-1f are shown as structural representation of the preparation method in each step of semiconductor devices in the prior art.
Fig. 2 is shown as the flow chart of the preparation method of the semiconductor devices of the present invention.
Fig. 3 a-3f are shown as structural representation of the preparation method of the semiconductor devices of the present invention in each step.
Component label instructions
10,20 Semiconductor substrates
11,21 isolation structures
12,22 active areas
13,23 tunnel oxides
14,24 intrinsically polysilicon layer
d1The thickness of intrinsically polysilicon layer
d2The thickness of tunnel oxide
d3Fleet plough groove isolation structure is higher by the height of Semiconductor substrate
15,25 n-type doping polysilicon layers
16,26 mask layers
17,27 floating grids
18,28 selection grids
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to figure and refer to Fig. 2 to Fig. 3 f.It should be noted that the diagram provided in the present embodiment is only with signal side
Formula illustrates the basic conception of the present invention, though only display is with relevant component in the present invention rather than according to during actual implement in schema
Component count, shape and size are drawn, and kenel, quantity and the ratio of each component can change for a kind of random during its actual implementation
Become, and its assembly layout kenel may also be increasingly complex.
Such as Fig. 2 to Fig. 3 f, the present invention provides a kind of preparation method of semiconductor devices, and methods described at least includes：
1）The isolation junction being formed with semi-conductive substrate 20, the Semiconductor substrate 20 for isolating active area 22 is provided
Structure 21, the surface of isolation structure 21 is higher than Semiconductor substrate 20；
2）Tunnel oxide 23 is formed on the active area 22 of the Semiconductor substrate 20；
3）Intrinsically polysilicon layer 24 is formed on the tunnel oxide 23 and isolation structure 21；
4）The corresponding position of default selection grid 28 forms one layer of mask layer 26 in the intrinsically polysilicon layer 24, so
N-type doping is carried out to the intrinsically polysilicon layer 24 afterwards；
5）Mask layer 26 is removed, and planarization process is carried out to the polysilicon layer 25 of the n-type doping.
In step 1）In, referring to Fig. 2 S1 steps and Fig. 3 a, there is provided semi-conductive substrate 20, the Semiconductor substrate
The isolation structure 21 for isolating active area 22 is formed with 20, the surface of isolation structure 21 is higher than Semiconductor substrate 20.
In the present embodiment, the material of Semiconductor substrate 20 can be silicon, SiGe, silicon-on-insulator (silicon
Oninsulator, SOI), germanium on insulator SiClx (silicon germanium on insulator, SGOI) or insulator
Upper germanium (germanium on insulator, GOI).
The isolation structure 21 formed in Semiconductor substrate 20 is isolated for shallow trench（STI, Shallow Trench
Isolation）Or selective oxidation silicon（LOCOS, Locally Oxidized Silicon）Isolation structure, in the present embodiment
In, the isolation structure 21 is isolated for shallow trench, and its material at least includes silica.In the prior art, the shallow trench of formation every
Surface from structure is usually above the surface of Semiconductor substrate.
It should be noted that the formation process of fleet plough groove isolation structure can be skilled in the art realises that it is any one
Process is planted, for example：Etch isolation channel arranged in parallel being formed with the Semiconductor substrate of hard mask, then to it is described every
Filled from groove by oxide and planarization process is isolated with forming shallow trench, wherein, the shallow trench insulation surfaces and institute
State hard mask surface in Semiconductor substrate at grade, the hard mask includes being sequentially formed on the active area 22
Silica and silicon nitride.Surface using the groove isolation construction of described or similar shallow ditch groove separation process formation is usual
Higher than the surface of Semiconductor substrate.
In step 2）In, Fig. 2 S2 steps and Fig. 3 b is referred to, is formed on the active area 22 of the Semiconductor substrate 20
Tunnel oxide 23.The material of tunnel oxide 23 can be silica or silicon oxide/silicon nitride/silicon oxide, can also be oxidation
Hafnium, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide
The high-ks such as titanium, strontium oxide strontia titanium, aluminum oxide（High K）Material.The technique for being conventionally formed tunnel oxide 23 is thermal oxidation method,
In high temperature environments, Semiconductor substrate 20 is exposed in an oxygen-containing environment, the technique is generally in boiler tube（It is not shown）It is middle to realize,
The thickness for the tunnel oxide 23 being usually formed is all right in tens Izods.In the implementation case, in the Semiconductor substrate 20 of offer
On with situ steam produce oxidizing process or furnace oxidation method formation tunnel oxide 23.
It should be noted that forming concretely comprising the following steps for the tunnel oxide 23：Hard mask layer is first removed to expose
The surface of active area 22 is stated, wherein, using wet etching, utilize H3PO4Solution removes silicon nitride, and HF solution removes silicon；Then
Tunnel oxide 23 is prepared on the active area 22.
In step 3）In, refer to Fig. 2 S3 steps and Fig. 3 c, the shape on the tunnel oxide 23 and isolation structure 21
Into intrinsically polysilicon layer 24.
The material of intrinsically polysilicon layer 24 can be polysilicon or polycide etc., and its method formed can be low
Pressure chemical vapor deposition method（LPCVD, Low Pressure Chemical Vapor Depostion）.In the present embodiment, use
Low Pressure Chemical Vapor Deposition, using silicomethane as gas source deposition intrinsic polysilicon layer 24.
It should be noted that the intrinsically polysilicon layer 24 and the thickness sum of tunnel oxide 23 that are formed can be more than or
Person is higher by less than fleet plough groove isolation structure in the height on the surface of Semiconductor substrate 20, the present embodiment, it is preferable that what is formed is intrinsic
The thickness sum of polysilicon layer 24 and tunnel oxide 23（d1+d2）The table of Semiconductor substrate 20 is higher by more than fleet plough groove isolation structure
The height d in face3。
In step 4）In, Fig. 2 S4 steps and Fig. 3 d and Fig. 3 e is referred to, it is default in the intrinsically polysilicon layer 24
Select the corresponding position of grid 28 to form one layer of mask layer 26, n-type doping then is carried out to exposed intrinsically polysilicon layer 24.
Specifically, the mask layer 26 formed on the corresponding position of selection grid 28 can be photoresist or hard mask, this
It is preferably photoresist in embodiment, described Other substrate materials include but is not limited to silicon nitride.
It is barrier layer with mask layer 26 in the present embodiment, using ion implantation technology to the intrinsic polysilicon that is formed
Layer 24 carries out N-type ion doping.During the ion of the n-type doping is the ion of V major elements, the present embodiment, preferably N
The ion of type doping is P ion or As ions, and doping concentration is 1.0 × 1017~5.0 × 1020atom/cm2, and carry out N-type mix
Implantation Energy when miscellaneous is between 1KeV to 30KeV.
It should be noted that Fig. 3 e are the corresponding top views of Fig. 3 d, to the intrinsic polysilicon it can be seen from Fig. 3 e
When layer 24 carries out n-type doping, mask layer 26 only is formed on the corresponding position of selection grid, this guarantees to described
Levy polysilicon layer 24 carry out n-type doping region and meanwhile including the domain of floating grid polar region 27 and logic region, i.e. doped region be except
Whole polysilicon layer beyond selection grid 28 region.The corresponding region of selection grid 28 of n-type doping is not carried out follow-up
Need to carry out p-type doping in the preparation technology for selecting grid.
In step 5）In, Fig. 2 S5 steps and Fig. 3 f is referred to, mask layer 26 is removed, and to the polycrystalline of the n-type doping
Silicon layer 25 carries out planarization process.
In the present embodiment, mask layer 26 is removed using the method for wet etching.
In the present embodiment, planarization process is carried out to the polysilicon layer 25 of n-type doping using chemical mechanical polishing method.Carry out
Chemically-mechanicapolish polishing used polishing fluid and specific glossing can use in prior art, the present embodiment, provide
A kind of embodiment, uses silica for abrasive grains, and added with related chemical addition agent.Due in polysilicon
Doped with n-type doping ion, such as P ion, there is unnecessary electronics in the surface of polysilicon, when being chemically-mechanicapolish polished, such as
Contain the cation meeting in the excess electron and polishing fluid in stronger cation, polysilicon in the additive of fruit polishing fluid addition
Attract each other, cause polishing speed to increase.Under this environmental condition, the removal speed of the polysilicon layer of n-type doping is substantially big
In the removal speed of undoped polysilicon layer.It is except selection grid due to carrying out the region of n-type doping to intrinsically polysilicon layer 24
Whole polysilicon layer beyond the region of pole 28, this allows for the polycrystalline that whole polysilicon layer most areas is n-type doping
Silicon 25, so when CMP is carried out to it, while floating gate polysilicon layer necessity thickness is ensured, can subtract significantly
It is few that the residual polycrystalline silicon after CMP is carried out to it, it is effectively improved CMP uniformity.Further, since entering to doped polysilicon layer
Residual polycrystalline silicon after row planarization process is considerably less, and this just need not be as prior art, in order to remove the polycrystalline of residual
Silicon and further CMP is carried out to whole polysilicon layer, so avoid many to the floating grid for having reached requirement thickness
Crystal silicon layer carries out CMP again, effectively reduces the loss of floating gate polysilicon.
Specifically, the thickness after the planarization process of polysilicon layer 25 of the n-type doping is 100~250nm, it is more highly preferred to
Thickness after ground, the planarization process of polysilicon layer 25 of the n-type doping is 60~100nm.
In summary, in the present invention when n-type doping is carried out to polysilicon layer, while to floating grid and logic area
Domain is adulterated, that is, the region adulterated is whole polysilicon layer in addition to select gate regions, this with prior art only
N-type doping is carried out to floating grid to compare, and considerably increases the region of polysilicon layer n-type doping.Due to entering in floating grid
On the premise of row n-type doping, use the corresponding polishing fluid can be so that the removal speed of n-type doping polysilicon is not mixed significantly greater than
The removal speed of miscellaneous polysilicon.Increase polysilicon layer carries out the region of n-type doping in such a situa-tion, and CMP is being carried out to it
When, while floating gate polysilicon layer necessity thickness is ensured, it can greatly reduce and the polysilicon after CMP is carried out to it
Residual, is effectively improved CMP uniformity, and then leads during avoiding follow-up flash memories use to greatest extent
Cause the generation for the problem of floating grid is short-circuited.Further, since it is non-that the residual polycrystalline silicon after CMP is carried out to doped polysilicon layer
Often few, this need not just be carried out further as prior art in order to remove the polysilicon of residual to whole polysilicon layer
CMP, so avoid to carry out CMP again to the floating gate polysilicon layer for having reached requirement thickness, effectively
The loss of floating gate polysilicon is reduced, and then avoids caused control gate therefrom the coupling efficiency of raceway groove is declined, made
Flash memories write-in and erasing speed it is slack-off the problem of generation.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of preparation method of semiconductor devices, it is characterised in that comprise the following steps：
1) isolation structure being formed with Semiconductor substrate, the Semiconductor substrate for isolating active area, isolation structure are provided
Upper surface be higher than the Semiconductor substrate；
2) tunnel oxide is formed on the active area of the Semiconductor substrate；
3) intrinsically polysilicon layer is formed on the tunnel oxide and isolation structure；
4) it is only default in the intrinsically polysilicon layer to select to be provided with mask layer on the corresponding region of grid, then to exposed
Remaining intrinsically polysilicon layer carries out n-type doping；
5) mask layer is removed, and planarization process is carried out to the polysilicon layer of the n-type doping.
2. the preparation method of semiconductor devices according to claim 1, it is characterised in that：Step 5) also include to choosing afterwards
Select the step of corresponding region of grid carries out p-type doping.
3. the preparation method of semiconductor devices according to claim 1, it is characterised in that：Step 4) in described intrinsic many
The ion that crystal silicon layer carries out n-type doping is the ion of V major elements.
4. the preparation method of semiconductor devices according to claim 3, it is characterised in that：Step 4) in described intrinsic many
The ion that crystal silicon layer carries out n-type doping is P ion or As ions.
5. the preparation method of semiconductor devices according to claim 1, it is characterised in that：Step 4) in described intrinsic many
The doping concentration that crystal silicon layer carries out n-type doping is 1.0 × 1017~5.0 × 1020atom/cm2；Implantation Energy is arrived between 1KeV
Between 30KeV.
6. the preparation method of semiconductor devices according to claim 1, it is characterised in that：Step 1) described in isolation structure
For shallow trench isolation or the isolation of selective oxidation silicon.
7. the preparation method of semiconductor devices according to claim 1, it is characterised in that：Step 5) in use chemical machinery
Polishing processes carry out planarization process to the polysilicon layer of the n-type doping.
8. the preparation method of semiconductor devices according to claim 1, it is characterised in that：Step 5) described in n-type doping
Polysilicon layer planarization process after thickness be 100~250nm.
9. the preparation method of semiconductor devices according to claim 7, it is characterised in that：Step 5) described in n-type doping
Polysilicon layer planarization process after thickness be 60~100nm.
10. the preparation method of semiconductor devices according to claim 1, it is characterised in that：Step 2) described in tunnelling oxygen
The material for changing layer is silica, silicon oxide/silicon nitride/silicon oxide, hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, oxygen
Change at least one in zirconium, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminum oxide.
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| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| CN101572224A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for smoothening doped polysilicon and method for preparing polysilicon floating gate |
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| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| CN101572224A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for smoothening doped polysilicon and method for preparing polysilicon floating gate |
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