CN104576537A - Preparation method of semiconductor devices - Google Patents
Preparation method of semiconductor devices Download PDFInfo
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- CN104576537A CN104576537A CN201310492653.1A CN201310492653A CN104576537A CN 104576537 A CN104576537 A CN 104576537A CN 201310492653 A CN201310492653 A CN 201310492653A CN 104576537 A CN104576537 A CN 104576537A
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- polysilicon layer
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- oxide
- doping
- semiconductor device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
Abstract
The invention provides a preparation method of semiconductor devices. When N-type doping is performed to a polycrystalline silicon layer, doping is also performed to a floating grid and a logic area, namely, the doped area is the entire polycrystalline silicon layer except a selected grid area. Compared with the prior art that only the floating grid is subjected to N-type doping, the N-type doping area of the polycrystalline silicon layer is greatly enlarged, residual polycrystalline silicon is greatly reduced after planarization, and CMP uniformity is effectively improved; and besides, little residual polycrystalline silicon does not need to be removed deliberately, so that consumption of floating grid polycrystalline silicon is reduced, further, slow writing-in and erasure speed of a flash memory due to lowered coupling efficiency of a control grid to a channel caused by short circuit of a floating grid during the follow-up use of the flash memory is avoided to the hilt.
Description
Technical field
The invention belongs to the manufacture field of semiconductor device, relate to a kind of preparation method of semiconductor device.
Background technology
Flash memories due to have can repeatedly carry out data stored in, read, the action such as to erase, and stored in the data advantage that also can not disappear after a loss of power, so become a kind of memory component that PC and electronic equipment extensively adopt.
Typical flash memory components is stacked gate structure, makes floating grid and control gate with the polysilicon adulterated.Floating grid is in floating state, is attached thereto, is separated by between floating grid and control gate with gate dielectric layer without any circuit, and floating grid and substrate are separated by with tunnel dielectric layer; Control gate is then connected with wordline.
In the preparation process of floating grid, chemical mechanical polishing method (CMP, Chemical MechanicalPolishing) is usually adopted to carry out planarization to floating gate polysilicon layer.But due to floating gate polysilicon layer formed after to carry out ion doping process, therefore, for formed polysilicon layer be first carry out planarization or first carry out doping treatment be one be worth inquire into problem.Due to the restriction of existing CMP technology, be difficult to control to the precision of CMP, the uniformity of thickness after very difficult guarantee polysilicon layer planarization, the thickness difference of the polysilicon layer sometimes after planarization even can more than 10nm.In such a situa-tion ion doping is carried out to polysilicon layer, thicker polysilicon layer place ion doping can be caused inadequate, and thinner polysilicon layer place ion may enter in Semiconductor substrate through polysilicon layer, this will affect the uniformity of this doping polycrystalline silicon layer greatly, and then produces serious influence to the performance of floating grid and whole device.If carried out ion doping to polysilicon layer before CMP, under the condition of thermal diffusion, it is relatively more even that polysilicon layer will adulterate, and also can not there is ion enters Semiconductor substrate phenomenon through polysilicon layer.Therefore, in the preparation process of existing floating grid, normally first ion doping is carried out to polysilicon layer, then planarization is carried out to it.
The preparation process of existing floating grid is as shown in Fig. 1 a to Fig. 1 f.As shown in Figure 1a, provide semi-conductive substrate 10, in Semiconductor substrate 10, form isolation structure 11 to isolate active area 12, the surface of isolation structure 11 is higher than Semiconductor substrate 10.As shown in Figure 1 b, active area 12 forms tunnel oxide 13.As illustrated in figure 1 c, tunnel oxide 13 and isolation structure 11 form intrinsically polysilicon layer 14.As shown in Figure 1 d, intrinsically polysilicon layer 14 forms the mask layer 16 that one deck has hatch frame, mask layer 16 aperture position corresponds to the position of floating grid 17, then carries out N-type doping to floating grid 17.Fig. 1 e is the vertical view corresponding to Fig. 1 d, known from Fig. 1 e, and mask layer 16 covers the whole polysilicon layer comprising and select grid 18, and only stay the position being opened on floating grid 17, this region that N-type is adulterated is only floating grid 17.As shown in Figure 1 f, remove mask layer 16, and planarization is carried out to the polysilicon layer 15 that described N-type is adulterated, form floating grid 17.
Because polysilicon can change in doping after-potential, and CMP is the finishing method that an electrochemical polish and physics polishing combine, the change of polysilicon electromotive force inherently has an impact to its polishing speed, after doping polysilicon remove speed and undoped polycrystalline silicon to remove speed obviously different.After doping, the change of polysilicon removal rate is relevant with polysilicon doping element type with polishing fluid, in any case but all will the uniformity of CMP be made to receive obvious impact.And in the preparation process of existing floating grid, the region of doping is very little, be only floating grid, larger non-doped region inherently makes it in the process of CMP, there is a large amount of residual polycrystalline silicons, causes floating grid to be short-circuited in the process that residual polysilicon can use at follow-up flash memories.And if residual polysilicon to be removed and further CMP is carried out to whole polysilicon layer, floating gate polysilicon loss will be caused.The loss of floating gate polysilicon can cause control gate to decline to the coupling efficiency of raceway groove, thus makes the speed of the write of flash memories and erasing slack-off.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of preparation method of semiconductor device, for solve existing floating grid preparation process in planarization carried out to polysilicon layer time CMP uniformity poor, the non-doped region of polysilicon layer is made to there is a large amount of residual polycrystalline silicons, and then the problem causing floating grid to be short-circuited in the process that can use at follow-up flash memories or carry out further CMP to remove the residual polysilicon of the non-doped region of polysilicon layer, cause floating gate polysilicon loss, and then cause control gate to decline to the coupling efficiency of raceway groove, thus make flash memories write and wipe and to obtain the slack-off problem of digit rate.
For achieving the above object and other relevant objects, the invention provides a kind of preparation method of semiconductor device, described method at least comprises:
1) provide semi-conductive substrate, be formed with the isolation structure for isolating active area in described Semiconductor substrate, the surface of isolation structure is higher than Semiconductor substrate;
2) on the active area of described Semiconductor substrate, tunnel oxide is formed;
3) on described tunnel oxide and isolation structure, intrinsically polysilicon layer is formed;
4) position that the selection grid preset in described intrinsically polysilicon layer is corresponding forms one deck mask layer, then carries out N-type doping to the intrinsically polysilicon layer exposed;
5) remove mask layer, and planarization is carried out to the polysilicon layer that described N-type is adulterated.
Preferably, the step to selecting region corresponding to grid to carry out the doping of P type is also comprised after formation floating grid.
Alternatively, the ion carrying out N-type doping to described intrinsically polysilicon layer is the ion of V major element.More preferably, the ion carrying out N-type doping to described intrinsically polysilicon layer is P ion or As ion.
Preferably, to described intrinsically polysilicon layer (24) carry out N-type doping time Implantation Energy between 1KeV to 30KeV.
Preferably, the doping content of carrying out N-type doping to described intrinsically polysilicon layer is 1.0 × 10
17~ 5.0 × 10
20atom/cm
2.
Alternatively, the isolation structure formed in described Semiconductor substrate be shallow trench isolation from or selective oxidation insulate on Si.
Preferably, chemical mechanical polishing method is adopted to carry out planarization to the polysilicon layer that described N-type is adulterated.
Alternatively, the thickness after the polysilicon layer planarization of described N-type doping is 100 ~ 250nm, and more preferably, the thickness after the polysilicon layer planarization of described N-type doping is 60 ~ 100nm.
Alternatively, the material of described tunnel oxide is at least one in silica, silicon oxide/silicon nitride/silicon oxide or hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide.
As mentioned above, the preparation method of semiconductor device of the present invention, there is following beneficial effect: in the present invention when carrying out N-type doping to polysilicon layer, floating grid and logic region are adulterated simultaneously, the region of namely adulterating is the whole polysilicon layer except select gate regions, this and prior art only carry out compared with N-type adulterates, considerably increasing the region of polysilicon layer N-type doping to floating grid.Due to carry out N-type doping at floating grid prerequisite under, use corresponding polishing fluid can make N-type doped polycrystalline silicon remove that speed is obviously greater than undoped polycrystalline silicon remove speed, increase the region that polysilicon layer carries out N-type doping in such a situa-tion, when carrying out CMP to it, while the necessary thickness of guarantee floating gate polysilicon layer, can greatly reduce and the residual polycrystalline silicon after CMP is carried out to it, effectively improve the uniformity of CMP, and then avoid the generation of the problem causing floating grid to be short-circuited in the process of follow-up flash memories use to greatest extent.In addition, because the residual polycrystalline silicon carried out after CMP doped polysilicon layer is considerably less, this just need not as prior art, in order to remove residual polysilicon, further CMP is carried out to whole polysilicon layer, doing so avoids the CMP carrying out again to the floating gate polysilicon layer reaching required thickness, effectively reduce the loss of floating gate polysilicon, and then avoid the control gate caused therefrom the coupling efficiency of raceway groove is declined, the generation of the problem making the speed of the write of flash memories and erasing slack-off.
Accompanying drawing explanation
Fig. 1 a-1f is shown as the structural representation of preparation method in each step of semiconductor device in prior art.
Fig. 2 is shown as the flow chart of the manufacture method of semiconductor device of the present invention.
Fig. 3 a-3f is shown as the structural representation of preparation method in each step of semiconductor device of the present invention.
Element numbers explanation
10,20 Semiconductor substrate
11,21 isolation structures
12,22 active areas
13,23 tunnel oxides
14,24 intrinsically polysilicon layer
D
1the thickness of intrinsically polysilicon layer
D
2the thickness of tunnel oxide
D
3fleet plough groove isolation structure exceeds the height of Semiconductor substrate
15,25 N-type doped polysilicon layers
16,26 mask layers
17,27 floating grids
18,28 select grid
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to figure and refer to Fig. 2 to Fig. 3 f.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, though only show the assembly relevant with the present invention in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As Fig. 2 to Fig. 3 f, the invention provides a kind of preparation method of semiconductor device, described method at least comprises:
1) provide semi-conductive substrate 20, be formed with the isolation structure 21 for isolating active area 22 in described Semiconductor substrate 20, the surface of isolation structure 21 is higher than Semiconductor substrate 20;
2) on the active area 22 of described Semiconductor substrate 20, tunnel oxide 23 is formed;
3) on described tunnel oxide 23 and isolation structure 21, intrinsically polysilicon layer 24 is formed;
4) position of selection grid 28 correspondence preset in described intrinsically polysilicon layer 24 forms one deck mask layer 26, then carries out N-type doping to described intrinsically polysilicon layer 24;
5) remove mask layer 26, and planarization is carried out to the polysilicon layer 25 that described N-type is adulterated.
In step 1), refer to S1 step and Fig. 3 a of Fig. 2, provide semi-conductive substrate 20, be formed with the isolation structure 21 for isolating active area 22 in described Semiconductor substrate 20, the surface of isolation structure 21 is higher than Semiconductor substrate 20.
In the present embodiment, the material of Semiconductor substrate 20 can be silicon, SiGe, silicon-on-insulator (silicon oninsulator, SOI), germanium on insulator SiClx (silicon germanium on insulator, or germanium on insulator (germanium oninsulator, GOI) SGOI).
The isolation structure 21 formed in Semiconductor substrate 20 is that shallow trench isolation is from (STI, Shallow Trench Isolation) or selective oxidation silicon (LOCOS, Locally Oxidized Silicon) isolation structure, in the present embodiment, described isolation structure 21 be shallow trench isolation from, its material at least comprises silica.In prior art, the surface of the fleet plough groove isolation structure of formation is usually above the surface of Semiconductor substrate.
It should be noted that, the formation process of fleet plough groove isolation structure can be any one process that those skilled in the art understand, such as: in the Semiconductor substrate being formed with hard mask, etch isolation channel arranged in parallel, then described isolation channel is filled by oxide and planarization with formed shallow trench isolation from, wherein, at grade, described hard mask comprises and is formed at silica on described active area 22 and silicon nitride successively hard mask surface in described shallow trench insulation surfaces and described Semiconductor substrate.Adopt the surface of surface usually above Semiconductor substrate of the groove isolation construction of described or similar shallow ditch groove separation process formation.
In step 2) in, refer to S2 step and Fig. 3 b of Fig. 2, the active area 22 of described Semiconductor substrate 20 forms tunnel oxide 23.The material of tunnel oxide 23 can be silica or silicon oxide/silicon nitride/silicon oxide, can also be high-k (high K) materials such as hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide.The technique that tradition forms tunnel oxide 23 is thermal oxidation method, in high temperature environments, expose in an oxygen-containing environment by Semiconductor substrate 20, described technique realizes usually in boiler tube (not shown), and the thickness of the tunnel oxide 23 usually formed is all right at tens Izods.In the implementation case, the Semiconductor substrate 20 provided produces oxidizing process or furnace oxidation method formation tunnel oxide 23 by situ steam.
It should be noted that, the concrete steps forming described tunnel oxide 23 are: first remove hard mask layer to expose surface, described active area 22, wherein, adopt wet etching, utilize H
3pO
4solution removal silicon nitride, HF solution removal silica; Then on described active area 22, prepare tunnel oxide 23.
In step 3), refer to S3 step and Fig. 3 c of Fig. 2, described tunnel oxide 23 and isolation structure 21 form intrinsically polysilicon layer 24.
The material of intrinsically polysilicon layer 24 can be polysilicon or polycide etc., and its method formed can be Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Depostion).In the present embodiment, adopting Low Pressure Chemical Vapor Deposition, take silicomethane as gas source deposition intrinsic polysilicon layer 24.
It should be noted that, the intrinsically polysilicon layer 24 formed and the thickness sum of tunnel oxide 23 can be greater than or less than the height that fleet plough groove isolation structure exceeds Semiconductor substrate 20 surface, in the present embodiment, preferably, the thickness sum (d of the intrinsically polysilicon layer 24 formed and tunnel oxide 23
1+ d
2) be greater than the height d that fleet plough groove isolation structure exceeds Semiconductor substrate 20 surface
3.
In step 4), refer to S4 step and Fig. 3 d and Fig. 3 e of Fig. 2, the position of selection grid 28 correspondence that described intrinsically polysilicon layer 24 is preset forms one deck mask layer 26, then carries out N-type doping to the intrinsically polysilicon layer 24 exposed.
Concrete, can be photoresist or hard mask at the mask layer 26 selecting the position of grid 28 correspondence is formed, be preferably photoresist in the present embodiment, described Other substrate materials includes but not limited to silicon nitride.
In the present embodiment, with mask layer 26 for barrier layer, ion implantation technology is adopted to carry out N-type ion doping to formed intrinsically polysilicon layer 24.The ion of described N-type doping is be the ion of V major element, and in the present embodiment, the ion of preferably N-type doping is P ion or As ion, and doping content is 1.0 × 10
17~ 5.0 × 10
20atom/cm
2, and Implantation Energy when carrying out N-type doping is between 1KeV to 30KeV.
It should be noted that, Fig. 3 e is the vertical view that Fig. 3 d is corresponding, as can be seen from Fig. 3 e, when carrying out N-type doping to described intrinsically polysilicon layer 24, only selecting position corresponding to grid forms mask layer 26, the region that this guarantees described intrinsically polysilicon layer 24 carries out N-type doping comprises territory, floating grid polar region 27 and logic region simultaneously, and namely doped region is the whole polysilicon layer except selecting grid 28 region.The region of not carrying out selection grid 28 correspondence of N-type doping needs to carry out the doping of P type in the preparation technology of follow-up selection grid.
In step 5), refer to S5 step and Fig. 3 f of Fig. 2, remove mask layer 26, and planarization is carried out to the polysilicon layer 25 that described N-type is adulterated.
In the present embodiment, the method for wet etching is adopted to remove mask layer 26.
In the present embodiment, chemical mechanical polishing method is adopted to carry out planarization to the polysilicon layer 25 that N-type is adulterated.Carry out polishing fluid that chemico-mechanical polishing adopts and concrete glossing can adopt prior art, in the present embodiment, provide a kind of embodiment, employing silicon dioxide is abrasive grains, and is added with relevant chemical addition agent.Due in polysilicon doped with N-type Doped ions, as P ion etc., there is unnecessary electronics in the surface of polysilicon, when carrying out chemico-mechanical polishing, if containing stronger cation in the additive that polishing fluid adds, excess electron in polysilicon and the cation in polishing fluid can attract each other, and cause polishing speed to increase.Under this environmental condition, the polysilicon layer of N-type doping remove that speed is obviously greater than undoped polysilicon layer remove speed.Due to the whole polysilicon layer that the region of intrinsically polysilicon layer 24 being carried out to N-type doping is except selecting grid 28 region, this just makes whole polysilicon layer most areas be the polysilicon 25 of N-type doping, so when carrying out CMP to it, while the necessary thickness of guarantee floating gate polysilicon layer, can greatly reduce and the residual polycrystalline silicon after CMP is carried out to it, effectively improve the uniformity of CMP.In addition, because the residual polycrystalline silicon carried out after planarization doped polysilicon layer is considerably less, this just need not as prior art, in order to remove residual polysilicon, further CMP is carried out to whole polysilicon layer, doing so avoids the CMP carrying out again to the floating gate polysilicon layer reaching required thickness, effectively reduce the loss of floating gate polysilicon.
Concrete, the thickness after polysilicon layer 25 planarization of described N-type doping is 100 ~ 250nm, and more preferably, the thickness after polysilicon layer 25 planarization of described N-type doping is 60 ~ 100nm.
In sum, in the present invention when carrying out N-type doping to polysilicon layer, floating grid and logic region are adulterated simultaneously, the region of namely adulterating is the whole polysilicon layer except select gate regions, this and prior art only carry out compared with N-type adulterates, considerably increasing the region of polysilicon layer N-type doping to floating grid.Due to carry out N-type doping at floating grid prerequisite under, use corresponding polishing fluid can make N-type doped polycrystalline silicon remove that speed is obviously greater than undoped polycrystalline silicon remove speed.Increase the region that polysilicon layer carries out N-type doping in such a situa-tion, when carrying out CMP to it, while the necessary thickness of guarantee floating gate polysilicon layer, can greatly reduce and the residual polycrystalline silicon after CMP is carried out to it, effectively improve the uniformity of CMP, and then avoid the generation of the problem causing floating grid to be short-circuited in the process of follow-up flash memories use to greatest extent.In addition, because the residual polycrystalline silicon carried out after CMP doped polysilicon layer is considerably less, this just need not as prior art, in order to remove residual polysilicon, further CMP is carried out to whole polysilicon layer, doing so avoids the CMP carrying out again to the floating gate polysilicon layer reaching required thickness, effectively reduce the loss of floating gate polysilicon, and then avoid the control gate caused therefrom the coupling efficiency of raceway groove is declined, the generation of the problem making the speed of the write of flash memories and erasing slack-off.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a preparation method for semiconductor device, is characterized in that, comprises the following steps:
1) providing Semiconductor substrate, being formed with the isolation structure for isolating active area in described Semiconductor substrate, the upper surface of isolation structure is higher than described Semiconductor substrate;
2) on the active area of described Semiconductor substrate, tunnel oxide is formed;
3) on described tunnel oxide and isolation structure, intrinsically polysilicon layer is formed;
4) region that the selection grid preset in described intrinsically polysilicon layer is corresponding is provided with mask layer, then N-type doping is carried out to all the other intrinsically polysilicon layer exposed;
5) remove mask layer, and planarization is carried out to the polysilicon layer that described N-type is adulterated.
2. the preparation method of semiconductor device according to claim 1, is characterized in that: also comprise the step to selecting region corresponding to grid to carry out the doping of P type after step 5).
3. the preparation method of semiconductor device according to claim 1, is characterized in that: the ion carrying out N-type doping to described intrinsically polysilicon layer in step 4) is the ion of V major element.
4. the preparation method of semiconductor device according to claim 3, is characterized in that: the ion carrying out N-type doping to described intrinsically polysilicon layer in step 4) is P ion or As ion.
5. the preparation method of semiconductor device according to claim 1, is characterized in that: the doping content of carrying out N-type doping to described intrinsically polysilicon layer in step 4) is 1.0 × 10
17~ 5.0 × 10
20atom/cm
2; Implantation Energy is between 1KeV to 30KeV.
6. the preparation method of semiconductor device according to claim 1, is characterized in that: isolation structure described in step 1) be shallow trench isolation from or selective oxidation insulate on Si.
7. the preparation method of semiconductor device according to claim 1, is characterized in that: adopt chemical mechanical polishing method to carry out planarization to the polysilicon layer that described N-type is adulterated in step 5).
8. the preparation method of semiconductor device according to claim 1, is characterized in that: the thickness after the polysilicon layer planarization of the doping of N-type described in step 5) is 100 ~ 250nm.
9. the preparation method of semiconductor device according to claim 7, is characterized in that: the thickness after the polysilicon layer planarization of the doping of N-type described in step 5) is 60 ~ 100nm.
10. the preparation method of semiconductor device according to claim 1, is characterized in that: step 2) described in the material of tunnel oxide be at least one in silica, silicon oxide/silicon nitride/silicon oxide or hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide.
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| KR100624924B1 (en) * | 2004-12-27 | 2006-09-18 | 주식회사 하이닉스반도체 | Method of forming a floating gate electrode in flash memory device |
| CN101572224A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for smoothening doped polysilicon and method for preparing polysilicon floating gate |
| US20130183819A1 (en) * | 2004-10-29 | 2013-07-18 | Spansion Llc | Semiconductor device and method for fabricating thereof |
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| CN1514485A (en) * | 2003-03-19 | 2004-07-21 | ̨��ï�����ӹɷ�����˾ | Non Volatile internal storage and its manufacturing method |
| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| US20130183819A1 (en) * | 2004-10-29 | 2013-07-18 | Spansion Llc | Semiconductor device and method for fabricating thereof |
| KR100624924B1 (en) * | 2004-12-27 | 2006-09-18 | 주식회사 하이닉스반도체 | Method of forming a floating gate electrode in flash memory device |
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