CN104572557A

CN104572557A - Bus matching method and device

Info

Publication number: CN104572557A
Application number: CN201410853858.2A
Authority: CN
Inventors: 苏俊
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2014-12-31
Filing date: 2014-12-31
Publication date: 2015-04-29
Anticipated expiration: 2034-12-31
Also published as: CN104572557B

Abstract

An embodiment of the invention provides a bus matching method and device, and relates to the field of circuit board design. The bus matching method includes the steps: sequentially selecting one pin from pins needing matching in a main control chip according to a preset matching sequence, and controlling the pins to output matching signals; determining pins receiving the matching signals from pins needing matching in a controlled chip, establishing the corresponding relationship among the pins receiving the matching signals and signal wires connected with the pins outputting the matching signals, and storing the corresponding relationship in a corresponding list of the controlled chip. The bus matching method solves the problem that the signal wires are seriously crossed in the actual signal interconnection process due to point-to-point interconnection constraint of chips in related technology, and lead crossing degree of the chips in interconnection is greatly decreased.

Description

Bus widening method and apparatus

Technical field

The present invention relates to board design field, particularly a kind of bus widening method and apparatus.

Background technology

Along with the development of digital circuit, chip functions from strength to strength, integrated level is more and more higher, same circuit board can comprise several functional chips usually, by various bus (such as local bus (English abbreviation: LB between chip, English full name: LocalBus), interconnected (the English abbreviation: QPI of express passway, English full name: Quick Path Interconnect), high speed peripheral component interlinkage (English abbreviation: PCIE, English full name: Peripheral Component Interconnect Express), Peripheral Component Interconnect (English abbreviation: PCI, English full name: Peripheral Component Interconnect), serial media independent interfaces (English abbreviation: SMII, English full name: Serial Media Independent Interface) etc. carry out interconnected, to realize the exchanges data between difference in functionality chip.

In order to make normally to work between chips on circuit boards, need to carry out initialization to each chip on circuit board, common initialized process is: circuit board power supply powers on, on circuit board, all chip reset signal solutions reset, chip directly enters mode of operation, namely by the address data bus order of agreement, the data communication between two logic chips is realized.Because this initialization procedure requires the data communication realizing between logic chip according to the address data bus order of agreement, therefore the pin between logic chip is one to one, and the signal interconnection namely on circuit board must follow the point-to-point interconnection of the identical signal of each definition.Such as, main control chip central processing unit (English abbreviation: CPU is comprised in system, English full name: Central ProcessingUnit) and controlled chip FLASH, wherein the address 0 of main control chip CPU must be connected to the address 0 of controlled chip FLASH, otherwise the contents of program in the controlled chip FLASH of the reading that main control chip CPU cannot be correct.

Realizing in process of the present invention, inventor finds that prior art at least exists following problem: due to what normally interconnected by data bus, address bus and control bus between two chips, the quantity of these buses is very many, and every root signal wire has fixed definitions, signal wire between chip can not wrong, therefore be subject to the constraint of the point-to-point interconnection of chip chamber, these signal wires there will be serious intersection in actual signal interconnection process.

Summary of the invention

In order to solve in correlation technique owing to being subject to the constraint of the point-to-point interconnection of chip chamber, cause signal wire in actual signal interconnection process, there is serious problem of intersecting, embodiments providing a kind of bus widening method and apparatus.Described technical scheme is as follows:

First aspect, provide a kind of bus widening method, described method is applied in the circuit board including main control chip and at least one controlled chip, and connect one to one without intersecting between the pin on the pin on described main control chip and same controlled chip, described method comprises:

Need successively according to predetermined matching order to select a pin in the pin carrying out mating from described main control chip, control described pin output matching signal;

Need in the pin carrying out mating from described controlled chip, determine the pin receiving described matched signal, corresponding relation between the signal wire that the described pin that foundation receives described matched signal is connected with the described pin exporting described matched signal, is saved to described corresponding relation in the corresponding lists of described controlled chip.

In the first possible embodiment of first aspect, described in determine the pin receiving described matched signal, comprising:

Detect the initializing signal whether described controlled chip receives the transmission of described main control chip, described initializing signal is used for notifying that described controlled chip mates;

When described controlled chip receives described initializing signal, need, in the pin carrying out mating, to determine the pin uniquely receiving signal, described pin is defined as the pin receiving described matched signal from described controlled chip.

In conjunction with the first possible embodiment of first aspect, in the embodiment that the second of first aspect is possible, described method also comprises:

When controlling described pin and exporting described matched signal, control described main control chip and export described initializing signal, and forbid that the pin that in described main control chip, other needs carry out mating exports described matched signal.

In conjunction with in the first possible embodiment of first aspect, first aspect or the possible embodiment of the second of first aspect, in the third possible embodiment of first aspect, corresponding relation between the signal wire that the described pin that described foundation receives described matched signal is connected with the described pin exporting described matched signal, comprising:

The pin exporting described matched signal is determined according to described predetermined matching order;

Obtain the signal wire be connected with described pin;

Set up the corresponding relation between the pin receiving described matched signal in described signal wire and described controlled chip.

In conjunction with the third possible embodiment of first aspect, in the 4th kind of possible embodiment of first aspect, described method also comprises:

When the pin mated in described controlled chip receives signal, according to the described corresponding lists stored, find the signal wire corresponding with the pin receiving described signal in described controlled chip, described signal is defined as the signal that described signal wire sends.

Second aspect, provide a kind of bus widening device, described application of installation is in the circuit board including main control chip and at least one controlled chip, and connect one to one without intersecting between the pin on the pin on described main control chip and same controlled chip, described device comprises:

First output module, selecting a pin for needing from described main control chip successively according to predetermined matching order in the pin that carries out mating, controlling described pin output matching signal;

Set up module, for needing in the pin that carries out mating from described controlled chip, determine the pin receiving the described matched signal that described first output module exports, corresponding relation between the signal wire that the described pin that foundation receives described matched signal is connected with the described pin exporting described matched signal, is saved to described corresponding relation in the corresponding lists of described controlled chip.

In the first possible embodiment of second aspect, describedly set up module, also for:

In conjunction with the first possible embodiment of second aspect, in the embodiment that the second of second aspect is possible, described device also comprises:

Second output module, for when controlling described pin and exporting described matched signal, controls described main control chip and exports described initializing signal, and forbid that the pin that in described main control chip, other needs carry out mating exports described matched signal.

In conjunction with in the first possible embodiment of second aspect, second aspect or the possible embodiment of the second of second aspect, in the third possible embodiment of second aspect, describedly set up module, also for:

Obtain the signal wire be connected with described pin;

In conjunction with the third possible embodiment of second aspect, in the 4th kind of possible embodiment of second aspect, described device also comprises:

Search module, when pin for having mated in described controlled chip receives signal, according to the described corresponding lists stored, find the signal wire corresponding with the pin receiving described signal in described controlled chip, described signal is defined as the signal that described signal wire sends.

The third aspect, provide a kind of bus widening device, described application of installation is in the circuit board including main control chip and at least one controlled chip, connect one to one without intersecting between pin on pin on described main control chip and same controlled chip, described device comprises: processor and storer, wherein, described storer is for storing one or more than one instruction, and described instruction is configured to be performed by described processor;

Described processor, selecting a pin for needing from described main control chip successively according to predetermined matching order in the pin that carries out mating, controlling described pin output matching signal;

Described processor, also for needing in the pin that carries out mating from described controlled chip, determine the pin receiving the described matched signal that described first output module exports, corresponding relation between the signal wire that the described pin that foundation receives described matched signal is connected with the described pin exporting described matched signal, is saved to described corresponding relation in the corresponding lists of described controlled chip.

In the first possible embodiment of the third aspect, described processor, also for:

In conjunction with the first possible embodiment of the third aspect, in the embodiment that the second of the third aspect is possible, described processor, also for control described pin export described matched signal time, control described main control chip and export described initializing signal, and forbid that the pin that in described main control chip, other needs carry out mating exports described matched signal.

In conjunction with in the first possible embodiment of the third aspect, the third aspect or the possible embodiment of the second of the third aspect, in the third possible embodiment of the third aspect, described processor, also for:

Obtain the signal wire be connected with described pin;

In conjunction with the third possible embodiment of the third aspect, in the 4th kind of possible embodiment of the third aspect, described processor, when pin also for having mated in described controlled chip receives signal, according to the described corresponding lists stored, find the signal wire corresponding with the pin receiving described signal in described controlled chip, described signal is defined as the signal that described signal wire sends.

The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:

By being undertaken between the pin on the pin on main control chip on circuit board and same controlled chip without cross connection, and mate one to one without cross-coupled pin between main control chip and controlled chip; The signal wire connected due to each pin on controlled chip does not distinguish circuit types, therefore the constraint of point to point connect can be no longer subject between each bar wire that each pin in main control chip is connected with each pin on same controlled chip, therefore to solve in correlation technique owing to being subject to the constraint of the point-to-point interconnection of chip chamber, cause signal wire in actual signal interconnection process, there is serious problem of intersecting; Reach the effect of the wires cross degree greatly reduced when interconnecting between chip.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the method flow diagram of the bus widening method provided in one embodiment of the invention;

Fig. 2 A is the method flow diagram of the bus widening method provided in another embodiment of the present invention;

Fig. 2 B is the structural representation of the circuit board provided in one embodiment of the invention;

Fig. 3 A is the structural representation of the circuit board provided in another embodiment of the present invention;

Fig. 3 B be provide in the present invention's part embodiment with the schematic diagram of circuit board of local bus interconnection;

Fig. 3 C be provide in section Example of the present invention with the schematic diagram of the circuit board of PCIE bus interconnection;

Fig. 3 D be provide in another part embodiment of the present invention with the schematic diagram of circuit board of local bus interconnection;

Fig. 3 E is the sequential chart that the board structure of circuit in Fig. 3 B provided in the embodiment of the present invention carries out in matching process;

Fig. 3 F is the sequential chart that the board structure of circuit in Fig. 3 C provided in the embodiment of the present invention carries out in matching process;

Fig. 3 G is the sequential chart that the board structure of circuit in Fig. 3 D provided in the embodiment of the present invention carries out in matching process;

Fig. 4 is the structural representation of the bus widening device provided in one embodiment of the invention;

Fig. 5 is the structural representation of the bus widening device provided in another embodiment of the present invention;

Fig. 6 is the structural representation of the bus widening device provided in another embodiment of the present invention.

Embodiment

For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.

Before the embodiment of the present invention being introduced and illustrating, first some nouns involved by each embodiment of the present invention and concept are described and are explained here.In each embodiment of the present invention:

Bus: be the common communication main line transmitting information between the various functional part of digital circuit, the transmission line that it is made up of physical conductors, the bus of digital circuit can be divided into data bus, address bus and control bus, is used for respectively transmitting data, data address and bus control signal.(some type bus only has synchronous clock and data bus, and the control bus in this kind of bus and address bus are integrated in data-signal by bus protocol.)

LB:LocalBus, i.e. local bus, refer to the communication bus comprising data bus, address bus and control bus three kinds of buses in the embodiment of the present invention.

Please refer to Fig. 1, the method flow diagram of the bus widening method provided in one embodiment of the invention is provided.This bus widening method can be applied in the circuit board including main control chip and at least one controlled chip, connects one to one between the pin on the pin on main control chip and same controlled chip without intersecting.This bus widening method can be applied in processor, this processor is used for control circuit board, also namely the executive agent of this bus widening method can be the processor for control circuit board, this processor can be the part arranged in the circuit board, also can be the processor be connected with circuit board.This bus widening method can comprise:

Step 101, needs successively according to predetermined matching order to select a pin in the pin carrying out mating, controls this pin output matching signal from main control chip;

Step 102, need in the pin carrying out mating from controlled chip, determine the pin receiving matched signal, set up and receive the pin of matched signal and the corresponding relation between the signal wire be just connected at the pin of output matching signal, this corresponding relation is saved in the corresponding lists of controlled chip.

In sum, the bus widening method provided in the embodiment of the present invention, by being undertaken between the pin on the pin on main control chip on circuit board and same controlled chip without cross connection, and mate one to one without cross-coupled pin between main control chip and controlled chip; The signal wire connected due to each pin on controlled chip does not distinguish circuit types, therefore the constraint of point to point connect can be no longer subject between each bar wire that each pin in main control chip is connected with each pin on same controlled chip, therefore to solve in correlation technique owing to being subject to the constraint of the point-to-point interconnection of chip chamber, cause signal wire in actual signal interconnection process, there is serious problem of intersecting; Reach the effect of the wires cross degree greatly reduced when interconnecting between chip.

Please refer to Fig. 2 A, the method flow diagram of the bus widening method provided in another embodiment of the present invention is provided.This bus widening method can be applied in the circuit board including main control chip and at least one controlled chip, connects one to one between the pin on the pin on main control chip and same controlled chip without intersecting.This bus widening method can be applied in processor, this processor is used for control circuit board, also namely the executive agent of this bus widening method can be the processor for control circuit board, this processor can be the part arranged in the circuit board, also can be the processor be connected with circuit board.This bus widening method can comprise:

Step 201, needs successively according to predetermined matching order to select a pin in the pin carrying out mating, controls this pin output matching signal from main control chip.

In actual applications, circuit board can comprise a main control chip and at least one controlled chip, main control chip is used for sending signal to controlled chip.

In order to reduce the crossing elimination between main control chip and controlled chip, can by the pin on main control chip with carry out nothing between the pin on same controlled chip and intersect and be connected one to one, for example, refer to Fig. 2 B, the structural representation of the circuit board provided in one embodiment of the invention is provided.In fig. 2b, circuit board comprises main control chip and controlled chip 1, controlled chip 2, each pin wherein on main control chip is connected without intersecting one to one with between each pin on controlled chip 1, and each pin on main control chip is connected without intersecting one to one with between each pin on controlled chip 2.

By each pin on main control chip and between each pin on same controlled chip without intersect be connected one to one time, the connection between the pin of main control chip and controlled chip pin is needed not to be limited by the constraint of chip chamber point to point connect, but in practical work process, controlled chip needs to know the signal received is that in main control chip, which signal wire sends, to ensure the correct output of circuit board, therefore need to mate one to one with the pin on controlled chip the pin on main control chip after electricity on circuit boards.

Main control chip comprises the pin that needs carry out mating, controlled chip comprises the pin that needs carry out mating, after circuit board powers on, need the pin needing in main control chip to carry out mating to mate one to one with needing the carrying out carrying out the pin mated in controlled chip.

On circuit boards after electricity for the processor of control circuit board, need successively according to predetermined matching order to select a pin in the pin carrying out mating from main control chip, and control this pin output matching signal.

Here said predetermined matching order is that processor pre-sets, also can be that processor reads from storer, carrying out in matching process, processor needs according to this matching order to select a pin to mate in the pin carrying out mating successively from main control chip, repetition can be avoided like this or omit the pin needing to carry out mating, and success ratio and the validity of coupling can be ensured.

Here said matched signal can be the one in logical signal 1 and 0.

Optionally, the processor arranged in the circuit board can comprise the first processor be arranged in main control chip and the second processor be arranged in controlled chip, or, the processor be connected with circuit board can comprise the first processor for controlling main control chip and the second processor for controlling controlled chip, step 201 now can be: first processor needs according to predetermined matching order to select a pin in the pin carrying out mating successively from main control chip, controls this pin output matching signal.

Step 202, when controlling this pin output matching signal, control main control chip and export initializing signal, and forbid that in main control chip, other needs carry out the pin output matching signal mated, this initializing signal is used for notifying that controlled chip mates.

When controlling the pin output matching signal selected from main control chip, mating to ensure that controlled chip can be learnt, processor can also control main control chip and export initializing signal, and this initializing signal is used for notifying that controlled chip mates.

In main control chip, other need the pin carrying out mating also to output signal, and have influence on the judgement of controlled chip to the pin of reception matched signal, therefore, when controlling this pin output matching signal, processor also forbids that in main control chip, other needs carry out the pin output matching signal mated.

Optionally, processor is when forbidding that in main control chip, other needs carry out the pin output matching signal mated, can forbid that the pin that in main control chip, other needs carry out mating exports any signal, also can control the pin that in main control chip, other needs carry out mating and export non-matching signal.

For example, when matched signal is 0, processor can forbid that the pin that in main control chip, other needs carry out mating exports any signal, also can control the pin that in main control chip, other needs carry out mating and all export 1.

Optionally, main control chip is when exporting initializing signal, pin can be sent by the notice in main control chip and export initializing signal, notice wherein in the main control chip notice sent in pin and controlled chip receives pin and has one-to-one relationship, and this corresponding relation to be processor known.

Optionally, initializing signal can be the one in logical signal 1 and 0, and this initializing signal is pre-set.For example, when initialization signal is 1, processor controls main control chip and sends initializing signal 1.

Optionally, the processor arranged in the circuit board can comprise the first processor be arranged in main control chip and the second processor be arranged in controlled chip, or, the processor be connected with circuit board can comprise the first processor for controlling main control chip and the second processor for controlling controlled chip, step 202 now can be: when controlling this pin output matching signal, first processor controls main control chip and exports initializing signal, and forbids that in main control chip, other needs carry out the pin output matching signal mated.

Step 203, detects the initializing signal whether controlled chip receives main control chip transmission.

Optionally, processor, when detecting controlled chip and whether receiving the initializing signal of main control chip transmission, can detect notice in controlled chip and receive the initializing signal whether pin receives main control chip transmission.

For example, notice transmission pin in main control chip receives pin with the notice in controlled chip and is connected, when initialization signal is 1, processor is when controlling the notice sending tube human hair combing waste in main control chip and sending initializing signal 1, and the processor notice then detected in controlled chip receives pin and whether receives 1.

Optionally, the processor arranged in the circuit board can comprise the first processor be arranged in main control chip and the second processor be arranged in controlled chip, or, the processor be connected with circuit board can comprise the first processor for controlling main control chip and the second processor for controlling controlled chip, and step 203 now can be: the second processor detects the initializing signal whether controlled chip receives main control chip transmission.

Step 204, when controlled chip receives this initializing signal, needs, in the pin carrying out mating, to determine the pin uniquely receiving signal, this pin is defined as the pin receiving matched signal from controlled chip.

From step 202, processor is when controlling main control chip and sending initializing signal, also control to need to carry out mating the pin output matching signal selected in pin from main control chip, and forbid that in main control chip, other needs carry out the pin output matching signal mated, again because the pin of main control chip is connected one to one with the pin of controlled chip, therefore controlled chip is when receiving this initialize signal that main control chip sends, need in the pin carrying out mating, usually only to have a pin be connected with transmission matched signal pin that matched signal can be received in controlled chip, therefore, processor can need in the pin carrying out mating from controlled chip, determine the pin uniquely receiving signal, and this pin can be defined as the pin receiving matched signal.

Optionally, when processor is when controlling main control chip and sending initializing signal, also control to need to carry out mating the pin output matching signal selected in pin from main control chip, and to control in main control chip other and need the pin carrying out mating to export non-matching signal, again because the pin of main control chip is connected one to one with the pin of controlled chip, therefore controlled chip is when receiving this initialize signal that main control chip sends, need in the pin carrying out mating, usually only to have a pin be connected with transmission matched signal pin that matched signal can be received in controlled chip, in controlled chip, other need the pin carrying out mating then only may receive the non-matching signal of main control chip transmission.Therefore, processor can need in the pin carrying out mating from controlled chip, determine the pin that the signal received by pin that received signal and controlled chip other each need to carry out mating is different, and this pin can be defined as the pin receiving matched signal.

Optionally, the processor arranged in the circuit board can comprise the first processor be arranged in main control chip and the second processor be arranged in controlled chip, or, the processor be connected with circuit board can comprise the first processor for controlling main control chip and the second processor for controlling controlled chip, step 204 now can be: when controlled chip receives initializing signal, second processor needs in the pin carrying out mating from controlled chip, determine the pin uniquely receiving signal, this pin is defined as the pin receiving matched signal.

Step 205, determines just at the pin of output matching signal according to predetermined matching order.

This predetermined matching order pre-sets within a processor, or processor reads from storer, therefore processor is when carrying out mating the pin of main control chip and the pin of controlled chip, needs can be selected successively from main control chip to carry out the pin output matching signal mated according to this predetermined matching order, corresponding, processor also needs to determine according to this predetermined matching order the pin receiving matched signal in controlled chip successively.

For example, pin corresponding to predetermined matching order is Pin0-Pin7, now, processor selects a pin output matching signal successively according to this predetermined matching order from these pins, such as, the pin Pin2 that processor third time is selected according to this predetermined matching order, and send matched signal according to this pin Pin2, processor detect in controlled chip need the pin carrying out mating to receive this matched signal time, determine to be just pin Pin2 at the pin of output matching signal according to this predetermined matching order.

It should be added that, the processor arranged in the circuit board can comprise the first processor be arranged in main control chip and the second processor be arranged in controlled chip, or, the processor be connected with circuit board can comprise the first processor for controlling main control chip and the second processor for controlling controlled chip, and step 205 now can be: the second processor is determined just at the pin of output matching signal according to predetermined matching order.

Step 206, obtains the signal wire be connected with this pin.

In actual applications, the signal wire that in the known predetermined matching order of processor and main control chip, each pin connects.Like this, processor determining just when the pin of output matching signal, then can obtain the signal wire be connected with this pin.

For example, pin corresponding to predetermined matching order is Pin0-Pin7, the signal wire that these pins connect respectively is: addr [1], addr [3], data [2], addr [2], data [1], data [0], addr [0] and data [3], now, processor selects a pin output matching signal successively according to this predetermined matching order from these pins, such as, the pin Pin2 that processor third time is selected according to this predetermined matching order, the signal wire that this pin Pin2 connects is data [2], and send matched signal according to the pin Pin2 that this signal wire data [2] connects, processor detect in controlled chip need the pin carrying out mating to receive this matched signal time, determine to be just the pin Pin2 in main control chip at the pin of output matching signal according to this predetermined matching order, and the signal wire that this pin Pin2 connects is data [2].

Optionally, main control chip comprises the bus of at least two types, now, can to be that this pin corresponding to two kinds of buses is randomly ordered obtain this predetermined matching order, also can be successively the pin sequence corresponding to dissimilar bus is obtained, such as main control chip comprises the bus of two types, pin sequence corresponding to the bus of the first type is front, pin sequence corresponding to the bus of the second type rear, and can be sequentially to sort or randomly ordered when sorting to every type bus.

Optionally, the processor arranged in the circuit board can comprise the first processor be arranged in main control chip and the second processor be arranged in controlled chip, or, the processor be connected with circuit board can comprise the first processor for controlling main control chip and the second processor for controlling controlled chip, and step 206 now can be: the second processor obtains the signal wire be connected with this pin.

Step 207, sets up the corresponding relation between the pin receiving matched signal in this signal wire and controlled chip, is saved to by this corresponding relation in the corresponding lists of controlled chip.

Processor after obtaining the signal wire be connected with this pin, then can be set up the corresponding relation between the pin receiving matched signal in this signal wire and controlled chip, and is saved to by this corresponding relation in the corresponding lists of this controlled chip.

Obviously, due to processor can learn in main control chip in advance each need to carry out the corresponding relation between the pin that mates and signal wire, processor can also set up in main control chip the corresponding relation between the pin receiving this matched signal in the pin and controlled chip sending matched signal.

Optionally, due to processor can learn in main control chip each need to carry out the corresponding relation between the pin that mates and signal wire, processor can also be set up main control chip and send corresponding relation between the pin receiving this matched signal in the signal wire and controlled chip that the pin of matched signal is connected with this pin, and the corresponding relation also namely set up comprises the pin receiving this matched signal in the pin of main control chip transmission matched signal, the signal wire be connected with this pin and controlled chip.

When actual realization, the corresponding lists of controlled chip can be stored in the storer corresponding with the circuit board including this controlled chip, also can be stored in this storer corresponding to controlled chip.Corresponding, storer said here can be connected with the processor corresponding to circuit board by bus.

Optionally, the processor arranged in the circuit board can comprise the first processor be arranged in main control chip and the second processor be arranged in controlled chip, or, the processor be connected with circuit board can comprise the first processor for controlling main control chip and the second processor for controlling controlled chip, step 207 now can be: the corresponding relation between the pin receiving matched signal in signal wire and controlled chip set up by the second processor, is saved to by this corresponding relation in the corresponding lists of controlled chip.Optionally, above-mentioned said can also to be connected with the second processor by wire for the storer storing corresponding relation.

Step 208, when the pin mated receives signal, according to the corresponding lists stored, finds the signal wire corresponding with the pin receiving this signal in controlled chip, this signal is defined as the signal that signal wire sends in controlled chip.

After coupling completes, processor can normally work by control circuit board, when normally working, the pin that processor controls in main control chip sends signal to controlled chip, corresponding, when the pin mated in controlled chip receives signal, processor can according to the corresponding lists of this controlled chip stored, find the signal wire that the pin that receives this signal in chip controlled with this is corresponding, this signal is defined as the signal that signal wire sends.

Optionally, need in controlled chip to receive signal in the pin carrying out mating, the corresponding relation that the corresponding lists of this controlled chip stores comprises pin corresponding with this pin in the pin and main control chip receiving this signal in controlled chip, now, the signal wire be connected with this pin in main control chip then searched by processor, and the signal received in controlled chip is defined as the signal that this signal wire sends.

Optionally, controlled chip receives the work notice signal that main control chip sends, and this work notice signal is used for notifying that controlled chip carries out work.Optionally, send to the pin of work notice signal can be identical with sending the pin of initializing signal in main control chip; The pin receiving work notice signal in controlled chip can be identical with the pin receiving initialize signal.

After entering mode of operation, the pin mated in controlled chip receives signal, according to the corresponding lists stored, finds the signal wire corresponding with the pin receiving this signal in controlled chip, this signal is defined as the signal that signal wire sends.

Optionally, the processor arranged in the circuit board can comprise the first processor be arranged in main control chip and the second processor be arranged in controlled chip, or, the processor be connected with circuit board can comprise the first processor for controlling main control chip and the second processor for controlling controlled chip, step 208 now can be: when the pin mated in controlled chip receives signal, second processor is according to the corresponding lists stored, find the signal wire corresponding with the pin receiving this signal in controlled chip, this signal is defined as the signal that signal wire sends.

In actual applications, in order to ensure that the signal that controlled chip can send according to main control chip is determined to carry out mating or normally working, when design circuit plate, can first determine one group of pin that there is known corresponding relation between main control chip and controlled chip, controlled chip carries out mating or normally working to utilize this group pin to notify.This group exists in the pin of known corresponding relation the pin be positioned on main control chip can be designated as notice transmission pin, and the pin be positioned on controlled chip can be designated as notice and receive pin.

Refer to shown in Fig. 3 A, the structural representation of the circuit board provided in another embodiment of the present invention is provided, this circuit board comprises main control chip 320 and two controlled chips 340, pin wherein in main control chip 320 is connected without intersecting one to one with between the pin on same controlled chip 340, main control chip 320 comprises pin 320a that needs carry out mating and notice sends pin 320b, and corresponding controlled chip 340 comprises the pin 340a and notice reception pin 340b that needs carry out mating.

Notice sends pin 320b and notice receives pin 340b one_to_one corresponding, and the quantity that notice sends pin 320b can be one, two or more, corresponding, in each control chip notice receive pin 340b also can be one, two or more.

When mating, sending pin 320b sends initializing signal can only to use one to notify, now, the predetermined matching order that storer stores defines the matching order that the pin that mates needs all in main control chip mates, and sends notice that pin 320b is connected receive pin 340b and can mate the pin that needs mate according to this predetermined matching order in controlled chip with this notice.

When mating, at least two can be used to notify, and sending pin 320b sends initializing signal, now, send pin 320b for each notice in storer and store a predetermined matching order, each predetermined matching order defines the order of mating a part of pin in the pin needing in main control chip to mate, and each notifies that sending all pins included in the predetermined matching order corresponding to pin 320b is that in main control chip, all needs carry out the pin mated.When one of them notice sends pin 320b to controlled chip transmission initializing signal, notice corresponding in controlled chip receives pin 340b after receiving initializing signal, can determine and send predetermined matching order corresponding to pin 320b with this notice, and can mate needing the pin mated according to this predetermined matching order.

Optionally, notify to send pin 320b and notify that receiving pin 340b can be the pin being exclusively used in transmission initializing signal and work notice signal arranged on circuit boards.For the circuit board of local bus interconnection, refer to shown in Fig. 3 B, it illustrates provide in the present invention's part embodiment with the schematic diagram of circuit board of local bus interconnection.In figure 3b, the pin Pin1-Pin12 in this circuit board, main control chip CPU comprised is the pin that needs carry out mating, wherein respectively with pin Pin3, Pin6, the signal wire data [0] that Pin4 with Pin1 is connected, data [1], data [2], data [3] is the signal wire in data bus, respectively with pin Pin5, Pin7, Pin2, the signal wire addr [0] that Pin8 connects, addr [1], addr [2], addr [3] is the signal wire in address bus, respectively with pin Pin9, Pin10, Pin11, the signal wire WE that Pin12 connects, RE, CS0, CS1 is the signal wire in control bus, the pin Pin13-Pin15 that this main control chip CPU also comprises is notice transmission pin, and wherein pin Pin13 is connected with signal wire addr_init, and pin Pin14 is connected with signal wire data_init, and pin Pin15 is connected with signal wire ctrl_init.

In Fig. 3 B, the pin pin1-pin11 that controlled chip FLASH comprises is the pin that needs carry out mating, signal wire ad [0]-ad [10] on controlled chip FLASH is connected with the pin Pin1-Pin11 on controlled chip FLASH respectively, and needs in CPU between the pin that carries out mating and each bar wire needing the pin carrying out mating to be connected in FLSAH without intersecting.The pin Pin13-Pin15 that controlled chip FLASH comprises is notice reception pin, the pin Pin13 that the pin Pin13 that signal wire addr_init wherein on main control chip CPU connects connects with the corresponding signal wire addr_init on controlled chip FLASH is connected by wire, the pin Pin14 that the pin Pin14 that signal wire data_init on main control chip CPU connects connects with the corresponding signal wire data_init on controlled chip FLASH is connected by wire, the pin Pin15 that the pin Pin15 that signal wire ctrl_init on main control chip CPU connects connects with the corresponding signal wire ctrl_init on controlled chip FLASH is connected by wire.For controlled chip SDRAM setting be connected with controlled chip FLASH similar, just repeat no more here.

It should be noted that, in storer, store in main control chip CPU the predetermined matching order needing the pin Pin1 to Pin12 carrying out mating, now, in pin Pin13 to Pin15 can be only set in main control chip CPU.The pin be set up in pin Pin13 to Pin15 in main control chip CPU is designated as notice and sends pin, corresponding, sends pin that pin is connected be designated as and notify to receive pin in controlled chip with this notice.

Optionally, store in main control chip CPU the predetermined matching order in the pin Pin1 to Pin12 needing to carry out mating respectively according to bus type in storer, such as, storer stores separately the predetermined matching order relevant to the pin that data bus connects, and stores separately the predetermined matching order relevant to the pin that address bus connects and stores separately the relevant predetermined matching order of the pin that is connected with control bus.

Processor pre-defines the matching order mated this three kinds of buses, such as, processor defines and first mates the pin that data bus connects, again the pin that address bus connects is mated, finally the pin that control bus connects is mated, now, the pin Pin13 to Pin15 in main control chip CPU only can arrange one of them.

Processor does not store the matching order mated this three kinds of buses, now, configuration pin Pin13 to Pin15 is then needed in main control chip CPU, wherein when mating the pin corresponding to the data bus (comprising data [0], data [1], data [2], data [3]) in main control chip CPU, pin Pin14 in main control chip CPU can be defined as notice and send pin, corresponding, pin Pin14 in controlled chip CPU is defined as notice and receives pin.

Similar, when mating the pin corresponding to the address bus (comprising addr [0], addr [1], addr [2], addr [3]) in main control chip CPU, pin Pin13 in main control chip CPU can be defined as notice and send pin, corresponding, pin Pin13 in pin Pin13 in controlled chip FLASH and controlled chip SDRAM is defined as notice and receives pin.

Similar, when mating the pin corresponding to the data bus (comprising data [0], data [1], data [2], data [3]) in main control chip CPU, pin Pin13 in main control chip CPU can be defined as notice and send pin, corresponding, pin Pin13 in pin Pin13 in controlled chip FLASH and controlled chip SDRAM is defined as notice and receives pin.

PCIE bus interconnection is passed through again with main control chip and controlled chip, main control chip is CPU, controlled chip is equipment DEV1 and equipment DEV2 is that the structure of example to circuit board is described, refer to shown in Fig. 3 C, it illustrates provide in section Example of the present invention with the schematic diagram of the circuit board of PCIE bus interconnection.In circuit board, main control chip CPU interpolation is provided with the pin be connected with signal wire data_init, this pin is designated as notice and sends pin, in main control chip CPU, remaining needs the pin carrying out mating to be connected (because the data signal line in PCIE is many respectively with the data line in data bus, simplify in Fig. 3 C, and eliminate the diagram to pin).Corresponding, the pin that the pin that in DEV1, all needs carry out mating carries out mating with each needs in main control chip CPU all is one by one without cross connection; The pin be connected with signal wire data_init is provided with in controlled chip DEV1, this pin is designated as notice and receives pin, and the pin that the pin that the signal wire data_init in main control chip CPU connects is connected with the signal wire data_init in controlled chip DEV1 by wire connects.To the setting of controlled chip DEV2 be connected with controlled chip DEV1 similar, just repeat no more here.

Obviously, in order to reduce the change to hardware, to reduce production cost, one of default setting in main control chip or part pin can also be designated as notice and send pin, sending default setting in controlled chip with notice pin that pin is connected and be designated as and notify to receive pin, and when design circuit plate, processor or storer prestore notice and send pin and notify to receive the corresponding relation between pin.

Interconnected by local bus with main control chip and controlled chip, main control chip is CPU, controlled chip is FLSH and SDRAM is that the structure of example to circuit board is described, refer to shown in Fig. 3 D, it illustrates provide in another part embodiment of the present invention with the schematic diagram of circuit board of local bus interconnection.The pin Pin1-Pin8 in this circuit board, main control chip CPU comprised is the pin that needs carry out mating, the signal wire data [0] be wherein connected with pin Pin3, Pin6, Pin4 and Pin1 respectively, data [1], data [2], data [3] are the signal wire in data bus, and the signal wire addr [0] be connected with pin Pin5, Pin7, Pin2, Pin8 respectively, addr [1], addr [2], addr [3] are the signal wire in address bus; The pin Pin9-Pin12 that this main control chip CPU also comprises is notice transmission pin, the signal wire RE be wherein connected with Pin9 in main control chip CPU is the reading signal lines in control bus, the signal wire WE be connected with Pin10 in main control chip CPU is the write signal line in control bus, the signal wire CS0 be connected with Pin11 in main control chip CPU is for selecting the chip selection signal line of FLASH in control bus, and the signal wire CS1 be connected with Pin12 is for selecting the chip selection signal line of SDRAM in control bus.

In Fig. 3 D, the pin Pin1-Pin8 that controlled chip FLASH comprises is the pin that needs carry out mating, signal wire ad [0]-ad [7] is connected with pin Pin1-Pin8 respectively, and needs in CPU to connect one to one without intersecting between the pin that carries out mating and each bar wire needing the pin carrying out mating to be connected in FLSAH.The pin Pin9-Pin11 that controlled chip FLASH comprises is notice reception pin, the pin Pin9 that wherein signal wire WE connects is connected by wire with the pin Pin9 that corresponding signal wire WE connects, the pin Pin10 that the pin Pin10 that signal wire RE connects connects with corresponding signal wire WE is connected by wire, and the pin Pin11 that the pin Pin11 that signal wire CS connects connects with corresponding signal wire CS0 is connected by wire.To the setting of controlled chip SDRAM be connected with controlled chip FLASH similar, just repeat no more here.

Optionally, one of them in the pin Pin9-Pin12 of main control chip CPU is set to notice transmission pin, and in the pin Pin9-Pin12 of main control chip CPU, other pins remaining and pin Pin1 to Pin8 are the pin needing to carry out mating.Optionally, one of them in the pin Pin1-Pin11 of main control chip CPU is set to notice transmission pin, and in the pin Pin1-Pin11 of main control chip CPU, remaining pin is the pin needing to carry out mating.

For the circuit board involved by Fig. 3 B, Fig. 3 C and Fig. 3 D, each step in Fig. 2 is described respectively below.

The process that composition graphs 3B mates pin Pin1 to Pin12 in main control chip CPU is as follows:

The predetermined matching order that main control chip CPU needs the pin Pin1 to Pin12 mated to mate is followed successively by: Pin5, Pin7, Pin2, Pin8, Pin3, Pin6, Pin4, Pin1, Pin9, Pin10, Pin11, Pin12, Pin13 in main control chip sends pin as notice, and the Pin13 in controlled chip receives pin as notice.

Matching process is as follows:

1, the Pin13 of CPU exports initializing signal 0, and notice FLASH/Pin13 and SDRAM/Pin13 mates.

When the logical signal that FLASH/Pin13 and SDRAM/Pin13 receives is 0, show that CPU prepares to mate, in follow-up, FLASH and SDRAM then can mate according to predetermined matching order.

2, when the Pin13 of CPU exports initializing signal 0, choose addr [the 0]/Pin5 output matching signal 0 of CPU according to predetermined matching order, and forbid that in CPU, other each needs carry out the pin output matching signal 0 mated.

Now, the pin that other each needs carry out mating can not output signal, and also can export non-matching signal 1.

3, when the logical signal received as FLASH/Pin13 and SDRAM/Pin13 is 0, the signal only having ad [4]/Pin2 to receive in the Pin1 ~ Pin11 of FLASH chip is 0 logic, now FLASH chip then sets up the corresponding relation in FLASH in Pin2 and main control chip between addr [0], and is stored in the corresponding lists of FLASH by this corresponding relation.Only have ad [5]/Pin6 to be 0 logic in the Pin1 ~ Pin11 of SDRAM, now SDRAM chip then sets up the corresponding relation in SDRAM in Pin6 and main control chip between addr [0], and is stored in the corresponding lists of SDRAM by this corresponding relation.

According to predetermined matching order, from CPU, choose the pin needing to carry out mating successively, repeat and be similar to above-mentioned step 1 to step 3, the corresponding lists of the FLASH obtained after having mated is as following table 1:

Table 1

The signal wire of pin and the connection of mating is needed in FLASH	The signal wire of pin and the connection of mating is needed in CPU
		Pin2/ad[4]	addr[0]/Pin5
Pin10/ad[6]	addr[1]/Pin7
		Pin5/ad[1]	addr[2]/Pin2
Pin3/ad[7]	addr[3]/Pin8

Pin11/ad[2]	data[0]/Pin3
		Pin6/ad[5]	data[1]/Pin6
Pin1/ad[3]	data[2]/Pin4
		Pin9/ad[0]	data[3]/Pin1
Pin7/ad[8]	WE/Pin9
		Pin4/ad[9]	RE/Pin10
Pin8/ad[10]	CS0/Pin11

The corresponding lists of the SDRAM obtained after having mated is as following table 2:

Table 2

The signal wire of pin and the connection of mating is needed in SDRAM	The signal wire of pin and the connection of mating is needed in CPU
		Pin6/ad[5]	addr[0]/Pin5
Pin3/ad[7]	addr[1]/Pin7
		Pin1/ad[3]	addr[2]/Pin2
Pin5/ad[1]	addr[3]/Pin8
		Pin7/ad[8]	data[0]/Pin3
Pin9/ad[0]	data[1]/Pin6
		Pin2/ad[4]	data[2]/Pin4
Pin8/ad[10]	data[3]/Pin1
		Pin11/ad[2]	WE/Pin9
Pin4/ad[9]	RE/Pin10
		Pin10/ad[6]	CS0/Pin12

After coupling completes, the signal that FLASH can utilize table 1 to determine that in FLASH, Pin1 to Pin11 receives is which signal wire of CPU sends, and the signal that SDRAM can utilize table 2 to determine that in SDRAM, Pin1 to Pin11 receives is which signal wire of CPU sends.

Optionally, in actual applications, the predetermined matching order of every type bus is stored in storer, processor directly can access out these predetermined matching order from storer, or store these predetermined matching order in processor, now, can respectively the pin corresponding to every type bus be mated.Optionally, in the matching process, carry out the pin output matching signal mated at the needs controlling to select in main control chip, control the pin that in main control chip, other needs carry out mating and export non-matching signal.Still the circuit board involved by Fig. 3 B is mated, refer to shown in Fig. 3 E carrying out the sequential chart in matching process, the process of composition graphs 3B and Fig. 3 E to the coupling of WE, the RE in data bus data [0] to data [3], address bus addr [0] to addr [3] and control bus is as follows:

What storer stored is followed successively by the predetermined matching order that the corresponding pin of data bus data [0] to data [3] in main control chip CPU mates: Pin5, Pin7, Pin2, Pin8, the predetermined matching order that the corresponding pin of address bus addr [0] to addr [3] in main control chip CPU mates is followed successively by: Pin3, Pin6, Pin4, Pin1, to the WE in control bus in main control chip CPU, the predetermined matching order that pin corresponding to RE carries out mating is followed successively by Pin9, Pin10, addr_init/Pin13 in main control chip CPU, data_inti/Pin14 and ctrl_init/Pin15 sends pin respectively as notice, Pin13/addr_inti in controlled chip FLASH and SDRAM, Pin14/data_inti and Pin15/ctrl_init receives pin as notice, storer defines the corresponding relation between each notice transmission pin and each notice reception pin.

Matching process is as follows:

1, the notice of CPU sends pin addr_init/Pin13 and exports initializing signal 0 logic, and lasting duration is T1, the current preparation sequence of addresses coupling of notice FLASH/Pin13 and SDRAM/Pin13.

When the signal that FLASH/Pin13 and SDRAM/Pin13 receives is 0, show that CPU prepares to carry out sequence of addresses coupling, in follow-up, FLASH and SDRAM then can carry out order coupling according to the predetermined matching order addr [0] corresponding with address bus/Pin5, addr [1]/Pin7, addr [2]/Pin2 and addr [3]/Pin8.

2, send after pin addr_init/Pin13 exports initializing signal 0 logic T2 duration in the notice of CPU, according to addr [0]/Pin5 output matching signal 0 logic of predetermined matching order control CPU corresponding to address bus, lasting duration is T1.General, the value of T2 is less than T1.

3, the signal received at the notice reception pin of FLASH SDRAM meets addr_init/Pin13 rising edge, ad [4]/Pin2 is only had to be 0 logic in the Pin1 ~ Pin11 of FLASH chip, now FLASH chip is then set up by the corresponding relation of addr [0] in Pin2 in FLASH and main control chip, and is stored in the corresponding lists of FLASH by this corresponding relation.Only have ad [5]/Pin6 to be 0 logic in the Pin1 ~ Pin11 of SDRAM, now SDRAM then sets up the corresponding relation of addr [0] in Pin6 and main control chip in SDRAM, and is stored in the corresponding lists of SDRAM by this corresponding relation.

Because FLASH and SDRAM is the order coupling of carrying out according to predetermined matching order addr [0]/Pin5, addr [1]/Pin7, addr [2]/Pin2 and addr [3]/Pin8 corresponding with address bus, first is addr [0]/Pin5, the corresponding relation between addr [the 0]/Pin5 that therefore can set up ad [4]/Pin2 and the CPU receiving matched signal 0 logic.

According to the predetermined matching order of address bus, from CPU, choose the pin corresponding to address bus needing to carry out mating successively, repeat and be similar to above-mentioned step 1 to step 3, complete the coupling to address bus.

Similar, respectively data bus and control bus are mated, and set up corresponding relation, just repeat no more here.

It should be noted that, for control bus, CPU send WE RE the order of CS signal time, need to become consistent with the reception sequence constraint that controlled chip (FLASH, SDRAM) is held, namely controlled chip receive the order of these signals be also WE RE the order of CS signal, otherwise the coupling of control signal will be made mistakes.

Pin coupling is carried out to circuit board involved in Fig. 3 C, refer to shown in Fig. 3 F carrying out the sequential chart in matching process, composition graphs 3C and Fig. 3 F to data bus CPU _ PCIE1 [3:0] _ RX/TX ±, CPU_PCIE2 [7:0] _ RX/TX ± the process of order coupling as follows:

Predetermined matching order has been pre-defined in processor, or prestore predetermined matching order in storer, and processor can obtain this predetermined matching order from storer, predetermined matching order is wherein followed successively by: CPU_PCIE1 [3:0] _ RX+, CPU_PCIE1 [3:0] _ RX-, CPU_PCIE1 [3:0] _ TX+, CPU_PCIE1 [3:0] _ TX-, CPU_PCIE2 [7:0] _ RX+, CPU_PCIE2 [7:0] _ RX-, CPU_PCIE2 [7:0] _ TX+, CPU_PCIE2 [7:0] _ TX-, the pin that in main control chip, signal wire data_init connects sends pin as notice, the pin that in controlled chip, signal wire data_init connects receives pin as notice.Optionally, in the matching process, carry out the pin output matching signal mated at the needs controlling to select in main control chip CPU, control the pin that in main control chip CPU, other needs carry out mating and export non-matching signal.

Matching process is as follows:

1, the notice that in CPU, signal wire data_init connects sends pin and exports initializing signal 0 logic, and the duration is T1, the current preparation data sequence coupling of notice DEV1 DEV2.

2, after the notice that signal wire data_init connects in CPU sends the pin output initializing signal 0 logic T2 time, according to CPU_PCIE1 [0] _ RX+ output matching signal 0 logic of predetermined matching order control CPU, the duration is T1.

3, CPU_PCIE1 [0] _ this signal of RX+ is connected to DEV1, be not connected to DEV2, so when the signal that notice reception pin in DEV1 DEV2 receives meets data_init rising edge, have in the signal that in DEV1, signal wire DEV1_PCIE [15:0] _ DATA receives and only have a signal to be 0 logic, now DEV1 then sets up in the pin and CPU being currently received 0 logic between CPU_PCIE1 [0] _ RX+ corresponding relation, and is stored in the corresponding lists of DEV1 by this corresponding relation.All pins in DEV2 corresponding to signal wire DEV2_PCIE [31:0] _ DATA all do not receive 0 logic, and now DEV2 ignores this data_init rising edge received, and is left intact.

According to predetermined matching order, from CPU, choose the pin needing to carry out mating successively, repeat and be similar to above-mentioned step 1 to step 3, complete the coupling to all data buss.

It should be added that, addr_init data_init ctrl_init also can with existing signal multiplexing (such as CPU_PCIE1 [0] _ RX+ signal and addr_init signal multiplexing), this method can reduce the change to existing hardware.

Optionally, in actual applications, the predetermined matching order of the known every type bus of processor, now, can mate for the pin corresponding to every type bus respectively.Optionally, in the matching process, the needs controlling to select in main control chip carry out the pin output matching signal mated, and control the pin that in main control chip, other needs carry out mating and export non-matching signal.Optionally, pin existing in circuit board is carried out multiplexing, send pin by pin multiplexing in main control chip as notice, pin multiplexing in controlled chip is received pin as notice.Pin in circuit board involved in Fig. 3 D is mated, refer to shown in Fig. 3 G carrying out the sequential chart in matching process, the process of composition graphs 3D and Fig. 3 G to the coupling of data bus data [0] to data [3] and address bus addr [0] to addr [3] is as follows:

Processor definition the predetermined matching order that the corresponding pin of data bus data [0] to data [3] in main control chip CPU mates is followed successively by: Pin5, Pin7, Pin2, Pin8, the predetermined matching order that the corresponding pin of address bus addr [0] to addr [3] in main control chip CPU mates is followed successively by: Pin3, Pin6, Pin4, Pin1, WE/Pin9 in main control chip CPU, RE/Pin10, the pin that CS0/Pin11 with CS1/Pin12 is connected sends pin respectively as notice, Pin9/WE in controlled chip FLASH and SDRAM, Pin10/RE and Pin11/CS receives pin as notice.

Matching process is as follows:

1, main control chip CPU is when powering on, and first controls notice transmission pin CS0/Pin11 and exports 0 logic, and now the notice reception pin CS/Pin11 of controlled chip FLASH can receive a sheet and select 0 logic, and controlled chip FLASH is selected.

2, the notice of main control chip CPU sends pin WE/Pin9 and exports initializing signal 0 logic, notifies that controlled chip FLASH mates.

When the logical signal that FLASH/Pin9 receives is 0, show that CPU prepares to carry out sequence of addresses coupling, in follow-up, FLASH then can carry out order coupling according to the predetermined matching order addr [0] of address/Pin5, addr [1]/Pin7, addr [2]/Pin2 and addr [3]/Pin8.

3, the RE/Pin10 of main control chip CPU exports initializing signal 0 logic, and lasting duration is T1.

4, after the RE/Pin10 of main control chip CPU exports initializing signal 0 logic T2 duration, addr [0]/Pin5 output matching signal 0 logic of main control chip CPU, lasting duration is T1, and T2 is wherein less than T1.

When 5, meeting CS/Pin110 logic, WE/Pin90 logic, RE/Pin10 rising edge on controlled chip FLASH output pin, ad [the 4]/Pin5 that only has in the Pin1 ~ Pin8 of controlled chip FLASH is 0 logic, now controlled chip FLASH then sets up the corresponding relation between addr [0] that the Pin5 that is currently received logical signal 0 and main control chip CPU sends logical signal, is saved to by this corresponding relation in the corresponding lists of controlled chip FLASH.

6, CS0/Pin11, WE/Pin9 of main control chip CPU remain 0 logic, and the RE/Pin10 of main control chip CPU exports second initializing signal 0 logic, the 3rd initializing signal 0 logic and the 4th initializing signal 0 logic respectively; And when the RE/Pin10 of main control chip CPU exports second initializing signal 0 logic, control addr [1] output matching signal 0; When the RE/Pin10 of main control chip CPU exports the 3rd initializing signal 0 logic, control addr [2] output matching signal 0; When the RE/Pin10 of main control chip CPU exports the 4th initializing signal 0 logic, control addr [3] output matching signal 0.Controlled chip FLASH sets up the corresponding relation between corresponding relation between corresponding relation between ad [6]/Pin7 and addr [1], ad [1]/Pin2 and addr [2], ad [7]/Pin8 and addr [3] in this process respectively, these corresponding relations are saved in the corresponding lists of controlled chip FLASH, complete the coupling of address bus order.

Continue to carry out order coupling to each signal wire data [0] to data [3] in data bus, it is the pin in main control chip CPU corresponding to write signal line WE that the notice chosen sends pin, each signal wire data [0] to data [3] all output logic signals 1 in this write signal line WE and CPU, the predefined procedure corresponding with data bus is data [0]/Pin3, data [1]/Pin6, data [2]/Pin4 and data [3]/Pin1, and matching process is as follows:

7, the CS0/Pin11 of main control chip CPU still keeps output 0 logic, and WE/Pin9 recovers output 1 logic, and RE/Pin10 keeps output 0 logic, makes controlled chip FLASH enter data sequence matching stage.

When the logical signal that FLASH/Pin10 receives is 0, show that CPU prepares to carry out data sequence coupling, in follow-up, FLASH then can carry out order coupling according to the predetermined matching order data [0] of data bus, data [1], data [2] and data [3].

8, the WE/Pin9 of main control chip CPU exports 0 logic, and lasting duration is T1.

9, after the WE/Pin9 of main control chip CPU exports 0 logic T2 duration, data [the 0]/Pin3 of main control chip CPU exports 0 logic, and lasting duration is T1.

When 10, meeting CS/Pin110 logic, RE/Pin100 logic, WE/Pin9 rising edge on controlled chip FLASH output pin, ad [the 2]/Pin3 that only has in the Pin1 ~ Pin8 of controlled chip FLASH is 0 logic, and now controlled chip FLASH then records the data [0] of the current corresponding main control chip CPU of ad [2].

11, CS0/Pin11, RE/Pin10 of main control chip CPU remain 0 logic, and the WE/Pin9 of main control chip CPU exports second initializing signal 0 logic, the 3rd initializing signal 0 logic and the 4th initializing signal 0 logic respectively; And when the WE/Pin9 of main control chip CPU exports second initializing signal 0 logic, control data [1] output matching signal 0; When the WE/Pin9 of main control chip CPU exports the 3rd initializing signal 0 logic, control data [2] output matching signal 0; When the WE/Pin9 of main control chip CPU exports the 4th initializing signal 0 logic, control data [3] output matching signal 0.Controlled chip FLASH sets up corresponding relation between ad [5]/Pin6 and addr [1] in this process respectively, set up corresponding relation between ad [3]/Pin4 and addr [2], set up corresponding relation between ad [0]/Pin1 and addr [3], now completes sequence of addresses coupling.

After completing the coupling of each pin on controlled chip FLASH, the CS0/Pin11 of main control chip CPU reverts to 1 logic, synchronism output CS1/Pin12 is 0 logic, according to similar method adaptive with the pin of controlled chip FLASH, completes the pin adaptation work of controlled chip SDRAM.After all peripheral hardwares complete adaptation, the cpu system on circuit board can enter normal mode of operation.

Shown in Figure 4, the structural representation of the bus widening device provided in one embodiment of the invention is provided.This bus widening device can be applied in the circuit board including main control chip and at least one controlled chip, connect one to one without intersecting between pin on pin on main control chip and same controlled chip, this bus widening method can be applied in processor, this processor is used for control circuit board, also namely the executive agent of this bus widening method can be the processor for control circuit board, this processor can be the part arranged in the circuit board, also can be the processor be connected with circuit board.This bus widening device can include but not limited to: the first output module 420 and set up module 440.

Described first output module 420, selecting a pin for needing from described main control chip successively according to predetermined matching order in the pin that carries out mating, controlling described pin output matching signal;

Describedly set up module 440, for needing in the pin that carries out mating from described controlled chip, determine the pin receiving the described matched signal that described first output module 420 exports, corresponding relation between the signal wire that the described pin that foundation receives described matched signal is connected with the described pin exporting described matched signal, is saved to described corresponding relation in the corresponding lists of described controlled chip.

In sum, the bus widening device provided in this aspect embodiment, undertaken between the pin on the pin on main control chip on circuit board and same controlled chip without cross connection, and mate one to one without cross-coupled pin between main control chip and controlled chip; The signal wire connected due to each pin on controlled chip does not distinguish circuit types, therefore the constraint of point to point connect can be no longer subject between each bar wire that each pin in main control chip is connected with each pin on same controlled chip, therefore to solve in correlation technique owing to being subject to the constraint of the point-to-point interconnection of chip chamber, cause signal wire in actual signal interconnection process, there is serious problem of intersecting; Reach the effect of the wires cross degree greatly reduced when interconnecting between chip.

Shown in Figure 5, the structural representation of the bus widening device provided in another embodiment of the present invention is provided.This bus widening device can be applied in the circuit board including main control chip and at least one controlled chip, connect one to one without intersecting between pin on pin on main control chip and same controlled chip, this bus widening method can be applied in processor, this processor is used for control circuit board, also namely the executive agent of this bus widening method can be the processor for control circuit board, this processor can be the part arranged in the circuit board, also can be the processor be connected with circuit board.This bus widening device can include but not limited to: the first output module 520 and set up module 540.

Described first output module 520, selecting a pin for needing from described main control chip successively according to predetermined matching order in the pin that carries out mating, controlling described pin output matching signal;

Describedly set up module 540, for needing in the pin that carries out mating from described controlled chip, determine the pin receiving the described matched signal that described first output module 520 exports, corresponding relation between the signal wire that the described pin that foundation receives described matched signal is connected with the described pin exporting described matched signal, is saved to described corresponding relation in the corresponding lists of described controlled chip.

Based in the embodiment provided embodiment illustrated in fig. 5, describedly set up module 540, also for:

Based in the embodiment provided embodiment illustrated in fig. 5, described bus widening device also comprises: the second output module 560.

Described second output module 560, for when controlling described pin and exporting described matched signal, controls described main control chip and exports described initializing signal, and forbid that the pin that in described main control chip, other needs carry out mating exports described matched signal.

Obtain the signal wire be connected with described pin;

Based in the embodiment provided embodiment illustrated in fig. 5, described bus widening device also comprises: search module 580.

Describedly search module 580, when pin for having mated in described controlled chip receives signal, according to the described corresponding lists stored, find the signal wire corresponding with the pin receiving described signal in described controlled chip, described signal is defined as the signal that described signal wire sends.

It should be noted that: the bus widening device that above-described embodiment provides is when carrying out bus widening, only be illustrated with the division of above-mentioned each functional module, in practical application, can distribute as required and by above-mentioned functions and be completed by different functional modules, inner structure by circuit board is divided into different functional modules, to complete all or part of function described above.In addition, the bus widening device that above-described embodiment provides and bus widening embodiment of the method belong to same design, the bus widening device that above-described embodiment provides and bus widening embodiment of the method belong to same design, and its specific implementation process refers to embodiment of the method, repeats no more here.

Shown in Figure 6, the structural representation of the bus widening device provided in another embodiment of the present invention is provided.This bus widening device can be applied in the circuit board including main control chip and at least one controlled chip, connects one to one between the pin on the pin on main control chip and same controlled chip without intersecting.This bus widening device can include but not limited to: bus 610, and is connected to processor 620 and the storer 630 of bus 610.Wherein, storer 630 is for storing one or more than one instruction, and this instruction is configured to be performed by processor 620.Wherein:

Described processor 620, selecting a pin for needing from described main control chip successively according to predetermined matching order in the pin that carries out mating, controlling described pin output matching signal;

Described processor 620, also for needing in the pin that carries out mating from described controlled chip, determine the pin receiving described matched signal, corresponding relation between the signal wire that the described pin that foundation receives described matched signal is connected with the described pin exporting described matched signal, is saved to described corresponding relation in the corresponding lists of described controlled chip.

Based in the embodiment provided embodiment illustrated in fig. 6,

Described processor 620, whether receive the initializing signal of described main control chip transmission for detecting described controlled chip, described initializing signal is used for notifying that described controlled chip mates;

Described processor 620, for when described controlled chip receives described initializing signal, need, in the pin carrying out mating, to determine the pin uniquely receiving signal, described pin is defined as the pin receiving described matched signal from described controlled chip.

Based in the embodiment provided embodiment illustrated in fig. 6,

Described processor 620, for when controlling described pin and exporting described matched signal, controls described main control chip and exports described initializing signal, and forbid that the pin that in described main control chip, other needs carry out mating exports described matched signal.

Based in the embodiment provided embodiment illustrated in fig. 6,

Described processor 620, for determining according to described predetermined matching order the pin exporting described matched signal;

Described processor 620, for obtaining the signal wire be connected with described pin;

Described processor 620, for setting up the corresponding relation between the pin receiving described matched signal in described signal wire and described controlled chip.

Based in the embodiment provided embodiment illustrated in fig. 6, described processor 620, when pin for having mated in described controlled chip receives signal, according to the described corresponding lists stored, find the signal wire corresponding with the pin receiving described signal in described controlled chip, described signal is defined as the signal that described signal wire sends.

The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.

One of ordinary skill in the art will appreciate that all or part of step realizing above-described embodiment can have been come by hardware, the hardware that also can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. a bus widening method, it is characterized in that, described method is applied in the circuit board including main control chip and at least one controlled chip, and connect one to one without intersecting between the pin on the pin on described main control chip and same controlled chip, described method comprises:

2. method according to claim 1, is characterized in that, described in determine the pin receiving described matched signal, comprising:

3. method according to claim 2, is characterized in that, described method also comprises:

4. want arbitrary described method in 1 to 3 according to right, it is characterized in that, the corresponding relation between the signal wire that the described pin that described foundation receives described matched signal is connected with the described pin exporting described matched signal, comprising:

Obtain the signal wire be connected with described pin;

5. want the method described in 4 according to right, it is characterized in that, described method also comprises:

6. a bus widening device, it is characterized in that, described application of installation is in the circuit board including main control chip and at least one controlled chip, and connect one to one without intersecting between the pin on the pin on described main control chip and same controlled chip, described device comprises:

7. device according to claim 6, is characterized in that, describedly sets up module, also for:

8. device according to claim 7, is characterized in that, described device also comprises:

9. want arbitrary described device in 6 to 8 according to right, it is characterized in that, describedly set up module, also for:

Obtain the signal wire be connected with described pin;

10. want the device described in 9 according to right, it is characterized in that, described device also comprises: