CN104572514A - Globally shared I/O (input/output) server design method - Google Patents

Globally shared I/O (input/output) server design method Download PDF

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Publication number
CN104572514A
CN104572514A CN201510027205.3A CN201510027205A CN104572514A CN 104572514 A CN104572514 A CN 104572514A CN 201510027205 A CN201510027205 A CN 201510027205A CN 104572514 A CN104572514 A CN 104572514A
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China
Prior art keywords
subsystem
subsystems
server
controller
computing
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CN201510027205.3A
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Chinese (zh)
Inventor
贡维
林楷智
李鹏翀
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Inspur Electronic Information Industry Co Ltd
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Langchao Electronic Information Industry Co Ltd
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Priority to CN201510027205.3A priority Critical patent/CN104572514A/en
Publication of CN104572514A publication Critical patent/CN104572514A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)

Abstract

The invention provides a globally shared I/O server design method. A globally shared I/O server system comprises computing subsystems, I/O subsystems and interconnection subsystems. Processors in any of the computing subsystems are connected to the interconnection subsystems through node controllers and all of the processors can access I/O controllers in any of the I/O subsystems to achieve global sharing of I/O resources. Every computing subsystem is used for server data calculation and processing and comprises a processor, a memory and a node controller, wherein the node controller is connected to the interconnection subsystems. Every I/O subsystem is used for server data storage and transmission and comprises an I/O controller and a plurality of PCIe slots for I/O expansion, wherein the I/O controller is connected to the interconnection subsystems and the PCIe slots are used for connecting I/O devices. Every interconnection subsystem is used for interconnecting all modules in a server, comprises a high-speed interconnection chip and is connected to the computing subsystems and the I/O subsystems.

Description

A kind of method for designing of overall share I/O server
Technical field
The present invention relates to Computer Applied Technology field, specifically a kind of method for designing of overall share I/O server.
Background technology
High-end server generally refers to the internal memory shared server system be made up of more than 8 or 8 processors, and it has stronger computing power and IO extended capability, is widely used in the crucial industry higher to Performance And Reliability requirement.The composition of high-end computer generally comprises the parts such as computing subsystem, I/O subsystem, interconnects subsystems and ADMINISTRATION SUBSYSTEM.
The composition of the server of tradition this type as shown in Figure 1, computing subsystem is connected to interconnects subsystems by high-speed interconnect bus, can realize the access of cross-node between computing subsystem, for example, computing subsystem 1 can processor in access computation subsystem 2 and memory source.Can realize 8,16,32 the even interconnection of more processors by the connection of interconnects subsystems between multiple computing subsystem, and the internal memory of all processors is shared.In addition, each computing subsystem has the I/O subsystem of its correspondence to realize the expansion of IO, and I/O subsystem is attached to this computing subsystem, and both are communicated by I/O interconnect bus.This be designed with a significant shortcoming be exactly I/O extendability poor, can not realize flexibly global I/O share.Such as I/O subsystem 1 can only be accessed by computing subsystem 1, wanting in other computing subsystems must by computing subsystem 1 when accessing I/O subsystem 1, whole access leapfrog is longer, and when computing subsystem 1 is stopped using, the I/O subsystem 1 of its correspondence also cannot employ.
Summary of the invention
The present invention proposes the method for designing that one realizes overall share I/O server, its function realized is all I/O(input and output in server) device resource all can access control to all processors.
The object of the invention is to realize in the following manner, overall situation share I/O server system comprises: computing subsystem, I/O subsystem and interconnects subsystems, processor in any computing subsystem is connected to interconnects subsystems by Node Controller, all processors can access the I/O controller in arbitrary I/O subsystem, thus realize sharing of global I/O resource, wherein:
Computing subsystem, the data in charge server calculate and process, and comprise processor, internal memory and Node Controller, wherein Node Controller is connected with interconnects subsystems;
I/O subsystem, the data in charge server store and data transmission, and comprise I/O controller and several PCIe slots for I/O expansion, wherein I/O controller is connected with interconnects subsystems, and PCIe slot is for connecting I/O equipment;
Interconnects subsystems, the interconnection of all intermodules in charge server, comprises high-speed interconnect chip, and interconnects subsystems is connected with computing subsystem and I/O subsystem.
The invention has the beneficial effects as follows: in order to solve the flexible configuration problem of I/O resource, the present invention proposes the server implementation method of a kind of overall share I/O.As shown in Figure 2, computing subsystem is still connected to interconnects subsystems by high-speed interconnect bus, realize processor, memory source share, I/O subsystem is also connected in interconnects subsystems simultaneously, the processor of so any computing subsystem just can access the resource of all I/O subsystems by interconnects subsystems, thus realizes sharing of global I/O.
Accompanying drawing explanation
Fig. 1 is traditional high-side server each several part composition structural representation;
Fig. 2 is the high-end server composition structural representation shared based on I/O;
Fig. 3 is the system architecture schematic diagram of the high-end server that I/O shares.
Embodiment
With reference to Figure of description, method of the present invention is described in detail below.
As shown in Figure 3, one of the present invention realizes the method for designing of overall share I/O server, and its composition comprises: (1) computing subsystem; (2) I/O subsystem; (3) interconnects subsystems.
(1) computing subsystem: comprise processor, internal memory and Node Controller.For 2 processors in the present invention, every processor has respective internal memory, and two processors are connected to Node Controller by Cache consistance bus, and then Node Controller is connected to interconnects subsystems.Wherein the effect of Node Controller forms the conforming tight coupling internal memory sharing system of overall Cache.
(2) I/O subsystem: it mainly comprises I/O controller and several PCIe slots for I/O expansion.Wherein I/O controller is connected to interconnects subsystems, PCIe slot for connecting I/O equipment, such as hard disk, network interface etc.
(3) interconnects subsystems: mainly comprise high-speed interconnect chip, high-speed interconnect chip be responsible for connecting Node Controller in computing subsystem and and I/O subsystem in I/O controller.
In above-mentioned server system, the processor in any computing subsystem can access the I/O controller in arbitrary I/O subsystem by interconnects subsystems, thus realizes sharing of global I/O resource.
Except the technical characteristic described in instructions, be the known technology of those skilled in the art.

Claims (1)

1. the method for designing of overall share I/O server, it is characterized in that, overall situation share I/O server system comprises: computing subsystem, I/O subsystem and interconnects subsystems, processor in any computing subsystem is connected to interconnects subsystems by Node Controller, all processors can access the I/O controller in arbitrary I/O subsystem, thus realize sharing of global I/O resource, wherein:
Computing subsystem, the data in charge server calculate and process, and comprise processor, internal memory and Node Controller, wherein Node Controller is connected with interconnects subsystems;
I/O subsystem, the data in charge server store and data transmission, and comprise I/O controller and several PCIe slots for I/O expansion, wherein I/O controller is connected with interconnects subsystems, and PCIe slot is for connecting I/O equipment;
Interconnects subsystems, the interconnection of all intermodules in charge server, comprises high-speed interconnect chip, and interconnects subsystems is connected with computing subsystem and I/O subsystem.
CN201510027205.3A 2015-01-20 2015-01-20 Globally shared I/O (input/output) server design method Pending CN104572514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510027205.3A CN104572514A (en) 2015-01-20 2015-01-20 Globally shared I/O (input/output) server design method

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Application Number Priority Date Filing Date Title
CN201510027205.3A CN104572514A (en) 2015-01-20 2015-01-20 Globally shared I/O (input/output) server design method

Publications (1)

Publication Number Publication Date
CN104572514A true CN104572514A (en) 2015-04-29

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105607709A (en) * 2015-07-22 2016-05-25 加弘科技咨询(上海)有限公司 lectronic device
CN106095720A (en) * 2016-06-21 2016-11-09 浪潮(北京)电子信息产业有限公司 A kind of multichannel computer system
CN106844263A (en) * 2016-12-26 2017-06-13 中国科学院计算技术研究所 It is a kind of based on configurable multiprocessor computer system and implementation method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1133993A (en) * 1995-03-15 1996-10-23 三菱电机株式会社 Multi-computer system
CN1591367A (en) * 2003-09-02 2005-03-09 三星电子株式会社 Method and apparatus for sharing a device among multiple CPU systems
CN103150264A (en) * 2013-01-18 2013-06-12 浪潮电子信息产业股份有限公司 Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method
CN103488605A (en) * 2013-09-24 2014-01-01 许继集团有限公司 Bus architecture for multiprocessor parallel communication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1133993A (en) * 1995-03-15 1996-10-23 三菱电机株式会社 Multi-computer system
CN1591367A (en) * 2003-09-02 2005-03-09 三星电子株式会社 Method and apparatus for sharing a device among multiple CPU systems
CN103150264A (en) * 2013-01-18 2013-06-12 浪潮电子信息产业股份有限公司 Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method
CN103488605A (en) * 2013-09-24 2014-01-01 许继集团有限公司 Bus architecture for multiprocessor parallel communication

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105607709A (en) * 2015-07-22 2016-05-25 加弘科技咨询(上海)有限公司 lectronic device
CN105607709B (en) * 2015-07-22 2019-10-01 加弘科技咨询(上海)有限公司 Electronic device
CN106095720A (en) * 2016-06-21 2016-11-09 浪潮(北京)电子信息产业有限公司 A kind of multichannel computer system
CN106844263A (en) * 2016-12-26 2017-06-13 中国科学院计算技术研究所 It is a kind of based on configurable multiprocessor computer system and implementation method
CN106844263B (en) * 2016-12-26 2020-07-03 中国科学院计算技术研究所 Configurable multiprocessor-based computer system and implementation method

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Application publication date: 20150429