CN104569675B - Flicker detection circuit and detection method in electric energy metering chip - Google Patents

Flicker detection circuit and detection method in electric energy metering chip Download PDF

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CN104569675B
CN104569675B CN201410854846.1A CN201410854846A CN104569675B CN 104569675 B CN104569675 B CN 104569675B CN 201410854846 A CN201410854846 A CN 201410854846A CN 104569675 B CN104569675 B CN 104569675B
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尹汝泼
王红美
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Shanghai Beiling Co Ltd
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Abstract

The invention provides a flicker detection circuit in an electric energy metering chip, which comprises an input conversion module and a processing module which are connected with each other, wherein the input conversion module is used for receiving a differential input analog voltage signal, converting the differential input analog voltage signal into a first digital signal and outputting the first digital signal to the processing module, and the processing module is used for realizing the detection of flicker visual sensitivity and outputting an instantaneous flicker visual sensitivity value. The invention also provides a flicker detection method in the electric energy metering chip. The method can meet the basic requirements of IEC, reduce the circuit resource overhead and power consumption of flicker detection, and reduce the implementation cost of flicker detection.

Description

Flicker detection circuit and detection method in electric energy metering chip
Technical Field
The invention relates to a flicker detection circuit and a flicker detection method in an electric energy metering chip.
Background
Along with the rapid development of the industry, the power load equipment with impact power is greatly increased, so that the voltage fluctuation and flicker of a power supply system of a power grid are caused, and sensitive electrical equipment is influenced. The international electrotechnical commission IEC formally lists voltage fluctuation and flicker as important indexes for measuring the quality of electric energy. As the grade is closest to the grade of a European power system, China refers to IEC61000-4-15 specifications, and establishes a voltage fluctuation flicker standard GB/T12326-2008 and a flicker meter function design and test specification GB/T17626.15-2011.
The current research on voltage flicker analysis methods and implementations can be roughly divided into analog and digital types. The simulation design takes hardware as a main body, modification and upgrading are inconvenient, and instruments are expensive. The digital implementation is through a/D sampling, followed by various digital processing using a microcomputer, such as a virtual instrument. The software-based implementation method is flexible, but has large calculation amount and higher requirements on the performance of the processor. With the improvement of the level of integrated circuit design and manufacturing process, the realization of digital flicker meter based on special hardware digital circuit ASIC becomes a new focus of design research. The chip area is rapidly reduced along with the improvement of the process, so that the flicker circuit is integrated in special chips such as an intelligent metering chip and the like, the flicker measurement is simpler and easier, and the measurement cost is greatly reduced. The integration of flicker function will further strengthen the effect of metering chip in the electric energy quality monitoring field undoubtedly, promote manufacturer's product competitiveness, also put forward new requirement to the design of metering chip.
Disclosure of Invention
In order to effectively realize the flicker detection function in the metering chip, the invention provides a flicker detection circuit and a detection method in the electric energy metering chip on the basis of IEC flicker instrument specifications, thereby reducing the circuit resource overhead and power consumption of flicker detection.
The invention provides a flicker detection circuit in an electric energy metering chip, which comprises an input conversion module and a processing module which are connected with each other, wherein the input conversion module is used for receiving a differential input analog voltage signal, converting the differential input analog voltage signal into a first digital signal and outputting the first digital signal to the processing module, and the processing module is used for realizing the detection of flicker visual sensitivity and outputting an instantaneous flicker visual sensitivity value.
Specifically, the output conversion module includes a gain amplifier and an analog-to-digital converter, which are connected in sequence, where the gain amplifier is configured to scale an input signal to a linear interval suitable for the analog-to-digital converter to operate, and the analog-to-digital converter is configured to convert the input analog signal into the first digital signal and output the first digital signal to the processing module.
Specifically, the processing module includes:
the voltage waveform sampling module is connected with the input conversion module and used for receiving the first digital signal and generating and outputting a second digital signal;
the effective value calculating module is connected with the voltage waveform sampling module and used for receiving the second digital signal, calculating and outputting an effective value of the second digital signal;
the visual sensation detection module is connected with the voltage waveform sampling module and the effective value calculation module and is used for detecting the flicker visual sensation of the input second digital signal and generating and outputting an instantaneous flicker visual sensation numerical value;
and the digital clock frequency division module is respectively connected with the voltage waveform sampling module, the effective value calculating module and the visual sensitivity detection circuit and is used for providing a digital clock signal.
A circuit configuration module: and the input conversion module, the voltage waveform sampling module, the effective value calculating module and the visual sensation measuring module are respectively connected and used for storing and providing configuration parameters.
Specifically, the voltage waveform sampling module comprises a down-sampling filter, a direct current isolation circuit and a digital gain adjusting circuit which are connected in sequence;
the down-sampling filter is used for receiving the first digital signal and restoring the first digital signal into a digital sequence in a fixed-point format;
the direct current isolation circuit is used for receiving the digital sequence and filtering out direct current components in the digital sequence;
the digital gain adjusting circuit is used for adjusting and outputting the second digital signal.
Specifically, the effective value calculation module includes a multiplier, an integrator, a squaring operation circuit, an average value calculation circuit, and a smoothing filter, which are connected in sequence, and is configured to output the effective value through the smoothing filter after the second digital signal is subjected to squaring operation, integrating operation, squaring operation, and average value operation.
Specifically, the visibility detection module includes: the input adaptation circuit, the square demodulator, the high-pass low-pass filter, the frequency weighting filter, the square sum integral filter circuit and the auxiliary optimization circuit receive the input of the second digital signal and output the instantaneous flicker visual sensitivity value.
Preferably, the input adaptation circuit comprises a sampling rate adaptation circuit, an effective value normalization circuit and a digital gain setting circuit;
the sampling rate adaptation circuit adjusts the sampling frequency of the flicker detection circuit according to the input bandwidth and the flicker sensitive frequency range, reduces the sampling rate by adopting a two-stage extraction mode and comprises a first lower extraction module and a second lower extraction module;
the effective value normalization circuit uses the effective value output by the effective value calculation circuit as a normalization divisor factor to adjust the voltage waveforms with different amplitudes to a uniform reference level;
the digital gain adjusting circuit reduces the input signal by setting the digital gain register to a proper proportion, avoids overflow in subsequent fixed point circuit operation caused by overlarge voltage fluctuation, and automatically executes an amplification recovery function before outputting a flicker visibility detection result.
Preferably, the auxiliary optimization circuit comprises a direct current bias accelerating circuit, a vision sensitivity coefficient normalizing circuit and a vision sensitivity gain compensating circuit;
the direct current offset accelerating circuit is used for adaptively subtracting a direct current offset component from an output signal of the square demodulator, eliminating the direct current component contained in the output signal of the square demodulator and accelerating the convergence speed of a high-pass filter connected behind the square demodulator;
the vision sensitivity coefficient normalization circuit normalizes the coefficient of the detected fluctuation voltage before the weighting filter, so that the output meets the IEC-defined requirement of the fluctuation amplitude of the relative voltage of the vision sensitivity output of 1 perception unit;
the visual sensitivity gain compensation circuit uses a compensation value obtained by calibration according to actual conditions to set a register, and compensates the filter gain attenuation of the visual sensitivity detection circuit before the instantaneous flicker visual sensitivity is output.
The invention also relates to a flicker detection method in the electric energy metering chip, which is based on the flicker detection circuit in the electric energy metering chip as claimed in claim 6, and comprises the following steps:
an analog-to-digital conversion step: the input conversion module converts the received differential input analog voltage signal into a first digital signal and inputs the first digital signal to the processing module;
voltage waveform sampling: the voltage waveform sampling module receives the first digital signal, generates and outputs a second digital signal;
calculating an effective value: the effective value calculation module receives the second digital signal, performs effective value calculation on the second digital signal, and generates and outputs an effective value;
visual sensitivity detection: the visual sensitivity detection module receives the effective value and the second digital signal, and generates and outputs an instantaneous flicker visual sensitivity value;
wherein the effective value calculating step includes: and carrying out square operation, integral operation, square-on operation and average value operation on the input second digital signal in sequence, and then outputting the effective value through the smoothing filter.
Specifically, the visual acuity detecting step includes:
a sampling rate adaptation step, which adopts a two-stage extraction mode to reduce the sampling rate, and concretely comprises the steps that a first-stage extraction is realized by inputting a second digital signal through a first lower extraction module, the extraction sampling rate meets the bandwidth requirement of an IEC input signal, and then, a second-stage extraction is realized by a low-pass filtering signal through a second lower extraction module, and the reduction of the sampling rate meets the requirement of the upper limit of flicker frequency;
an effective value normalization step, namely, using the effective value output by the effective value calculation circuit as a normalization divisor factor to adjust the second digital signals with different amplitudes to be uniform to a reference level;
a digital gain adjustment step, namely grading the gain adjustment proportion, selecting a proper proportion by setting a digital gain register, reducing an input signal, avoiding overflow in subsequent fixed point circuit operation caused by overlarge voltage fluctuation, and automatically executing an amplification recovery function before outputting a flicker visibility detection result;
a DC offset acceleration step for eliminating a DC component contained in the output signal of the square demodulator and accelerating the convergence speed of a high-pass filter connected behind the DC offset acceleration step, specifically, adaptively subtracting a DC offset component from the output signal of the square demodulator;
a visual sensitivity coefficient normalization step for normalizing the measured visual sensitivity coefficient and outputting it, specifically, dividing the output signal of the low-pass filter before the frequency weighting filter by a constant normalization coefficient;
and a visibility gain compensation step for compensating for the filter gain attenuation of the visibility detection circuit prior to the instantaneous flicker visibility output, in particular by dividing the instantaneous flicker visibility signal output by the smoothing low-pass filter by a constant value, which is set by a register.
The flicker detection circuit and the detection method in the electric energy metering chip can meet the basic IEC requirement, reduce the circuit resource overhead and power consumption of flicker detection and reduce the implementation cost of flicker detection.
Drawings
FIG. 1 is a block diagram of a flicker detection circuit in the electric energy metering chip of the present invention;
FIG. 2 is a block diagram of a voltage waveform sampling module;
FIG. 3 is a block diagram of an effective value calculation module;
FIG. 4 is a block diagram of a visibility detection module;
fig. 5 is an IEC visibility frequency characteristic curve.
Detailed Description
The following describes the flicker detection circuit and method in the electric energy metering chip in detail with reference to the accompanying drawings. Fig. 1 is a structural diagram of a flicker detection circuit in an electric energy metering chip according to the present invention, as shown in fig. 1, in this embodiment, an input conversion module 1 is configured to receive voltage signals VP and VN input differentially, scale the input signals to a linear region suitable for an analog-to-digital converter 12 to operate through a gain amplifier 11, and the analog-to-digital converter 12 is configured to convert an input analog signal into a first digital signal and output the first digital signal to a processing module 2.
The voltage waveform sampling module 21 is connected to the analog-to-digital converter 12, and is configured to receive the first digital signal and output a second digital signal, and the specific structure of the voltage waveform sampling module is as shown in fig. 2, and includes a down-sampling filter 211, a dc isolation circuit 212, and a digital gain adjustment circuit 213, which are connected in sequence.
The effective value calculating module 22 is connected to the voltage waveform sampling module 21 for calculating an effective value of the second digital signal, specifically, as shown in fig. 3, the effective value is finally output by the multiplier 221, the integrator 222, the square-on operation circuit 223, the average value calculating circuit 224 and the smoothing filter circuit 225 which are connected in sequence, wherein the integrator 222 adopts a low-pass filter to simulate an integration function, and the smoothing filter circuit 225 uses a low-pass filter LPF3 for suppressing the effective value transition.
The visual sensitivity detection module 23 is respectively connected with the voltage waveform sampling module 21 and the effective value measuring module 22, receives the second digital signal and the effective value as input, and outputs an instantaneous flicker visual sensitivity value. Specifically, as shown in fig. 4, the adaptive filter is composed of an input adaptation circuit 231, a square demodulator 232, a high-pass low-pass filter 233, a frequency weighting filter 234, a square sum integration filter 235, and an auxiliary optimization circuit 236; in the input adaptation circuit 231, DGA is a digital gain adjustment module. As shown in fig. 4, the auxiliary optimization circuit 236 includes a DC bias accelerating circuit ST _ DC, a sensitivity timing normalization circuit, and a sensitivity gain compensation circuit ST _ GN.
In addition, the digital clock frequency division module 24 is respectively connected to the voltage waveform sampling module 21, the effective value calculation module 22 and the visibility detection module 23, and provides a digital clock signal for the sampling rate change during the visibility detection process, and provides a clock driving signal to the above modules.
The circuit configuration module 25 is used for storing configuration information of all modules, including gain setting parameters of each module, module on and off control parameters, and the like.
In addition, the invention also provides a flicker detection method in the electric energy metering chip, and the flicker detection method in the electric energy metering chip is described in detail below with continuing reference to the attached drawings.
An analog-to-digital conversion step: the input conversion module 1 converts the received differential input analog voltage signal VP/VN into a first digital signal, and inputs the first digital signal to the processing module 2, specifically, the gain amplifier 11 scales the input signal to a linear interval suitable for the analog-to-digital converter 12 to operate, and the analog-to-digital converter 12 is configured to convert the input analog signal into the first digital signal and output the first digital signal to the processing module 2. The conversion precision of the analog-to-digital converter 12 affects the accuracy of measurement, and the conversion precision of the analog-to-digital converter is generally between 16 bits and 20 bits in the current measurement chip meeting the national network standard. According to the IEC standard, the input relative voltage fluctuation multiple of the sensing unit can be expressed with the precision of 10e-5 orders of magnitude, the minimum value is 0.199% times, and the test accuracy requirement of 5% influences the second place after the decimal point of the fluctuation multiple percentage, namely the voltage fluctuation multiple is at least expressed with 10e-4 orders of magnitude. The range of the ADC output in a metering chip is typically between-1000, +1000 mV, and a typical voltage channel typically operates on the order of 100 mV. The output precision of the ADC is at least 10e-5 stages or 16 bits in combination, so that the fluctuation voltage information can be detected. In fact, the ADC precision also depends on the minimum scaling range of voltage fluctuation that each flicker meter manufacturer needs to realize, for example, if the minimum scaling is 0.1 times, the ADC precision needs to reach 10e-6 levels, or 18 bits, and obviously, the detection of the voltage fluctuation puts more strict requirements on the ADC precision.
Because an ADC in a metering chip generally adopts a Sigma-Delta modulator oversampling technology, the effective bit width of actual output depends on the signal-to-noise ratio that can be achieved by the design of an SDM modulator, and if the number of bits of a quantizer is B, OSR times oversampling, theoretically, the SDM signal-to-noise ratio of M order is:
in the electric energy metering application, the bandwidth of an input signal is relatively small, the working frequency is low, in order to simplify the complexity of a hardware circuit, a second-order SDM noise shaping structure of a 1-bit quantizer is generally adopted in a metering chip, and the effective bit width of an ADC is increased by a method of increasing the oversampling multiple. To meet the requirement of ripple voltage detection with 0.1 times scaling,
the OSR is approximately 266.14 times, and in applications the OSR is usually an integer power of 2, and when the OSR is 256, the effective Bit width is 17.86 bits. Due to factors such as different design structures and manufacturing processes, the actual realization precision is generally lower than the theoretical precision. At this time, the minimum zoom factor can be properly increased to meet the requirement of test precision.
Voltage waveform sampling: the voltage waveform sampling module receives the first digital signal, generates and outputs a second digital signal, specifically, the voltage waveform sampling module comprises a down-sampling filter, receives the first digital signal, restores the first digital signal into a high-precision digital signal in a fixed-point format and outputs the high-precision digital signal, and a direct current isolation circuit performs direct current filtering.
The output of the SDM modulator is processed by a sampling filter and restored to a high precision value. In this embodiment, the maximum output resolution can be achieved when the comb filter SINC is used as the down-sampling filter
Bw=M log2OSR+Bi(3)
Wherein M is CIC order, OSR is decimation multiple, and Bi is input signal bit width. And the third-order SINC filter meets the requirement on bit width during 256-time down-sampling.
The peripheral circuit of the chip and the internal analog-to-digital conversion circuit can introduce direct current components into waveform sampling signals, so that the accuracy of electric energy measurement and voltage fluctuation detection are influenced. Amplitude-modulated wave v (ω) at a single frequency, assuming the presence of a DC component c in the signalFt)=VmcosωFt modulates the power frequency carrier wave,
Um、ωNthe amplitude and angular frequency of the power frequency carrier voltage are respectively. According to the IEC flicker square demodulation principle,
the existence of the direct current component c in the waveform sampling strengthens the direct current component in the square term and also introduces the power frequency carrier omegaN、(ωNF)、(ωNF) And (4) components. Filtering out DC component and 2 times power frequency related component according to IEC recommendation method to obtain approximate expression of fluctuation voltage, wherein the power frequency related component can cause voltage fluctuation to be incapable of normal demodulation,
v'(t)=Um 2mcosωFt+2cUmcosωNt+cUmmcos(ωNF)t+cUmmcos(ωNF)t(6)
square demodulation requires that the fluctuating component be associated only with the amplitude modulated waveThe dc component c must be filtered out.
In the design of a metering chip, after the analog signal is subjected to digital sampling, a configurable high-pass filter is designed to isolate a direct-current component, and the diagram is shown in figure 1. The voltage signal modulated by the sine amplitude modulation wave with a single frequency can be decomposed into the following frequency components,
the cut-off frequency of the high-pass filter is selected so as not to affect the transmission of the ripple component, ωc<<ωNFWherein 0.5Hz is not more than omegaF≤35Hz,ωN50Hz, therefore, ωc<<ωNFIs less than 15 Hz. The rectangular amplitude modulated wave can be decomposed into a series of sine wave superposition in a Fourier mode, low-frequency fluctuation components are influenced by high-pass filtering, and the design of cut-off frequency of the rectangular amplitude modulated wave is close to 0Hz in order to reduce errors. An IIR type ButterWorth filter with the cutoff frequency of 2.5Hz is designed in the design of a metering chip to meet the requirement of voltage fluctuation detection. When the voltage fluctuation detection function is started in the metering chip, the high-pass filter must be started.
Calculating an effective value:
fig. 5 is an IEC visibility frequency characteristic curve, where the amplitude of the voltage input pin is often different for different meter designs or different metering applications, and in order to eliminate the influence of the changed amplitude on the fluctuation detection, so as to satisfy the IEC-defined voltage fluctuation-flicker visibility frequency response curve, the flicker visibility level measurement needs to be normalized by applying an effective value. Considering that the digital circuit realizes fixed-point operation, normalization is carried out before the voltage signal enters the fluctuation detection circuit, and the processing precision of the subsequent digital circuit can be improved. After the HPF output waveform signal is normalized,
the accuracy of the effective value affects the result of the normalization, resulting in flicker measurement errors, when, the squared demodulated signal is,
the IEC standard specifies a tolerance range of 0.2% for the effective value of the half-wave in the steady state. The steady-state precision of the effective value output of the current metering chip can reach 0.1% at most, and is equivalent to a voltage fluctuation modulation coefficient, which is at most equal to 0.2% of error, and theoretically can meet the requirements of IEC standard.
In this embodiment, the effective value calculation module 22 as shown in fig. 3 is used to complete the effective value calculation step and output a high-precision effective value. The square operation circuit 221, the integrating circuit 222 and the open square 223 circuit are included, wherein the integrating circuit 222 is used for extracting a squared direct current component. For the convenience of realization, a low-pass filter LPF is usually used for simulating integration to attenuate components above twice power frequency, but the frequency response of the low-pass filter LPF is not an ideal rectangular window, certain components of twice power frequency are left in the output of the LPF, and certain sine ripples are superposed on an effective value.
The existence of the voltage fluctuation component aggravates the ripple phenomenon, formula (10), wherein the modulation coefficient m is small, the quadratic coefficient term of m is ignored, and ki is the gain of the low-pass filter at the corresponding frequency component,k0≈1,kwf>>k2wn,k2wn+wf,k2wn-wf
The double power frequency component is still a main ripple component, but as the frequency of the ripple voltage decreases, kwfApproximately equal to 1, the ripple voltage ripple is gradually strengthened. The cut-off frequency of the LPF is reduced, the order is increased, the ripple phenomenon can be improved, and the cost is that the convergence time of the LPF is prolonged. The average value calculation module can further smooth the ripple component of the fluctuating voltage by adjusting the accumulation time of the accumulator.
The existing effective value operation circuit (namely, the circuit shown in fig. 3) in the metering chip is directly multiplexed, so that repeated design caused by adopting an IEC method can be avoided, and the reduction of the chip area and the power consumption are facilitated. However, existing valid value results cannot be used directly for normalization operations. The average value operation module keeps the result unchanged between two adjacent times of calculation and causes the output waveform to jump at the updating moment. Unlike the IEC half-cycle effective value calculation, the jump behavior is sufficient to affect the detection of rectangular amplitude modulated waves, since the calculation does not require synchronization with the zero crossing points. And IEC stipulates that each flicker meter with a class classifier should be able to withstand a series of rectangular voltage fluctuations given in the table, and the instantaneous flicker visibility Pst should be 1.0 + -0.05 in each case.
TABLE 1 test Specifications for IEC flicker instrument class classifier
During the normalization of the effective value, the jump of the effective value caused by the ripple is superposed with the rectangular amplitude modulation wave, and particularly, pseudo rectangular fluctuation is caused on the low-frequency rectangular voltage fluctuation. In this case, the extended average calculation time may reflect a more realistic effective value, for example, when the amplitude modulation wave has 1 rectangular change per minute, the frequency is 1/120Hz, and the cumulative time is 120s to cover one complete amplitude modulation wave change including both positive and negative directions. GBT17626.15-2011 specifies a step change in rms input value with a response time at least equal to 1 minute. The sampling rate of the effective value operation circuit can reach KSPS, and the overlong integration time can greatly increase the implementation expense of an accumulator.
The low pass filter LPF3 is a smoothing interpolation filter introduced to suppress significant value transitions. Unlike the first order rc filter with a time constant of 27.3s recommended in IEC. In the effective value calculation circuit of the metering chip, as shown in fig. 3, low-pass straightening filtering is firstly carried out, zero-crossing synchronization is not needed in average value calculation, the accumulation time is an integral multiple of the power frequency carrier period, and at the moment, the convergence time of the effective value mainly depends on an LPF filter. This allows the time constant of the smoothing filter LPF3 to be reduced by a large amount, for example, 1 s. Suitably extending the average calculation time may further reduce the response time of the transitions.
Visual sensitivity detection:
using the circuit shown in fig. 4, the sensitivity detection is performed based on the second digital signal and the effective value. The signal processing of the visual sensitivity detection circuit mainly comprises an input adaptation module, a square demodulator, a high-pass low-pass filter, a frequency weighting filter, a square sum integral filter and an auxiliary optimization circuit, and the output is flicker visual sensitivity level. The step realizes the flicker instrument detection process recommended by IEC, and the statistical analysis of data is realized in a main control chip or an upper computer outside the metering chip.
Wherein the input voltage waveform adaptation functions include sample rate adaptation, significance normalization, and digital gain setting. Wherein
And (3) sampling rate adaptation, wherein according to the flicker sensitive frequency range of 0.05Hz-35Hz, theoretically, the sampling rate of the detection circuit is only required to be higher than 2 times of the upper limit frequency, namely 70Hz, and the excessive sampling rate can cause resource waste and power consumption increase. The power grid contains rich power frequency harmonic components, in order to guarantee the electric energy metering precision, the waveform sampling rate in the metering chip is generally higher, for example, 40-order harmonic metering is taken as an example, the bandwidth is 2KHz, the sampling rate at least reaches more than 4KSPS, and the sampling rate can reach 14KSPS or higher during actual design. The sampling rate adaptation adopts a two-stage extraction mode to reduce the sampling rate and realize the lower extraction of the integral power of 2.
First downsampling module D0: the voltage waveform sampling rate is not lower than 1.4KHz after down-sampling, and the bandwidth of the signal input into the voltage fluctuation detection circuit is not lower than 700Hz according to the IEC standard regulation;
second downsampling module D1: located after the 6 th order ButterWorth low pass filter LPF1, the IEC recommends a cutoff frequency of 35Hz for the 230V/50Hz system, with the output being an approximate voltage ripple component. Because the high-frequency component of 2 times of power frequency and above is suppressed, the sampling rate can be further reduced through D1, the requirement of flicker frequency upper limit is met, and more than 100Hz is selected practically.
Effective value normalization adjusts voltage waveforms of different amplitudes to a uniform reference level for different amplitudes applied to the voltage input pins of the metering chip. Under the circuit multiplexing mode, two input waveform normalization circuits are considered:
normalization before squaring the demodulator: the square root of the effective value operation result multiplied by 2 is converted into a voltage peak value which is used as a divisor, voltage waveform data is used as a dividend, and the division result is sent to a square demodulator, wherein the square root of the coefficient 2 can be simplified and realized in a shifting mode after the square demodulator;
normalization after squaring the demodulator: considering that the effective value circuit has performed voltage waveform squaring operation, the division operation can also be performed after the square demodulator is moved, D0 extracts the square voltage waveform and directly serves as a dividend, and at this time, the effective value needs to be squared and then serves as the dividend;
digital gain adjustment module DGA: the amplitude of the normalized voltage waveform is 1, the voltage fluctuation range can reach 20% according to the IEC standard, in order to avoid overflow in subsequent fixed-point circuit operation, the register AGN is set to reduce the input signal by a proper proportion, and the reduction proportion is designed to be four grades of 1,1/2,1/4 and 1/8; before the flicker visibility detection result is output, the amplification recovery function is automatically executed in the detection circuit according to the AGN set value.
The auxiliary optimization circuit comprises a direct current bias acceleration module, a vision sensitivity coefficient normalization module and a gain compensation module.
DC bias accelerates DCR: the output signal of the square demodulator contains a large dc component, formula (5), and the cut-off frequency of the HPF1 of the high pass filter is low, and the time constant is large, which results in too long convergence time of the HPF 1. To speed up the convergence speed of the HPF1, a DC offset ST _ DC component is subtracted from the output signal of the squaring demodulator. Suppose DGA is 1 and m<<1, the dc component caused by the modulation index is negligible, and after normalization of the voltage waveform, the corresponding dc component is approximately 1/2. Then ST _ DC can be made DGA2/2。
Visual sensitivity coefficient normalization:
the output signal of the square demodulator is subjected to band-pass filter composed of HPF1 and LPF1 to extract fluctuation voltage component, wherein the design of HPF1 and LPF1 follows IEC recommended parameters, and takes single-waveform sine voltage fluctuation as an example to obtain approximate fluctuation voltage, AGN is 1,
wherein d is the relative voltage fluctuation multiple, dwf,d8.8HzSine voltage fluctuation multiple of corresponding frequency for generating 1 perception unit visual sensitivity output, dnK (f) is a weighted value corresponding to the fluctuation frequency on the frequency characteristic curve of the visual sensitivity.
The visual sensitivity weighting filter BPF simulates the sensitivity characteristic K (f) of a lamp, an eye and a brain to weight the voltage fluctuation to obtain a flicker signal,
the square multiplier simulates the nonlinear perception characteristic of human eyes-brain, weights the flicker signal,
after smoothing treatment (taking direct current) by a low pass filter LPF2 simulating the memory characteristics of human brain, an instantaneous vision sensitivity output S (t) is obtained,
the equation (14) does not satisfy the IEC-defined list of relative voltage fluctuation amplitudes of 1-perceived-unit sensitivity outputs, but has a coefficient, and thus needs to be normalized. Due to d8.8HzWhen the voltage fluctuation component obtained after band-pass filtering is 0.25%, the voltage fluctuation component obtained after band-pass filtering is small, the value is further reduced after the subsequent square operation according to the formula (11), and the output accuracy of the subsequent digital fixed-point operation is reduced, so that the coefficient of the fluctuation voltage is normalized before the weighting filter. The square root operation of 2 involved can be shifted to the following square root operation by shifting.
In addition, the invention also comprises a gain compensation step, wherein a gain compensation register ST _ GN is utilized, from the generation of voltage waveform, the calculation of effective value to the detection of fluctuating voltage, signals flow through a plurality of filters with different functions, and the nonideal of the filter characteristics causes the accumulated attenuation of the signals, thereby affecting the accuracy of the final output result. Therefore, a gain correction compensation link V _ CHGN/V _ RMSGN is designed in both a voltage waveform generation circuit and an effective value calculation circuit in the metering chip so as to meet the accuracy of electric energy metering. The effective value normalization operation may further reduce the effects of input signal gain attenuation. The gain compensation register ST _ GN is mainly used for compensating the filter gain attenuation of the visual sensitivity detection circuit, and is designed according to each filter parameter recommended by IEC, so that a theoretical compensation value can be deduced, F (.). represents frequency response,
ST_GN=[(|FHPF1F)|·|FLPF1F)|·|FBPFF)|)2·(1+|FLPF2(2ωF)|)]-1(15)
when a single sinusoidal voltage at 8.8Hz fluctuates, ST _ GN defaults to 0.967464, ensuring a visual perception output of 1 perceived unit. In practice, when the filter is digitized, different digitization methods will result in slightly different theoretical values of ST _ GN, which need to be set according to actual conditions.
In summary, the circuit resource overhead and power consumption of flicker detection can be reduced while the IEC standard is satisfied by using the flicker detection circuit and the detection method in the electric energy metering chip.

Claims (9)

1. A flicker detection circuit in an electric energy metering chip is characterized by comprising an input conversion module and a processing module which are connected with each other, wherein the input conversion module is used for receiving a differential input analog voltage signal, converting the differential input analog voltage signal into a first digital signal and outputting the first digital signal to the processing module;
wherein the processing module comprises: the voltage waveform sampling module is connected with the input conversion module and used for receiving the first digital signal and generating and outputting a second digital signal;
the effective value calculating module is connected with the voltage waveform sampling module and used for receiving the second digital signal, calculating and outputting an effective value of the second digital signal;
the visual sensation detection module is connected with the voltage waveform sampling module and the effective value calculation module and is used for detecting the flicker visual sensation of the input second digital signal and generating and outputting an instantaneous flicker visual sensation numerical value;
the digital clock frequency division module is respectively connected with the voltage waveform sampling module, the effective value calculating module and the visual sensitivity detection circuit and is used for providing a digital clock signal;
a circuit configuration module: and the input conversion module, the voltage waveform sampling module, the effective value calculating module and the visual sensation measuring module are respectively connected and used for storing and providing configuration parameters.
2. The flicker detection circuit of claim 1, wherein the input conversion module comprises a gain amplifier and an analog-to-digital converter connected in series, the gain amplifier is configured to scale the input signal to a linear interval suitable for the analog-to-digital converter to operate, and the analog-to-digital converter is configured to convert the input analog signal into the first digital signal and output the first digital signal to the processing module.
3. The flicker detection circuit of claim 1, wherein the voltage waveform sampling module comprises a down-sampling filter, a dc isolation circuit and a digital gain adjustment circuit connected in series;
the down-sampling filter is used for receiving the first digital signal and restoring the first digital signal into a digital sequence in a fixed-point format;
the direct current isolation circuit is used for receiving the digital sequence and filtering out direct current components in the digital sequence;
the digital gain adjusting circuit is used for adjusting and outputting the second digital signal.
4. The flicker detection circuit of claim 1, wherein the effective value calculating module comprises a multiplier, an integrator, a squaring circuit, a mean value calculating circuit, and a smoothing filter connected in sequence, and is configured to output the effective value through the smoothing filter after the second digital signal is subjected to a squaring operation, an integrating operation, a squaring operation, and a mean value operation.
5. The flicker detection circuit of claim 1, wherein the visual sensitivity detection module comprises: the input adaptation circuit, the square demodulator, the high-pass low-pass filter, the frequency weighting filter, the square sum integral filter circuit and the auxiliary optimization circuit receive the input of the second digital signal and output the instantaneous flicker visual sensitivity value.
6. The flicker detection circuit in an electric energy metering chip of claim 5, wherein the input adaptation circuit comprises a sampling rate adaptation circuit, an effective value normalization circuit and a digital gain setting circuit;
the sampling rate adaptation circuit adjusts the sampling frequency of the flicker detection circuit according to the input bandwidth and the flicker sensitive frequency range, reduces the sampling rate by adopting a two-stage extraction mode and comprises a first lower extraction module and a second lower extraction module;
the effective value normalization circuit uses the effective value output by the effective value calculation circuit as a normalization divisor factor to adjust the voltage waveforms with different amplitudes to a uniform reference level;
the digital gain adjusting circuit reduces the input signal by setting the digital gain register to a proper proportion, avoids overflow in subsequent fixed point circuit operation caused by overlarge voltage fluctuation, and automatically executes an amplification recovery function before outputting a flicker visibility detection result.
7. The flicker detection circuit of claim 5, wherein the auxiliary optimization circuit comprises a DC accelerating circuit, a visual sensitivity coefficient normalizing circuit and a visual sensitivity gain compensating circuit;
the direct current offset accelerating circuit is used for adaptively subtracting a direct current offset component from an output signal of the square demodulator, eliminating the direct current component contained in the output signal of the square demodulator and accelerating the convergence speed of a high-pass filter connected behind the square demodulator;
the vision sensitivity coefficient normalization circuit normalizes the coefficient of the detected fluctuation voltage before the weighting filter, so that the output meets the IEC-defined requirement of the fluctuation amplitude of the relative voltage of the vision sensitivity output of 1 perception unit;
the visual sensitivity gain compensation circuit uses a compensation value obtained by calibration according to actual conditions to set a register, and compensates the filter gain attenuation of the visual sensitivity detection circuit before the instantaneous flicker visual sensitivity is output.
8. A flicker detection method in an electric energy metering chip is based on the flicker detection circuit in the electric energy metering chip as claimed in claim 5, and is characterized by comprising the following steps:
an analog-to-digital conversion step: the input conversion module converts the received differential input analog voltage signal into a first digital signal and inputs the first digital signal to the processing module;
voltage waveform sampling: the voltage waveform sampling module receives the first digital signal, generates and outputs a second digital signal;
calculating an effective value: the effective value calculation module receives the second digital signal, performs effective value calculation on the second digital signal, and generates and outputs an effective value;
visual sensitivity detection: the visual sensitivity detection module receives the effective value and the second digital signal, detects and outputs an instantaneous flicker visual sensitivity value;
wherein the effective value calculating step includes: and carrying out square operation, integral operation, square-on operation and average value operation on the input second digital signal in sequence, and then outputting the effective value through a smoothing filter.
9. The method of claim 8, wherein the step of detecting visual sensitivity comprises:
a sampling rate adaptation step, which adopts a two-stage extraction mode to reduce the sampling rate, and concretely comprises the steps that a first-stage extraction is realized by inputting a second digital signal through a first lower extraction module, the extraction sampling rate meets the bandwidth requirement of an IEC input signal, and then, a second-stage extraction is realized by a second lower extraction module on a low-pass filtering signal, and the reduction of the sampling rate meets the requirement of the upper limit of flicker frequency;
an effective value normalization step, namely, using the effective value output by the effective value calculation circuit as a normalization divisor factor to adjust the second digital signals with different amplitudes to be uniform to a reference level;
a digital gain adjustment step, namely grading the gain adjustment proportion, selecting a proper proportion by setting a digital gain register, reducing an input signal, avoiding overflow in subsequent fixed point circuit operation caused by overlarge voltage fluctuation, and automatically executing an amplification recovery function before outputting a flicker visibility detection result;
a DC offset acceleration step for eliminating a DC component contained in the output signal of the square demodulator and accelerating the convergence speed of a high-pass filter connected behind the DC offset acceleration step, specifically, adaptively subtracting a DC offset component from the output signal of the square demodulator;
a visual sensitivity coefficient normalization step for normalizing the measured visual sensitivity coefficient and outputting it, specifically, dividing the output signal of the low-pass filter before the frequency weighting filter by a constant normalization coefficient;
and a visibility gain compensation step for compensating for the filter gain attenuation of the visibility detection circuit prior to the instantaneous flicker visibility output, in particular by dividing the instantaneous flicker visibility signal output by the smoothing low-pass filter by a constant value, which is set by a register.
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