CN104535917B - Quick detection method for digital circuit failure - Google Patents
Quick detection method for digital circuit failure Download PDFInfo
- Publication number
- CN104535917B CN104535917B CN201410809369.7A CN201410809369A CN104535917B CN 104535917 B CN104535917 B CN 104535917B CN 201410809369 A CN201410809369 A CN 201410809369A CN 104535917 B CN104535917 B CN 104535917B
- Authority
- CN
- China
- Prior art keywords
- product term
- computing
- product
- variable
- boolean difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a quick detection method for a digital circuit failure. The quick detection method for the digital circuit failure proposes a boolean difference computing method based on a product term disjoint sharp-product operation, and achieves a difference operation for a logical function through introducing a 'bitwise XOR' operation between a product term and a difference mark and combining the product term disjoint sharp-product operation. The quick detection method for the digital circuit failure avoids the spread of a minterm of the logical function or a graph, and has the advantages that a very big digital integrated circuit can be processed and the operation speed is high, and a boolean difference order to be solved has little effect on the speed of the quick detection method for the digital circuit failure.
Description
Technical field
The present invention relates to a kind of fault detection method of circuit, especially relate to a kind of quick detection of digital circuit failure
Method.
Background technology
Digital circuit in the fabrication process in circuit some wires it may happen that connection error.Some lines can be regularly
It is connected to low level, some wires can regularly be connected to high level.After there is this incorrect link, the signal on these wires will
It is a fixed value, that is, unrelated with the input value of circuit, so that the logic function of circuit makes a mistake.Above-mentioned wire connects wrong
In by mistake, it is connected to the referred to as stuck at 0 fault of low level mistake, represented with s-a-0；It is connected to the referred to as solid of high level mistake
Fixed 1 fault, is represented with s-a-1.Because connection error occurs in the inside of circuit, therefore the method for detection is generally by electricity
Apply different input combinations outside road, and relatively more corresponding output whether there are above-mentioned 2 kinds of connection errors inside decision circuitry.
Wherein different input groups is collectively referred to as test vector.
In circuit as shown in Figure 1, line c is beating the local generation Miswire of " x ", then according to the theory of testing, when even
When line c occurs s-a-1 fault, corresponding test vector can be usedTo represent.Wherein, f corresponds to for Fig. 1 circuit
Logical function expression, Represent the first degree Boolean difference to input variable c for the f；T1For s-a-1's
Test vector set.T1Result of calculation beSo the collection of test vector
It is combined into { 0001,1-00, -100 }.In set of vectors, " 0 " represents logic low, and " 1 " represents logic high, and "-" represents can
Arbitrarily take " 0 " or " 1 ".In the same manner, when line c occurs s-a-0 fault, corresponding test vector can be usedCome
Represent.If additionally, there are Dual Failures, such as variable x in circuitiAnd xjGeneration s-a- α or s-a- β fault, wherein α, β ∈ (0,
1), represent s-a-0 or s-a-1 fault respectively.According to the theory of testing, test vector set can be expressed asX in formula1=x, For logical function f pair
Variable xiAnd xjSecond degree Boolean difference computing.From the expression formula of test vector set above it is seen that, the event of digital circuit
The Boolean difference computing of barrier detection process logical function corresponding with this circuit is closely related, and quickly realizes digital circuit pair to be measured
The Boolean difference computing of the logical function answered is a very important step in digital circuit detection.Wherein n variable logic letter
The k rank Boolean difference of number f is defined as：
From the point of view of the definition of the Boolean difference of logical function, the result of Boolean difference is the distance fortune between logical function
Calculate.The nonequivalence operation result of two logical functions has a feature, that is, the common portion of two functions will be excluded
Outward.The nonequivalence operation f g of such as logical function f and g can be expressed as (f-f ∩ g) ∪ (g-f ∩ g), wherein (f-f ∩ g)
Represent the common portion removing in f with g；And (g-f ∩ g) represents the common portion removing in g with f.And (f-f ∩ g) and
(g-f ∩ g) operation can be realized by the non-intersect sharp-product of logical function.
Because Boolean difference computing is a kind of basic operation of logic circuit fault detect, the speed of Boolean difference computing and
Treatable circuit size directly affects the size of the speed, complexity and treatable circuit of logic circuit fault detect.
Content of the invention
The technical problem to be solved is to provide a kind of method for quick of digital circuit failure, the method base
In the Boolean difference computational methods based on product term non-intersect sharp-product computing, the numeral that input variable is more than 30 can be processed
Circuit, and there is processing speed quickly.
The present invention solves the technical scheme that adopted of above-mentioned technical problem：A kind of quick detection side of digital circuit failure
Method is it is characterised in that defining the corresponding logical function of circuit under test is f；Circuit input variable number is defined as m, and output variable number is fixed
Justice is n；Define pi,pjFor belonging to any pair product term of f；Arbitrary variable in regulation product term, represents this variable with " 0 "
Occurred with contravariant form, " 1 " represents that this variable is occurred with commercial weight form, and "-" represents that this variable occurs without；Define [pi]kFor taking advantage of
Long-pending item piThe value of kth position；Define the Boolean difference operation token that H is f；H comprises m position；Define [H]kThe taking of kth position for H
Value, 0≤k≤(m-1)；Regulation [H]kValue be only " 1 " or " 0 "；[H]kRepresent that this bit variable needs boolean poor for " 1 "
Partite transport is calculated, [H]kRepresent that this bit variable does not need to carry out Boolean difference computing for " 0 "；Use Χk(pi, H) and represent product term piWith H
Between kth position " position XOR " computing, and specify as [H]kWhen=1,In the case of other, Χk(pi,H)
=[pi]k；DefinitionRepresent pi,pjBetween non-intersect sharp-product computing,Wherein " ∩ " represents
piWith pjLogic "and" operation；The present invention concretely comprises the following steps：
Step is 1.. define three empty set C1, C2And C3, and according to logical function f, the Boolean difference relation of variable is obtained
To Boolean difference mark H；
Step is 2.. and whether the logical expression judging f is the "or" form of multiple product terms, if it is not, f is expanded into
The "or" form of product term；The all product terms constituting f are stored simultaneously in set C respectively1, set C2With set C3In；
Step is 3.. in set C2In appoint take a product term p 'i, by p 'iCarry out " position XOR " computing by turn and H between, that is,
By p 'iKth place value [p 'i]kUse Χk(p′i, H) it is replaced, 0≤k≤(m-1)；
Step is 4.. judge set C2In whether all of product term all completes " position XOR " computing with Boolean difference mark H,
If it is, execution step is 5., otherwise execution step is 3.；
Step is 5.. in set C1In appoint take a product term, be designated as p "i, in set C2In appoint take a product term, be designated as
p″j, carry outComputing, operation result is stored in set C1In, and in set C1Middle deletion p "i；
Step is 6.. judge set C1In any product term whether with C2In any product term all non-intersect, if it is,
7., otherwise execution step is 5. for execution step；
Step is 7.. in set C2In appoint take a product term, be designated as p "v, in set C3In appoint take a product term, be designated as
p″w, and carry outComputing, operation result is stored in set C2In, and in set C2Middle deletion p "v；
Step is 8.. judge set C2In any product term whether with set C3In any product term all non-intersect, if
It is that 9., otherwise execution step is 7. for execution step；
Step is 9.：Will set C1With set C2Product term carry out logical "or" computing, the boolean just obtaining logic circuit is poor
Divide result；
Step is 10.：According to step 9. in the Boolean difference result that obtains, theoretical in conjunction with the circuit test based on Boolean difference,
Obtain corresponding test vector, realize the detection of circuit under test fault.
Compared with prior art, it is an advantage of the current invention that：(1) very big digital integrated electronic circuit can be processed, and
Arithmetic speed is quickly.(2) Boolean difference exponent number to be solved affects very little to the speed of the present invention.
In view of based in the circuit detecting method of Boolean difference, the speed of Boolean difference computing will directly affect test arrow
The generation of amount, and then affect the detection speed of circuit.Tables 1 and 2 is entered to Boolean difference arithmetic speed proposed by the present invention respectively
Go test.Test circuit in Tables 1 and 2 comes from MCNC test circuit.In table 1, the input variable number of circuit under test is maximum
For 199, be far longer than 30.In table 1, data is the first degree Boolean difference to the first input variable of circuit.In table 2, survey
Try the impact to arithmetic speed of the present invention for the Boolean difference exponent number.In table, "-" represents there is not this valency Boolean difference.From experiment knot
From the point of view of fruit, to same circuit, not the time needed for Boolean difference computing of same order almost there is no significant change.
Some experimental datas of table 1 the inventive method
The impact to arithmetic speed for the table 2 Boolean difference exponent number
| Circuit | i/o/p | Second order | Quadravalence | Eight ranks | 16 ranks |
| 5xp1 | 7/10/75 | <1 millisecond | <1 millisecond | - | - |
| alu4 | 14/8/1028 | 0.67 | 0.65 | 0.66 | - |
| apex6 | 135/99/657 | 2.11 | 2.09 | 2.09 | 2.12 |
| cm150a | 21/1/17 | <1 millisecond | <1 millisecond | <1 millisecond | <1 millisecond |
| cht | 47/36/120 | <1 millisecond | <1 millisecond | <1 millisecond | <1 millisecond |
| example2 | 85/66/369 | 0.16 | 0.16 | 0.17 | 0.16 |
| i7 | 199/67/302 | 0.45 | 0.46 | 0.48 | 0.45 |
| x3 | 135/99/739 | 1.65 | 1.66 | 1.65 | 1.61 |
Brief description
There is the logic circuit schematic diagram of stuck-at fault for line c in Fig. 1.
Specific embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
Embodiment：
In the present embodiment, detected with the method for the present invention with circuit as shown in Figure 1.Numeral now to be tested
The corresponding logical function of circuit isCorresponding circuit is as shown in figure 1, line c fault type is s-a-1.
Then test vector can be expressed asSolved with the method for the present invention nowAnd produce corresponding test arrow
Amount.
Step is 1.. define three empty set C1, C2And C3, and according to logical function f, the Boolean difference relation of variable is obtained
It is H=(abcd)=(0010) to Boolean difference mark H；
Step is 2.. f is expanded into the "or" form of product term, the product term obtaining after launching is stored simultaneously in collection respectively
Close C1, set C2With set C3In；In this example, after f expands into the "or" of product term, set C1, set C2With set C3Storage
Product term be (ac, bc,)；With " 0 ", " 1 " and "-" representing the every variable-value situation of above-mentioned 3 product terms, then
Set C1, set C2With set C3The content of storage is (1-1-, -11-, -- 01)；
Step is 3.. in set C2In appoint and take a product term it is assumed that being (1-1-), then " the position of (1-1-) and H=(0010)
XOR " operation result is (1-0-)；
Step is 4.. repeat step 3., finally set C2Middle product term is changed into (1-0-, -10-, -- 11), and execution step is 5.；
Step is 5.. in set C1In appoint take a product term it is assumed that be (1-1-), in set C2In appoint take a product term,
It is assumed to be (1-0-), and carry outComputing；Because (1-1-) is non-intersect with (1-0-), soSet C therefore after computing1Middle content keeps constant；
Step is 6.. check set C1Middle product term and set C2In product term intersect situation, and repeat step is 5.；Assume
Set C1In the product term that takes remain as (1-1-), set C2In the product term that takes be (- 10-), (1-1-) right not phase with (- 10-)
Hand over；After this non-intersect computing of two product terms, set C1Middle content continues to keep constant；Repeat step is 5. it is assumed that set C again1
In the product term that takes be still (1-1-), C2In the product term that takes be (-- 11)；By (1-
10) store set C1, by (1-1-) from set C1Middle deletion, obtains set C1=(1-10, -11-, -- 01)；Constantly repeat to walk
Suddenly 5., finally give set C1=(1-10, -110,0001)；Now set C1In there is no product term and set C2In take advantage of
Long-pending item intersects, and execution step is 7.；
Step is 7.. in set C2In appoint take a product term it is assumed that be (1-0-), in set C3In appoint take a product term,
It is assumed to be (1-1-), the two is non-intersect, so set C2Keep constant；
Step is 8.. check set C2There is product term and set C3In product term intersect situation, repeat step is 7.；Assume
Set C2The product term taking remains as (1-0-), set C3In the product term that takes be (- 11-), the two is non-intersect, this two products
After the non-intersect computing of item, set C2Middle content continues to keep constant；Repeat step is 7. it is assumed that set C again2In the product term that takes
It is still (1-1-), set C3In the product term that takes be (-- 01)；(1-00) is stored in
Set C2In, and by (1-1-) from set C2Middle deletion, obtains set C2=(1-00, -10-, -- 11)；Constantly repeat step 7.,
Finally give set C2=(1-00, -100,0011), execution step is 9.；
Step is 9.. and will set C1With set C2Middle product term carries out logical "or" computing, obtains corresponding product term expression formula
ForHere it is functionResult.
Step 10. thus obtains and logical functionCorresponding circuit is in s-a-1 situation in line c
Under test vector table below can be had to reach formula calculated：
I.e. the collection of test vector is combined into { 0001,1-00, -100 }.By any one vector in the set of test vector, false
It is set to (0001), as the input variable of Fig. 1 circuit, because line c is in s-a-1 state, obtain circuit and be output as " 0 ",
And logical functionCorresponding result is " 1 ", according to the theory of testing it is known that line c breaks down.
From the example above as can be seen that whole calculating process is without the expansion carrying out minterm, and due to set C2
In product term be by set C1In some positions of product term negate and obtain, this makes set C1With set C2Middle many is taken advantage of
Long-pending item is all non-intersect so that the operation times of non-intersect sharp-product between product term greatly reduce, and has further speeded up boolean's difference
The calculating process dividing is so that method proposed by the present invention has very high efficiency.In addition, in upper example, if Boolean difference mark
Contains only in will H one " 1 ", represent and realize first degree Boolean difference；When containing k " 1 " in H it is possible to realize k rank cloth
That difference, therefore, the exponent number of Boolean difference is little on the arithmetic speed impact of the method proposing in the present invention.
Claims (1)
1. a kind of method for quick of digital circuit failure is it is characterised in that defining the corresponding logical function of circuit under test is f；
Circuit input variable number is defined as m, and output variable number is defined as n；Define pi,pjFor belonging to any pair product term of f；Regulation
With " 0 ", arbitrary variable in product term, represents that this variable is occurred with contravariant form, " 1 " represents that this variable is gone out with commercial weight form
Existing, "-" represents that this variable occurs without；Define [pi]kFor product term piThe value of kth position；Define the Boolean difference computing mark that H is f
Will；H comprises m position；Define [H]kThe value of the kth position for H, 0≤k≤(m-1)；Regulation [H]kValue be only " 1 " or
“0”；[H]kRepresent product term p for " 1 "iThe variable of kth position needs Boolean difference computing, [H]kRepresent product term p for " 0 "iKth
The variable of position does not need to carry out Boolean difference computing；Use Χk(pi, H) and represent product term piKth position " position XOR " fortune and H between
Calculate, and specify as [H]kWhen=1,In the case of other, Χk(pi, H) and=[pi]k；DefinitionRepresent
pi,pjBetween non-intersect sharp-product computing,Wherein " ∩ " represents piWith pjLogic "and" operation；
The present invention concretely comprises the following steps：
Step is 1.. define three empty set C1, C2And C3, and cloth is obtained to the Boolean difference relation of variable according to logical function f
You are difference mark H；
Step is 2.. and whether the logical expression judging f is the "or" form of multiple product terms, if it is not, f is expanded into product
The "or" form of item；The all product terms constituting f are stored simultaneously in set C respectively1, set C2With set C3In；
Step is 3.. in set C2In appoint take a product term p 'i, by p 'iCarry out " position XOR " computing by turn and H between, will p 'i
Kth place value [p 'i]kUse Χk(p′i, H) it is replaced, 0≤k≤(m-1)；
Step is 4.. judge set C2In whether all of product term all completes " position XOR " computing with Boolean difference mark H, if
It is that 5., otherwise execution step is 3. for execution step；
Step is 5.. in set C1In appoint take a product term, be designated as pi", in set C2In appoint take a product term, be designated as p "j, enter
OKComputing, operation result is stored in set C1In, and in set C1Middle deletion p "i；
Step is 6.. judge set C1In any product term whether with C2In any product term all non-intersect, if it is, execution
7., otherwise execution step is 5. for step；
Step is 7.. in set C2In appoint take a product term, be designated as p "v, in set C3In appoint take a product term, be designated as p "w, and
Carry outComputing, operation result is stored in set C2In, and in set C2Middle deletion p "v；
Step is 8.. judge set C2In any product term whether with set C3In any product term all non-intersect, if it is,
9., otherwise execution step is 7. for execution step；
Step is 9.：Will set C1With set C2Product term carry out logical "or" computing, just obtain logic circuit Boolean difference knot
Really；
Step is 10.：According to step 9. in the Boolean difference result that obtains, theoretical in conjunction with the circuit test based on Boolean difference, obtain
Corresponding test vector, realizes the detection of circuit under test fault.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410809369.7A CN104535917B (en) | 2014-12-23 | 2014-12-23 | Quick detection method for digital circuit failure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410809369.7A CN104535917B (en) | 2014-12-23 | 2014-12-23 | Quick detection method for digital circuit failure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104535917A CN104535917A (en) | 2015-04-22 |
| CN104535917B true CN104535917B (en) | 2017-02-22 |
Family
ID=52851479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410809369.7A Active CN104535917B (en) | 2014-12-23 | 2014-12-23 | Quick detection method for digital circuit failure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104535917B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106959413B (en) * | 2017-01-18 | 2019-04-16 | 宁波大学 | The detection method that wired AND is shorted failure occurs for digital combined logic circuit output |
| CN106960072B (en) * | 2017-01-18 | 2019-08-06 | 宁波大学 | The detection method that wired OR is shorted failure occurs for digital combined logic circuit output |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DD241317A1 (en) * | 1985-09-26 | 1986-12-03 | Mittweida Ing Hochschule | SEQUENTIAL CIRCUIT ARRANGEMENT WITH INTEGRATED FAULT RECOGNITION |
| CN101488745A (en) * | 2009-03-02 | 2009-07-22 | 宁波大学 | Method for reducing area of digital logic circuit |
| CN101614788A (en) * | 2009-07-17 | 2009-12-30 | 中国人民解放军63908部队 | A kind of method of testing of automatically generated vectors of digital circuit board |
| CN102156772A (en) * | 2011-02-21 | 2011-08-17 | 大连海事大学 | Logic-compatibility-based digital circuit fault diagnosis method and system |
| CN102435938A (en) * | 2011-10-28 | 2012-05-02 | 中国电子科技集团公司第三十八研究所 | Function-based digital circuit failure detecting and positioning system and method |
| CN103236837A (en) * | 2013-04-08 | 2013-08-07 | 宁波大学 | Sub-circuit extracting method of digital logic circuit |
| CN103926527A (en) * | 2014-04-28 | 2014-07-16 | 国网宁夏电力公司宁东供电公司 | Digital circuit board self-diagnosis system and method based on feature compression technique |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4977045B2 (en) * | 2008-01-16 | 2012-07-18 | 株式会社東芝 | Semiconductor integrated circuit and semiconductor device |
-
2014
- 2014-12-23 CN CN201410809369.7A patent/CN104535917B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DD241317A1 (en) * | 1985-09-26 | 1986-12-03 | Mittweida Ing Hochschule | SEQUENTIAL CIRCUIT ARRANGEMENT WITH INTEGRATED FAULT RECOGNITION |
| CN101488745A (en) * | 2009-03-02 | 2009-07-22 | 宁波大学 | Method for reducing area of digital logic circuit |
| CN101614788A (en) * | 2009-07-17 | 2009-12-30 | 中国人民解放军63908部队 | A kind of method of testing of automatically generated vectors of digital circuit board |
| CN102156772A (en) * | 2011-02-21 | 2011-08-17 | 大连海事大学 | Logic-compatibility-based digital circuit fault diagnosis method and system |
| CN102435938A (en) * | 2011-10-28 | 2012-05-02 | 中国电子科技集团公司第三十八研究所 | Function-based digital circuit failure detecting and positioning system and method |
| CN103236837A (en) * | 2013-04-08 | 2013-08-07 | 宁波大学 | Sub-circuit extracting method of digital logic circuit |
| CN103926527A (en) * | 2014-04-28 | 2014-07-16 | 国网宁夏电力公司宁东供电公司 | Digital circuit board self-diagnosis system and method based on feature compression technique |
Non-Patent Citations (3)
| Title |
|---|
| Logic Detection Algorithm for Dual Logic Implementations Based on Majority Cubes;Wang Lunyao,et al;《2010 International Conference on Computer Application and System Modeling》;20101024;第503-507页 * |
| 数字电路故障诊断;周继承等;《应用科技》;20080229;第35卷(第2期);第29-32页 * |
| 逻辑函数的双逻辑综合与优化;王伦耀等;《计算机辅助设计与图形学学报》;20120731;第24卷(第7期);第961-967页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104535917A (en) | 2015-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102104970B1 (en) | Error-tolerant syndrome extraction and decoding in bacon-shore quantum error correction | |
| US10002060B2 (en) | Matrix circuit detecting failure location in common signal | |
| JP6468247B2 (en) | Ising device and control method of Ising device | |
| US20180018147A1 (en) | Random number expanding device, random number expanding method, and non-transitory computer readable recording medium storing random number expanding program | |
| Zheng et al. | Diagnosability of star graphs under the comparison diagnosis model | |
| RU2011129298A (en) | IDENTIFICATION OF FAILURES IN THE AIRCRAFT ENGINE | |
| Blyudov et al. | Properties of code with summation for logical circuit test organization | |
| CN104535917B (en) | Quick detection method for digital circuit failure | |
| Pomeranz | OBO: An output-by-output scoring algorithm for fault diagnosis | |
| CN106601643B (en) | Measurement method, the device and system of the MOS process corner of chip | |
| US9411014B2 (en) | Reordering or removal of test patterns for detecting faults in integrated circuit | |
| Matrosova et al. | Generating all test patterns for stuck-at faults at a gate pole and their connection with the incompletely specified Boolean function of the corresponding subcircuit | |
| Alawieh et al. | Identifying systematic spatial failure patterns through wafer clustering | |
| Wu et al. | Reducing scan-shift power through scan partitioning and test vector reordering | |
| CN103258079A (en) | Equivalent function test method for digital combined logic circuits | |
| CN114529001A (en) | Index evaluation method and device of quantum algorithm, terminal and storage medium | |
| Matrosova et al. | PDFs testing of combinational circuits based on covering ROBDDs | |
| CN103926527A (en) | Digital circuit board self-diagnosis system and method based on feature compression technique | |
| Wu et al. | Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization | |
| Matrosova et al. | Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits | |
| CN107403028A (en) | The VLSI array reconfiguration methods of trouble point driving | |
| Hakem et al. | A parameter-free method for sensor fault detection and isolation in bilinear systems | |
| Pomeranz et al. | Gradual diagnostic test generation based on the structural distance between indistinguished fault pairs | |
| Yoshimura et al. | A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT | |
| CN106959413B (en) | The detection method that wired AND is shorted failure occurs for digital combined logic circuit output |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |