CN104535917A - Quick detection method for digital circuit failure - Google Patents

Abstract

The invention discloses a quick detection method for a digital circuit failure. The quick detection method for the digital circuit failure proposes a boolean difference computing method based on a product term disjoint sharp-product operation, and achieves a difference operation for a logical function through introducing a 'bitwise XOR' operation between a product term and a difference mark and combining the product term disjoint sharp-product operation. The quick detection method for the digital circuit failure avoids the spread of a minterm of the logical function or a graph, and has the advantages that a very big digital integrated circuit can be processed and the operation speed is high, and a boolean difference order to be solved has little effect on the speed of the quick detection method for the digital circuit failure.

Description

A kind of method for quick of digital circuit failure

Technical field

The present invention relates to a kind of fault detection method of circuit, especially relate to a kind of method for quick of digital circuit failure.

Background technology

Digital circuit in the fabrication process in circuit some wire may there is connection error.Some line can receive low level regularly, and some wire can receive high level regularly.After there is this incorrect link, the signal on these wires will be a fixed value, namely have nothing to do with the input value of circuit, thus the logic function of circuit is made a mistake.In above-mentioned wire connection error, that receives low level mistake is called stuck at 0 fault, represents with s-a-0; That receives high level mistake is called stuck at 1 fault, represents with s-a-1.Because connection error occurs in the inside of circuit, the method therefore detected is generally by applying different input combination outward at circuit, and more corresponding output comes decision circuitry inside whether there are above-mentioned 2 kinds of connection errors.Wherein different input combinations is called test vector.

In circuit as shown in Figure 1, there is Miswire in the place that line c is beating " x ", then according to the theory of testing, when s-a-1 fault occurs line c, corresponding test vector can be used represent.Wherein, f is the logical function expression that Fig. 1 circuit is corresponding, represent that f is to the first degree Boolean difference of input variable c; T ₁for the test vector set of s-a-1.T ₁result of calculation be so the set of test vector is { 0001,1-00 ,-100}.In set of vectors, " 0 " presentation logic low level, " 1 " presentation logic high level, "-" expression can be got arbitrarily " 0 " or " 1 ".In like manner, when s-a-0 fault occurs line c, corresponding test vector can be used represent.In addition, if there is Dual Failures in circuit, as variable x _iand x _jthere is s-a-α or s-a-β fault, wherein α, β ∈ (0,1), represent s-a-0 or s-a-1 fault respectively.According to the theory of testing, test vector set can be expressed as $T=\{{\stackrel{\‾}{x}}_i^{\mathrm{\α}}{x}_j^{\mathrm{\β}}\frac{\mathrm{df}}{{\mathrm{dx}}_i}+x_i^{\mathrm{\α}}{\stackrel{\‾}{x}}_j^{\mathrm{\β}}\frac{\mathrm{df}}{{\mathrm{dx}}_j}+{\stackrel{\‾}{x}}_i^{\mathrm{\α}}{\stackrel{\‾}{x}}_j^{\mathrm{\β}}\frac{d^{2}f}{d(x_i,x_j)}=1\},$ X in formula ¹=x, for logical function f is to variable x _iand x _jsecond degree Boolean difference computing.Be not difficult to find from the expression formula of test vector set above, the Boolean difference computing of the logical function that the process fault detection of digital circuit is corresponding with this circuit is closely related, and the Boolean difference computing realizing logical function corresponding to digital circuit to be measured is fast a very important step during digital circuit detects.Wherein the k rank Boolean difference of n variable logical function f is defined as:

$\frac{d^{k}f}{d(x_{i1},x_{i2},...{,x}_{\mathrm{ik}})}f(x_1,x_2,...,x_{i1},x_{i2},...,x_{\mathrm{ik}},...{,x}_n)\⊕f(x_1,x_2,...,\stackrel{\‾}{x_{i1}},\stackrel{\‾}{x_{i2}},...,\stackrel{\‾}{x_{\mathrm{ik}}},...,x_n);$

From the definition of the Boolean difference of logical function, the result of Boolean difference is the nonequivalence operation between logical function.The nonequivalence operation result of two logical functions has a feature, and that is exactly that the public part of two functions will be left out.The nonequivalence operation f ⊕ g of such as logical function f and g can be expressed as (f-f ∩ g) ∪ (g-f ∩ g), and wherein (f-f ∩ g) represents the public part of removing and g in f; And (g-f ∩ g) represents the public part of removing and f in g.And (f-f ∩ g) and (g-f ∩ g) operation can realize by the non-intersect sharp-product of logical function.

Due to a kind of basic operation that Boolean difference computing is logical circuit fault detect, the speed of Boolean difference computing and treatable circuit size directly affect the size of the speed of logical circuit fault detect, complexity and treatable circuit.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of method for quick of digital circuit failure, the method is based on the Boolean difference computing method based on the non-intersect sharp-product computing of product term, the digital circuit that input variable is greater than 30 can be processed, and there is very fast processing speed.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of method for quick of digital circuit failure, it is characterized in that the logical function defining circuit under test corresponding is f; Circuit input variable number is defined as m, and output variable number is defined as n; Definition p _i, p _jfor belonging to any pair product term of f; With " 0 ", arbitrary variable in regulation product term, represents that this variable occurs with contravariant form, " 1 " represents that this variable occurs with commercial weight form, and "-" represents that this variable does not occur; Definition [p _i] _kfor product term p _ithe value of kth position; Definition H is the Boolean difference operation token of f; H comprises m position; Definition [H] _kfor the value of the kth position of H, 0≤k≤(m-1); Regulation [H] _kvalue can only be " 1 " or " 0 "; [H] _kfor " 1 " represents that this bit variable needs Boolean difference computing, [H] _kfor " 0 " represents that this bit variable does not need to carry out Boolean difference computing; Use Χ _k(p _i, H) and represent product term p _iand kth position " position XOR " computing between H, and regulation is as [H] _kwhen=1, in other situations, Χ _k(p _i, H) and=[p _i] _k; Definition represent p _i, p _jbetween non-intersect sharp-product computing, wherein " ∩ " represents p _iwith p _jlogic "and" operation; Concrete steps of the present invention are:

Step is 1.. define three empty set C ₁, C ₂and C ₃, and obtain Boolean difference mark H according to the Boolean difference relation of logical function f to variable;

Step is 2.. judge that whether the logical expression of f is the "or" form of multiple product term, if not, f is expanded into the "or" form of product term; The all product terms forming f are stored in respectively simultaneously set C ₁, set C ₂with set C ₃in;

Step is 3.. at set C ₂in appoint get a product term p ' _i, by p ' _iand carry out " position XOR " computing between H by turn, by p ' _ikth place value [p ' _i] _kuse Χ _k(p ' _i, H) replace, 0≤k≤(m-1);

Step is 4.. judge set C ₂in whether all product terms all complete " position XOR " computing with Boolean difference mark H, if so, perform step 5., otherwise perform step 3.;

Step is 5.. at set C ₁in appoint get a product term, be designated as p " _i, at set C ₂in appoint get a product term, be designated as p " _j, carry out computing, operation result is stored in set C ₁in, and at set C ₁middle deletion p " _i;

Step is 6.. judge set C ₁in any product term whether with C ₂in any product term all non-intersect, if so, perform step 7., otherwise perform step 5.;

Step is 7.. at set C ₂in appoint get a product term, be designated as p " _v, at set C ₃in appoint get a product term, be designated as p " _w, and carry out computing, operation result is stored in set C ₂in, and at set C ₂middle deletion p " _v;

Step is 8.. judge set C ₂in any product term whether with set C ₃in any product term all non-intersect, if so, perform step 9., otherwise perform step 7.;

Step is 9.: will gather C ₁with set C ₂product term carry out logical "or" computing, just obtain the Boolean difference result of logical circuit;

Step is 10.: according to step 9. in the Boolean difference result that obtains, theoretical in conjunction with the circuit test based on Boolean difference, obtain corresponding test vector, realize the detection of circuit under test fault.

Compared with prior art, the invention has the advantages that: (1) can process very large digital integrated circuit, and arithmetic speed is very fast.(2) Boolean difference exponent number to be solved is very little to rate of the present invention.

Consider in the circuit detecting method based on Boolean difference, the speed of Boolean difference computing will directly affect the generation of test vector, and then affects the detection speed of circuit.Table 1 and table 2 are tested the Boolean difference arithmetic speed that the present invention proposes respectively.Test circuit in table 1 and table 2 comes from MCNC test circuit.What in table 1, the input variable number of circuit under test was maximum is 199, is far longer than 30.In table 1, data are the first degree Boolean difference to the first input variable of circuit.In table 2, test the impact of Boolean difference exponent number on arithmetic speed of the present invention.In table, "-" represents there is not this valency Boolean difference.From experimental result, to same circuit, the time needed for Boolean difference computing of same order does not almost have significant change.

Some experimental datas of table 1 the inventive method

Table 2 Boolean difference exponent number is on the impact of arithmetic speed

Circuit	i/o/p	Second order	Quadravalence	Eight rank	16 rank
						5xp1	7/10/75	< 1 millisecond	< 1 millisecond	-	-
alu4	14/8/1028	0.67	0.65	0.66	-
						apex6	135/99/657	2.11	2.09	2.09	2.12
cm150a	21/1/17	< 1 millisecond	< 1 millisecond	< 1 millisecond	< 1 millisecond
						cht	47/36/120	< 1 millisecond	< 1 millisecond	< 1 millisecond	< 1 millisecond
example2	85/66/369	0.16	0.16	0.17	0.16
						i7	199/67/302	0.45	0.46	0.48	0.45
x3	135/99/739	1.65	1.66	1.65	1.61

Accompanying drawing explanation

Fig. 1 is the logical circuit schematic diagram that stuck-at fault occurs line c.

Embodiment

Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.

Embodiment:

In the present embodiment, detect by method of the present invention with circuit as shown in Figure 1.Logical function corresponding to digital circuit now to be tested is as shown in Figure 1, line c fault type is s-a-1 to corresponding circuit.Then test vector can be expressed as solve by method of the present invention now and produce corresponding test vector.

Step is 1.. define three empty set C ₁, C ₂and C ₃, and to obtain Boolean difference mark H according to the Boolean difference relation of logical function f to variable be H=(abcd)=(0010);

Step is 2.. and f is expanded into the "or" form of product term, the product term obtained is stored in respectively set C after expansion simultaneously ₁, set C ₂with set C ₃in; In this example, after f expands into the "or" of product term, set C ₁, set C ₂with set C ₃the product term stored is (ac, bc, ); With " 0 ", " 1 " and "-" represents the every variable-value situation of above-mentioned 3 product terms, then gather C ₁, set C ₂with set C ₃the content stored is (1-1-,-11-,--01);

Step is 3.. at set C ₂in appoint and get a product term, be assumed to be (1-1-), then " position XOR " operation result of (1-1-) and H=(0010) is (1-0-);

Step is 4.. and repeat step 3., finally gather C ₂middle product term becomes (1-0-,-10-,--11), perform step 5.;

Step is 5.. at set C ₁in appoint get a product term, be assumed to be (1-1-), set C ₂in appoint get a product term, be assumed to be (1-0-), and carry out computing; Because (1-1-) and (1-0-) are non-intersect, so therefore C is gathered after computing ₁middle content remains unchanged;

Step is 6.. check set C ₁middle product term and set C ₂in product term intersect situation, and repeat step 5.; Assumption set C ₁in the product term got still be (1-1-), set C ₂in the product term got be (-10-), (1-1-) and (-10-) are so non-intersect; After these two non-intersect computings of product term, set C ₁middle content continues to remain unchanged; Again repeat step 5., Assumption set C ₁in the product term got be still (1-1-), C ₂in the product term got be (--11); (1-10) is stored into set C ₁, by (1-1-) from set C ₁middle deletion, obtains gathering C ₁=(1-10 ,-11-,--01); 5. continuous repetition step, finally obtains gathering C ₁=(1-10 ,-110,0001); Now gather C ₁in do not had product term with set C ₂in product term intersect, perform step 7.;

Step is 7.. at set C ₂in appoint get a product term, be assumed to be (1-0-), set C ₃in appoint get a product term, be assumed to be (1-1-), the two is non-intersect, thus set C ₂remain unchanged;

Step is 8.. check set C ₂there is product term and set C ₃in product term intersect situation, repeat step 7.; Assumption set C ₂the product term got still is (1-0-), set C ₃in the product term got be (-11-), the two is non-intersect, after these two non-intersect computings of product term, set C ₂middle content continues to remain unchanged; Again repeat step 7., Assumption set C ₂in the product term got be still (1-1-), set C ₃in the product term got be (--01); (1-00) is stored in set C ₂in, and by (1-1-) from set C ₂middle deletion, obtains gathering C ₂=(1-00 ,-10-,--11); 7. continuous repetition step, finally obtains gathering C ₂9.=(1-00 ,-100,0011), perform step;

Step is 9.. will C be gathered ₁with set C ₂middle product term carries out logical "or" computing, obtains corresponding product term expression formula to be here it is function result.

Step 10. obtains and logical function thus the corresponding expression formula of circuit below the test vector that line c is in s-a-1 situation can have calculates:

$T_1=\{\stackrel{\‾}{c}\frac{\mathrm{df}}{\mathrm{dc}}=1\}=\{\stackrel{\‾}{c}(\mathrm{ac}\stackrel{\‾}{d}+\mathrm{bc}\stackrel{\‾}{d}+\stackrel{\‾}{a}\stackrel{\‾}{b}\stackrel{\‾}{c}d+a\stackrel{\‾}{c}\stackrel{\‾}{d}+b\stackrel{\‾}{c}\stackrel{\‾}{d}+\stackrel{\‾}{a}\stackrel{\‾}{b}\mathrm{cd})=1\}=\{\stackrel{\‾}{a}\stackrel{\‾}{b}\stackrel{\‾}{c}d+a\stackrel{\‾}{c}\stackrel{\‾}{d}+b\stackrel{\‾}{c}\stackrel{\‾}{d}=1\};$

Namely the set of test vector is { 0001,1-00 ,-100}.By any one vector in the set of test vector, be assumed to be (0001), as the input variable of Fig. 1 circuit, because line c is in s-a-1 state, obtain the output of circuit for " 0 ", and logical function corresponding result is " 1 ", and according to the theory of testing, known line c breaks down.

As can be seen from example above, whole computation process need not carry out the expansion of minterm, and due to set C ₂in product term be by set C ₁in some negate of product term obtain, this makes to gather C ₁with set C ₂in many product terms all non-intersect, the operation times of the non-intersect sharp-product between product term is greatly reduced, and accelerate the calculating process of Boolean difference further, the method that the present invention is proposed has very high efficiency.In addition, in upper example, if contains only one " 1 " in Boolean difference mark H, represent and realize first degree Boolean difference; When containing k " 1 " in H, just can realize k rank Boolean difference, therefore, the arithmetic speed impact of exponent number on the method proposed in the present invention of Boolean difference is little.

Claims (1)

1. a method for quick for digital circuit failure, is characterized in that the logical function defining circuit under test corresponding is f; Circuit input variable number is defined as m, and output variable number is defined as n; Definition p _i, p _jfor belonging to any pair product term of f; With " 0 ", arbitrary variable in regulation product term, represents that this variable occurs with contravariant form, " 1 " represents that this variable occurs with commercial weight form, and "-" represents that this variable does not occur; Definition [p _i] _kfor product term p _ithe value of kth position; Definition H is the Boolean difference operation token of f; H comprises m position; Definition [H] _kfor the value of the kth position of H, 0≤k≤(m-1); Regulation [H] _kvalue can only be " 1 " or " 0 "; [H] _kfor " 1 " represents that this bit variable needs Boolean difference computing, [H] _kfor " 0 " represents that this bit variable does not need to carry out Boolean difference computing; Use Χ _k(p _i, H) and represent product term p _iand kth position " position XOR " computing between H, and regulation is as [H] _kwhen=1, in other situations, Χ _k(p _i, H) and=[p _i] _k; Definition represent p _i, p _jbetween non-intersect sharp-product computing, wherein " ∩ " represents p _iwith p _jlogic "and" operation; Concrete steps of the present invention are:

Step is 1.. define three empty set C ₁, C ₂and C ₃, and obtain Boolean difference mark H according to the Boolean difference relation of logical function f to variable;

Step is 2.. judge that whether the logical expression of f is the "or" form of multiple product term, if not, f is expanded into the "or" form of product term; The all product terms forming f are stored in respectively simultaneously set C ₁, set C ₂with set C ₃in;

Step is 3.. at set C ₂in appoint get a product term p ' _i, by p ' _iand carry out " position XOR " computing between H by turn, by p ' _ikth place value [p ' _i] _kuse Χ _k(p ' _i, H) replace, 0≤k≤(m-1);

Step is 4.. judge set C ₂in whether all product terms all complete " position XOR " computing with Boolean difference mark H, if so, perform step 5., otherwise perform step 3.;

Step is 5.. at set C ₁in appoint get a product term, be designated as p _i", at set C ₂in appoint get a product term, be designated as p " _j, carry out " computing, operation result is stored in set C ₁in, and at set C ₁middle deletion p " _i;

Step is 6.. judge set C ₁in any product term whether with C ₂in any product term all non-intersect, if so, perform step 7., otherwise perform step 5.;

Step is 7.. at set C ₂in appoint get a product term, be designated as p " _v, at set C ₃in appoint get a product term, be designated as p " _w, and carry out computing, operation result is stored in set C ₂in, and at set C ₂middle deletion p " _v;

Step is 8.. judge set C ₂in any product term whether with set C ₃in any product term all non-intersect, if so, perform step 9., otherwise perform step 7.;

Step is 9.: will gather C ₁with set C ₂product term carry out logical "or" computing, just obtain the Boolean difference result of logical circuit;

Step is 10.: according to step 9. in the Boolean difference result that obtains, theoretical in conjunction with the circuit test based on Boolean difference, obtain corresponding test vector, realize the detection of circuit under test fault.