CN104506191B - The correcting circuit of production line analog-digital converter based on Zero-cross comparator and bearing calibration - Google Patents
The correcting circuit of production line analog-digital converter based on Zero-cross comparator and bearing calibration Download PDFInfo
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- CN104506191B CN104506191B CN201410754786.6A CN201410754786A CN104506191B CN 104506191 B CN104506191 B CN 104506191B CN 201410754786 A CN201410754786 A CN 201410754786A CN 104506191 B CN104506191 B CN 104506191B
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Abstract
The invention belongs to technical field of integrated circuits, and in particular to the correcting circuit of the production line analog-digital converter based on Zero-cross comparator and bearing calibration.Correcting circuit provided by the invention is connected between the two-stage circuit of the production line analog-digital converter based on Zero-cross comparator, and the correcting circuit includes a difference 1/f error amplifiers, two correction electric capacity, two transmission gate circuits；Each transmission gate circuit includes a n type field effect transistor and a p type field effect transistor, both raceway groove parallel arrangements.The error of previous stage circuit is amplified and is stored on correction electric capacity by correcting circuit, and the error then is established into process compensation to its output with rear stage circuit.Bearing calibration provided by the invention, the conversion accuracy of circuit can be effectively improved, while the conversion time longer than traditional scheme is provided for sub- ADC, therefore the rate request to sub- adc circuit can be reduced.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of production line analog-digital converter correcting circuit and correction
Method.
Background technology
It is a kind of popular scheme for realizing production line analog-digital converter in recent years based on Zero-cross comparator, its adjacent two-stage differential
Circuit is as shown in Figure 1.Similar to traditional switch electric capacity gain stage, the differential switched capacitor gain stage based on Zero-cross comparator is with single-ended
The expense that twice of circuit realizes the processing to differential signal.The upper and lower symmetrical circuit structure of two parts forms positive and negative two and led to
Road, handles the positive input and negative input of differential input signal respectively, and draws final difference output result.Fig. 1 mainly includes
The sampling capacitance C of N levels circuit 1011±And C2±103 ~ 106, the sampling capacitance C of N+1 levels circuit 1023±And C4±107 ~ 110,
The sampling switch M of N levels circuit 1011111, the sampling switch M of N+1 levels circuit 1024112, the positive passage of N levels circuit 101
Preset transistor M2113, the negative channel presetting transistor M of N levels circuit 1013114, the current source I matched up and down1±、I2±115
~ 118 and I3±、I4±119 ~ 122, and middle difference zero-crossing comparator 100.Circuit is by current source to output node charge and discharge
Electricity realizes the inswept whole output area of output voltage, and difference zero-crossing comparator 100 realizes the function of detection " empty short " state.
The course of work of foregoing circuit is as follows.Work as φ1During in high potential, N levels circuit 101 is in sample phase, opens
Close φ1Closure, switch φ2Disconnect, Differential Input is sampled to the sampling capacitance C in N levels circuit 1011±And C2±103~106
On.Work as φ2During in high potential, N levels circuit 101 enters charge transfer phase, and N+1 levels circuit 102 enters sample phase,
Sampling capacitance C in N+1 levels circuit 1023±And C4±107 ~ 110 load capacitance as N levels circuit 101, sample N levels
The output V of circuit 101o±.Enter the beginning of charge transfer phase in N levels circuit 101, have a bit of preset stage φ2I。
In preset stage, the sampling capacitance C of N+1 levels circuit 1023±And C4±107 ~ 110 medial node can be connected to common mode electricity
Flat, the positive output node of N level circuits can be by positive channel presetting transistor M2113 discharge into system potential minimum, N level circuits
Negative output node can be by negative channel presetting transistor M3114 are charged to supply voltage, thus achieve to N+1 level circuits
The initialization of 102 sampling capacitance 107 ~ 110.After preset stage terminates, φ2IJump to low potential, respective transistor 113,114
It is turned off.The current source I being made up of pMOS pipes3±119th, 121 will charge to the positive output node of N level circuits, by nMOS pipe structures
Into current source I4±120th, 122 by the negative output node discharge of N level circuits.In the ideal case, upper and lower Current-source matching
And charging and discharging currents are constant, the equivalent capacity on output node to ground is also fixed, therefore positive output node voltage will be with constant rate of speed
Rise, negative output node voltage will be declined with constant rate of speed.By M4112 sampling switch as differential signal.Notice in electricity
Discharge and recharge is flowed during this, M4112 will be held on, and to connect sampling capacitance 107 ~ 110 up and down, carry charging and discharging currents.
Electric capacity C in upper and lower two parts circuit1And C2103 and 105,104 and 106 each form capacitive divider, zero-crossing comparator 100
The voltage V of two input nodesX+And VX-Will be respectively with its output node voltage Vo+And Vo-Change.Until zero-crossing comparator 100 is defeated
Ingress reaches " empty short " state, i.e. VX+=VX-, the output of zero-crossing comparator 100 redirects, M4112 shut-offs, upper down-sampling electricity
The path held between 107 ~ 110 disconnects, sampling capacitance C3±And C4±The quantity of electric charge on 107 ~ 110 just immobilizes.This moment is true
The end of the sampling process of N+1 levels circuit 102 is determined.Work as φ1After returning to low potential, a work period of circuit just terminates
.
It can be seen from the course of work of foregoing circuit, when zero-crossing comparator 100 can not be jumped in zero-acrross ing moment exactly
When turning, circuit will have transformed error.This error and the transformed error of stage circuit in conventional pipeline analog-digital converter
It is similar.With Δ VoThe transformed error of output is represented, with Δ VXRepresent zero-crossing comparator input summing junction X±Remainder error, then
Following relationship delta V be present in themX =ΔVo× f, wherein f are the feedback factor of the level production line circuit.It is specific for one-level
Flow line circuit, its feedback factor is substantially constant, therefore can utilize the remainder error of stage circuit summing junction to the level
The transformed error of circuit compensates.
The content of the invention
It is an object of the invention to provide a kind of correction electricity suitable for the production line analog-digital converter based on Zero-cross comparator
Road and method, it can realize the compensation to this grade of circuit conversion error according to the remainder error of stage circuit summing junction, from
And effectively improve the conversion accuracy of circuit.
The correcting circuit of production line analog-digital converter provided by the invention, its structure are as shown in Figure 2.The correcting circuit
200 are connected between the two-stage circuit 211,212 of the production line analog-digital converter based on Zero-cross comparator, and correcting circuit 200 includes
One difference 1/f error amplifiers 220, one first correction electric capacity 201, one second correction electric capacity 202, one first transmission gate electricity
Road 203, one second transmission gate circuit 204；Wherein：
Difference 1/f error amplifiers 220 have a positive input terminal, a negative input end, a positive output end and a negative output terminal；
First correction electric capacity 201 has a top crown end and once plate end；Second correction has on one with electric capacity 202
Plate end and once plate end；
Each transmission gate circuit 203,204 includes a n type field effect transistor and a p type field effect transistor, both ditches
Road parallel arrangement, both drain electrode ends are interconnected to constitute the drain electrode end of transmission gate circuit, and source terminal is interconnected to constitute transmission
The source terminal of gate circuit, the gate terminal of n type field effect transistor form the N gate terminals of transmission gate circuit, p type field effect transistor
Gate terminal form transmission gate circuit P-gate it is extreme.
In the present invention, the positive input terminal of the difference 1/f error amplifiers 220 is connected to the streamline based on Zero-cross comparator
The positive summing junction 207 of the front stage circuits 211 of analog-digital converter, negative input end are connected to the streamline modulus based on Zero-cross comparator
The negative summing junction 208 of the front stage circuits 211 of converter；The negative output terminal of difference 1/f error amplifiers 220 is connected to the first correction
With the bottom crown end of electric capacity 201, one first switching node 205 is formed；Positive output end is connected under the second correction electric capacity 202
Plate end, form one second switching node 206；Above-mentioned connected mode is to by the conversion of production line analog-digital converter front stage circuits
Error is stored on the first correction electric capacity 201 and the second correction electric capacity 202.
In the present invention, the first correction is connected to the negative output terminal of difference 1/f amplifiers 220 with the bottom crown end of electric capacity 201, i.e., and
One switching node 205；First correction is connected to the production line analog-digital converter based on Zero-cross comparator with the top crown end of electric capacity 201
The positive summing junction 209 of late-class circuit 212；Second correction is being connected to difference 1/f amplifiers 220 just with the bottom crown end of electric capacity 202
Output end, i.e. the second switching node 206；Second correction is connected to the streamline based on Zero-cross comparator with the top crown end of electric capacity 202
The negative summing junction 210 of the late-class circuit 212 of analog-digital converter；Before above-mentioned connected mode is to receive production line analog-digital converter
The transformed error of level circuit 211, then by the change-over error compensation of front stage circuits 211 into late-class circuit 212.
In the present invention, the drain electrode end of the first transmission gate 203 is connected to the bottom crown end of the first correction electric capacity 201, i.e. the first coupling
Close node 205；The source terminal of first transmission gate 203 is connected to common mode electrical level；The drain electrode end of second transmission gate 204 is connected to the second correction
With the bottom crown end of electric capacity 202, i.e. the second switching node 206；The source terminal of second transmission gate 204 is connected to common mode electrical level；First passes
The N gate terminals of defeated door are connected with the N gate terminals of the second transmission gate, a N Enable Pins are formed, to receive an enable signal；First
The P-gate of transmission gate is extremely extremely connected with the P-gate of the second transmission gate, a P Enable Pins is formed, to receive an enable signal.
In the present invention, the first correction is equal with the correction of electric capacity 201 and second capacitance of electric capacity 202, symmetry arrangement arranged side by side.
The present invention further provides the production line analog-digital converter based on Zero-cross comparator is entered using above-mentioned correcting circuit 200
The method of row correction, is comprised the following steps that：
First, in the first clock phase φ1Portion of time in, N levels circuit 211 is established, N+1 level circuits
212 sampling N levels circuits 211 establish result, and the summing junction 207,208 of N+1 levels circuit 212 is connected to altogether by switch
Mould level, enable signal make two transmission being connected across between correction electric capacity 201,202 bottom crowns 205,206 and common mode electrical level
Door 203,204 is also both turned on, and correction is initialized with electric capacity 201,202.After the completion of N levels circuit 211 is established, in N levels
There will be remainder error between the positive and negative summing junction 207,208 of circuit 211, the conversion that this error is equal to N levels circuit 211 misses
Poor Δ and the feedback factor f of N levels circuit 211NProduct.In φ1Remaining time in, the summing junction of N+1 levels circuit 212
209th, the switch between 210 and common mode electrical level continues to be held on, and two corrections top crown of electric capacity 201,202 continues with the
The summing junction 209,210 of N+1 level circuits is connected to common mode electrical level, is connected across correction electric capacity 201,202 bottom crowns 205,206
Two transmission gates 203,204 between common mode electrical level are turned off, and difference 1/f error amplifiers 220 are inputted end 207,208
Remainder error amplify a fixed gain AS, it is stored on two correction electric capacity 201,202.It is worth noting that,
This period can carry out 212 sub- ADC of N+1 levels circuit transfer process simultaneously.Because this measure can provide ratio for sub- ADC
The longer conversion time of known schemes, therefore the rate request to sub- adc circuit can be reduced.When in another clock phase
φ2When, the bottom crown 205,206 of two correction electric capacity 201,202 is connected to common mode electricity by two transmission gates 203,204
Flat, the transformed error of the N levels circuit 211 stored thereon just establishes process compensation to N+ with N+1 levels circuit 212
1 grade of establishing in result for circuit 212 is gone.
In order to realize to the accurate compensation of error, it is necessary to meet following relation：AS/fN= (C1,N+1+ C2,N+1)/CC,N, its
Middle ASFor the gain of difference 1/f error amplifiers 220, fNFor the feedback factor of N levels circuit 211, CC,NFor two correction electricity consumptions
Hold 201,202 capacitance, C1,N+1And C2,N+1For the capacitance of two groups of sampling capacitances of N+1 levels circuit 212.
From described above, each specifically based in the production line analog-digital converter of Zero-cross comparator, before any
Above-mentioned correcting circuit can be used between connected two-stage circuit afterwards, each correcting circuit can be by coupled previous stage electricity
The change-over error compensation on road is into rear stage circuit.While what deserves to be explained is, due to the similitude of transformed error, the present invention
The bearing calibration of offer is not limited in effective to the production line analog-digital converter based on Zero-cross comparator, and it is to conventional pipeline mould
Number converter is equally effective.
Bearing calibration of the present invention, go for various types of streams including the scheme based on Zero-cross comparator
When pipeline analog-to-digital converter, circuit conversion precision can be effectively improved, while the conversion longer than traditional scheme is provided to sub- ADC
Between, so as to reduce its circuit realiration difficulty.
Foregoing teachings substantially describe the present invention feature and technological merit, it is cited below particularly go out embodiment, to brighter
Illustrate the thought of the present invention clearly.Any those of ordinary skill in the art are it will be understood that can be according to disclosed
The framework for realizing the identical purpose of the present invention is designed in idea and specific embodiment modification, and this equal framework is without departing from this hair
Spirit and scope defined in bright appended claims.
Brief description of the drawings
Fig. 1 is the two-stage circuit structure chart of the production line analog-digital converter based on Zero-cross comparator.
Fig. 2 is schematic diagram of the correcting circuit provided by the invention in the production line analog-digital converter based on Zero-cross comparator.
When Fig. 3 is the work of the production line analog-digital converter based on Zero-cross comparator comprising correcting circuit provided by the invention
Sequence figure.
Fig. 4 is difference 1/f error amplifier circuit structure charts.
Label in figure：
101 be the N level circuits in the production line analog-digital converter based on Zero-cross comparator；102 be based on Zero-cross comparator
N+1 level circuits in production line analog-digital converter；100 be difference zero-crossing comparator；103 ~ 106 are followed successively by N level circuits
Sampling capacitance C1+、C1-And C2+、C2-；107 ~ 110 are followed successively by the sampling capacitance C of N+1 level circuits3+、C3- , C4+、C4- ；111 are
The sampling switch M of N level circuits1；112 be the sampling switch M of N+1 level circuits4；113 be the positive channel presetting of N level circuits
Transistor M2；114 be the negative channel presetting transistor M of N level circuits3；115 ~ 118 are followed successively by the current source in N level circuits
I1+、I1-, I2+、I2-；119 ~ 122 are followed successively by the current source I in N+1 level circuits3+、I3-、I4+、I4 -；
211 be the N level circuits of the production line analog-digital converter based on Zero-cross comparator；212 be the stream based on Zero-cross comparator
The N+1 level circuits of pipeline analog-to-digital converter；200 be the N level correcting circuits being connected between two-stage circuit；220 be difference
1/f error amplifiers；201st, 202 be two correction electric capacity CC+,N、CC-,N；203rd, 204 be two transmission gate circuit TG+,N、
TG- ,N；205th, 206 be two switching nodes；207th, 208 be N level circuits positive and negative summing junction X+,N、X - ,N；209、210
For the positive and negative summing junction X of N+1 level circuits+,N+1 、X-,N+1；
401st, 402 for difference 1/f error amplifiers input to pipe；403rd, 404 be with inputting two that pipe is connected
PMOS；405th, 406 be two variable resistors realized by switch resistance array；407th, 408 be difference 1/f error amplifiers
Two difference output ends；409 be bias current sources；410 be the switching node that two PMOS grid ends are connected to form.
Embodiment
Bearing calibration provided by the invention is described in detail below in conjunction with the accompanying drawings.It is worth noting that, the present invention carries
The bearing calibration of confession can be implemented in a number of different ways, and Examples below is an allusion quotation of bearing calibration provided by the invention
Type realizes circuit, only to illustrate the formation and use of the present invention, is not limited to the present invention.
Employ the two-stage circuit of the production line analog-digital converter based on Zero-cross comparator of bearing calibration provided by the invention
As shown in Fig. 2 it includes：N level production lines circuit 211, the N+1 level production lines based on Zero-cross comparator based on Zero-cross comparator
Circuit 212, N levels correcting circuit 200；
Wherein N levels correcting circuit includes：Electric capacity C is used in 220, two corrections of difference 1/f error amplifiersC+,N201、CC-, N202, two transmission gate circuit TG+,N203、TG- ,N204。
Two differential input ends of difference 1/f error amplifiers 220 are respectively connecting to production line analog-digital converter N levels electricity
The positive and negative summing junction X on road 211+,N207、X—,N208；Two difference output ends of difference 1/f error amplifiers 220 intersect respectively
It is connected to two correction electric capacity CC+,N201、CC-,N202 bottom crown end 205,206, i.e. negative output terminal are connected to the first correction
With electric capacity CC+,N201 bottom crown end 205, positive output end are connected to the second correction electric capacity CC-,N202 bottom crown end 206；Two
Electric capacity C is used in individual correctionC+,N201、CC-,N202 top crown end is respectively connecting to the positive and negative summing junction of N+1 levels circuit 212
X+,N+1209、X—,N+1210；Two transmission gate TG+,N203、TG- ,N204 are connected across two correction electric capacity C respectivelyC+,N201、
CC-,NBetween 202 bottom crown end 205,206 and common mode electrical level, both N grid ends short circuits are receiving control enable signal
Ea+,N, both P-gate end short circuits are receiving anti-phase control enable signal Ea-,N。
The working timing figure of the embodiment with reference to the timing diagram to its course of work as shown in figure 3, be explained as follows：
（1）Above-mentioned production line analog-digital converter works under two-phase non-overlapp-ing clock control, phase1With φ2With isometric
Time T1=T2=T T3, non-overlapped time T3 be present between them.
（2）First in the first clock phase φ1Portion of time in, N level production lines circuit 211 be in established
Journey, the sampling N levels of N+1 levels circuit 212 circuit 211 establish result, the summing junction X of N+1 levels circuit 212+,N+1209、
X—,N+1210 are connected to common mode electrical level, difference enable signal E by switcha+,NAnd Ea-,NMake to be connected across correction electric capacity 201,202
Two transmission gates 203,204 between bottom crown 205,206 and common mode electrical level are also both turned on so that electric capacity 201,202 is used in correction
Initialization.
（3）After the completion of N levels circuit 211 is established, in the positive and negative summing junction X of N levels circuit 211+,N207、X—,N208 it
Between there will be remainder error, this error is equal to the conversion error delta and the feedback factor f of N levels circuit 211 of N levels circuit 211N's
Product.
（4）In φ1Remaining time in, the summing junction X of N+1 levels circuit 212+,N+1209、X—,N+1210 and common mode electrical level
Between switch continue to be held on, the bottom crown of two correction electric capacity 201,202 continues asking with N+1 levels circuit 212
And nodes X+,N+1209、X—,N+1210 are connected to common mode electrical level, are connected across correction electric capacity 201,202 bottom crowns 205,206 and are total to
Two transmission gates 203,204 between mould level are turned off, and difference 1/f error amplifiers 220 are inputted the surplus of end 207,208
Remaining error amplifies a fixed gain AS, it is stored on two correction electric capacity 201,202.In this period, simultaneously
Carry out the sub- ADC of N+1 levels circuit 212 transfer process.In traditional scheme, this process is typically distributed over two phase clock
Non-overlapped period T4 in carry out, this period generally it is shorter.Therefore the present embodiment can provide ratio tradition side for sub- ADC
The longer conversion time of case, so as to reduce the rate request to sub- adc circuit, such as the lower SAR of a power consumption can be used
Sub ADC replace the flash sub ADC in traditional scheme.
（5）Then another clock phase φ will be in2, into process of establishing, difference is enabled to be believed N+1 levels circuit 212
Number Ea+,NAnd Ea-,NMake two transmission gates being connected across between correction electric capacity 201,202 bottom crowns 205,206 and common mode electrical level
203rd, 204 it is both turned on, the bottom crown 205,206 of two correction electric capacity 201,202 is connected to by two transmission gates 203,204
Common mode electrical level, the transformed error of the N levels circuit 211 stored thereon just arrive with the process compensation of establishing of N+1 levels circuit 212
The establishing in result of N+1 levels circuit 212 is gone.
From described above, the summing junction X of N levels circuit 211±,N207th, the remainder error between 208 is equal to N
The conversion error delta and the feedback factor f of N levels circuit 211 of level circuit 211NProduct, wherein N levels circuit 211 conversion miss
The margin of error that poor Δ compensates for needs.The output of N levels circuit 211 will be by N+ when being transferred to the output of N+1 levels circuit 212
1 grade of amplification (C1,N+1+ C2,N+1)/ C2,N+1Times, and electricity consumption is corrected in N levels correcting circuit 200 and holds upper 201,202 voltage biography
By exaggerated C when being handed to the output of N+1 levels circuit 212C,N / C2,N+1Times.Therefore in order to which the conversion of N levels circuit 211 is missed
Poor Δ accurate compensation to N+1 levels circuit 212 output, it is necessary to meet following relation：AS/fN= (C1,N+1+C2,N+1)/CC,N, its
Middle ASFor the gain of difference 1/f error amplifiers 220, fNFor the feedback factor of N levels circuit 211, CC,NFor two correction electricity consumptions
Hold 201,202 capacitance, C1,N+1And C2,N+1For the capacitance of two groups of sampling capacitances of N+1 level circuits.
Because we can not accurately measure the feedback factor f of a certain particular electrical circuitN, therefore following methods can only be taken：It is first
First estimate a 1/fNValue, thus obtain an ASValue, realize by physical circuit of the above-mentioned parameter as circuit parameter；So
The output of post analysis circuit, the 1/f of estimation is constantly updated using such as LMS etc feedback algorithmNValue so that circuit it is defeated
It is less and less to go out error.
According to the above, the gain for also requiring difference 1/f error amplifiers 220 is adjustable, and one kind realizes circuit such as
Shown in Fig. 4.As seen from the figure, it is used as input to pipe by a pair of nmos differentials to pipe 401,402.Two PMOSs 403,404
Grid end is connected to form a switching node 410, and source electrode is connected with power supply, the drain terminal drain terminal with two NMOS tubes 401,402 respectively
It is connected, forms two difference output ends 407,408 of difference 1/f error amplifiers.Current source 409 provides electricity for whole circuit
Stream biasing.Two variable resistors 405,406 are connected across two difference output ends of circuit 407,408 and PMOS 403,404 respectively
Between grid end switching node 410.The circuit realizes adjustable gain, variable resistor by adjusting above-mentioned variable resistor 405,406
Realized by the electric resistance array by switch control, therefore minimum change scale be present.The linear conditions of correction require that difference 1/f is missed
The gain of poor amplifier 220 is held essentially constant in the output area of its work.Due to every level production line circuit summing junction
Remainder error it is generally little, therefore difference 1/f error amplifiers work output area it is generally also little, to the linear of gain
It is required that it is readily obtained satisfaction.
What deserves to be explained is Fig. 2 show but N level production lines circuit 211, N+1 level production lines circuit 212 and
N levels correcting circuit 200, but for the entirely production line analog-digital converter based on Zero-cross comparator, any front and rear connected
Two-stage flow line circuit between above-mentioned correcting circuit can be used, each correcting circuit can be by coupled previous stage stream
The change-over error compensation of waterline circuit is into rear stage flow line circuit.While what deserves to be explained is, due to based on zero passage ratio
Compared with the transformed error of production line analog-digital converter and the transformed error of conventional pipeline analog-digital converter similitude be present, therefore
Bearing calibration provided by the invention is not limited in effective to the production line analog-digital converter based on Zero-cross comparator, and it is to conventional flow
Pipeline analog-to-digital converter is equally effective.
Although present disclosure and advantage disclose as above in detail, but should be noted that, the scope of the present invention is simultaneously
The specific embodiments such as method and step described in this description are not only restricted to, without departing from the spirit and scope of the present invention,
Any those of ordinary skill in the art can all make many deformations and modification according to disclosed content, and these should also be regarded
For protection scope of the present invention.
Claims (2)
- A kind of 1. correcting circuit suitable for the production line analog-digital converter based on Zero-cross comparator, it is characterised in that the correction Circuit（200）It is connected to the two-stage circuit of the production line analog-digital converter based on Zero-cross comparator（211、212）Between, correcting circuit （200）Including a difference 1/f error amplifiers（220）, one first correction electric capacity（201）, one second correction electric capacity （202）, one first transmission gate circuit（203）, one second transmission gate circuit（204）；Wherein：Difference 1/f error amplifiers（220）With a positive input terminal, a negative input end, a positive output end and a negative output terminal；First correction electric capacity（201）Plate end with a top crown end and once；Second correction electric capacity（202）On one Plate end and once plate end；Each transmission gate circuit（203、204）Include a n type field effect transistor and a p type field effect transistor, both raceway grooves Parallel arrangement, both drain electrode ends are interconnected to constitute the drain electrode end of transmission gate circuit, and source terminal is interconnected to constitute transmission gate The source terminal of circuit, the gate terminal of n type field effect transistor form the N gate terminals of transmission gate circuit, p type field effect transistor The P-gate that gate terminal forms transmission gate circuit is extreme；Difference 1/f error amplifiers（220）Positive input terminal be connected to the production line analog-digital converter based on Zero-cross comparator before Level circuit（211）Positive summing junction（207）, before negative input end is connected to the production line analog-digital converter based on Zero-cross comparator Level circuit（211）Negative summing junction（208）；Difference 1/f error amplifiers（220）Negative output terminal is connected to the first correction electricity consumption Hold（201）Bottom crown end, formed one first switching node（205）；Positive output end is connected to the second correction electric capacity（202）'s Bottom crown end, form one second switching node（206）；So, the transformed error of production line analog-digital converter front stage circuits is deposited It is stored in the first correction electric capacity（201）With the second correction electric capacity（202）On；First correction electric capacity（201）Bottom crown end is connected to difference 1/f amplifiers（220）Negative output terminal, i.e., the first coupling section Point（205）；First correction electric capacity（201）Top crown end is connected to the rear class of the production line analog-digital converter based on Zero-cross comparator Circuit（212）Positive summing junction（209）；Second correction electric capacity（202）Bottom crown end is connected to difference 1/f amplifiers （220）Positive output end, i.e. the second switching node（206）；Second correction electric capacity（202）Top crown end is connected to based on zero passage ratio Compared with production line analog-digital converter late-class circuit（212）Negative summing junction（210）；Above-mentioned connected mode is receiving flowing water Line analog-digital converter front stage circuits（211）Transformed error, then by front stage circuits（211）Change-over error compensation to late-class circuit （212）In；First transmission gate（203）Drain electrode end is connected to the first correction electric capacity（201）Bottom crown end, i.e. the first switching node （205）；First transmission gate（203）Source terminal is connected to common mode electrical level；Second transmission gate（204）Drain electrode end is connected to the second correction Use electric capacity（202）Bottom crown end, i.e. the second switching node（206）；Second transmission gate（204）Source terminal is connected to common mode electrical level； The N gate terminals of first transmission gate are connected with the N gate terminals of the second transmission gate, form a N Enable Pins, to receive an enabled letter Number；The P-gate of first transmission gate is extremely extremely connected with the P-gate of the second transmission gate, forms a P Enable Pins, enabled to receive one Signal.
- 2. correcting circuit as claimed in claim 1, it is characterised in that the first correction electric capacity（201）With the second correction electricity consumption Hold（202）Capacitance is equal, symmetry arrangement arranged side by side.
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| CN201410754786.6A CN104506191B (en) | 2014-12-11 | 2014-12-11 | The correcting circuit of production line analog-digital converter based on Zero-cross comparator and bearing calibration |
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| CN201410754786.6A CN104506191B (en) | 2014-12-11 | 2014-12-11 | The correcting circuit of production line analog-digital converter based on Zero-cross comparator and bearing calibration |
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| CN104506191B true CN104506191B (en) | 2017-11-17 |
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| CN107703468B (en) * | 2017-10-18 | 2023-12-01 | 厦门大学 | Driving circuit of gradient power amplifier of nuclear magnetic resonance apparatus |
| CN107733433B (en) * | 2017-11-13 | 2024-02-20 | 四川易冲科技有限公司 | Current source calibration device and method |
| CN107947794B (en) * | 2017-11-30 | 2021-02-26 | 无锡中微爱芯电子有限公司 | Error correction circuit for correcting offset error of analog-to-digital converter |
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| CN101192829A (en) * | 2007-12-19 | 2008-06-04 | 北京大学 | A forward error compensation and correction method and device for streamline analog/digital converter |
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